JPS5552235A - Fastening of semiconductor wafer on substrate - Google Patents

Fastening of semiconductor wafer on substrate

Info

Publication number
JPS5552235A
JPS5552235A JP12518078A JP12518078A JPS5552235A JP S5552235 A JPS5552235 A JP S5552235A JP 12518078 A JP12518078 A JP 12518078A JP 12518078 A JP12518078 A JP 12518078A JP S5552235 A JPS5552235 A JP S5552235A
Authority
JP
Japan
Prior art keywords
wafer
substrate
adhesive
grooves
exposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12518078A
Other languages
Japanese (ja)
Inventor
Michitoshi Sera
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12518078A priority Critical patent/JPS5552235A/en
Publication of JPS5552235A publication Critical patent/JPS5552235A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)
  • Dicing (AREA)

Abstract

PURPOSE: To provide an improved method for fastening a semiconductor wafer on a substrate in the formation of pellets thereform, which comprises providing a plurality of grooves in one surface of the wafer, putting the thus worked wafer on a substrate with the grooved surface downward, and adhesively bonding the attaching surfaces, followed by subjecting the resulting wafer to polishing and pellet-formation.
CONSTITUTION: A plurality of grooves are cut in one surface of a semiconductor wafer as shown in the drawing. The wafer thus worked is put on a substrate 4 of glass with the grooved surface downward, and the attaching surfaces are adhesively bonded using an adhesive. Then the other exposed surface of the wafer is subjected to lapping and polishing so that the groove lines become exposed. The exposed groove lines are covered by another glass substrate 6 with an instantly activating acrylic adhesive 7 forming a connecting layer inbetween. The substrate 4 with the adhesive wax is removed, using trichloroethylene or the like solvent. The grooves in the wafer are washed by the same solvent to remove the fragments of the wax remaining therein, while all excessive portions of the adhesive are washed off by a shower of acetone, to finally produce individual pellets of the semiconductor. The above method serves to make it available to easily obtain thinner wafers and form pellets therefrom with improved reliability.
COPYRIGHT: (C)1980,JPO&Japio
JP12518078A 1978-10-13 1978-10-13 Fastening of semiconductor wafer on substrate Pending JPS5552235A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12518078A JPS5552235A (en) 1978-10-13 1978-10-13 Fastening of semiconductor wafer on substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12518078A JPS5552235A (en) 1978-10-13 1978-10-13 Fastening of semiconductor wafer on substrate

Publications (1)

Publication Number Publication Date
JPS5552235A true JPS5552235A (en) 1980-04-16

Family

ID=14903868

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12518078A Pending JPS5552235A (en) 1978-10-13 1978-10-13 Fastening of semiconductor wafer on substrate

Country Status (1)

Country Link
JP (1) JPS5552235A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61112345A (en) * 1984-11-07 1986-05-30 Toshiba Corp Manufacture of semiconductor device
JPH04367250A (en) * 1991-06-14 1992-12-18 Sharp Corp Manufacture of semiconductor chip
JPH06224299A (en) * 1993-01-25 1994-08-12 Disco Abrasive Syst Ltd Dividing method for semiconductor wafer and dividing system
EP0981156A2 (en) * 1998-08-18 2000-02-23 Lintec Corporation Surface protective pressure-sensitive adhesive sheet for use in semiconductor wafer back grinding and method of use thereof
EP1014444A1 (en) * 1999-05-14 2000-06-28 Siemens Aktiengesellschaft Integrated circuit with protection layer and fabrication method therefor
US6184109B1 (en) 1997-07-23 2001-02-06 Kabushiki Kaisha Toshiba Method of dividing a wafer and method of manufacturing a semiconductor device
US6294439B1 (en) 1997-07-23 2001-09-25 Kabushiki Kaisha Toshiba Method of dividing a wafer and method of manufacturing a semiconductor device
US6337258B1 (en) 1999-07-22 2002-01-08 Kabushiki Kaisha Toshiba Method of dividing a wafer
EP1043772B1 (en) * 1999-04-09 2017-05-03 LAPIS Semiconductor Co., Ltd. Method for packaging and mounting semiconductor device

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61112345A (en) * 1984-11-07 1986-05-30 Toshiba Corp Manufacture of semiconductor device
JPH0554262B2 (en) * 1984-11-07 1993-08-12 Tokyo Shibaura Electric Co
JPH04367250A (en) * 1991-06-14 1992-12-18 Sharp Corp Manufacture of semiconductor chip
JPH06224299A (en) * 1993-01-25 1994-08-12 Disco Abrasive Syst Ltd Dividing method for semiconductor wafer and dividing system
US6184109B1 (en) 1997-07-23 2001-02-06 Kabushiki Kaisha Toshiba Method of dividing a wafer and method of manufacturing a semiconductor device
US6294439B1 (en) 1997-07-23 2001-09-25 Kabushiki Kaisha Toshiba Method of dividing a wafer and method of manufacturing a semiconductor device
EP0981156A2 (en) * 1998-08-18 2000-02-23 Lintec Corporation Surface protective pressure-sensitive adhesive sheet for use in semiconductor wafer back grinding and method of use thereof
EP0981156A3 (en) * 1998-08-18 2002-01-09 Lintec Corporation Surface protective pressure-sensitive adhesive sheet for use in semiconductor wafer back grinding and method of use thereof
US6465330B1 (en) 1998-08-18 2002-10-15 Lintec Corporation Method for grinding a wafer back
EP1043772B1 (en) * 1999-04-09 2017-05-03 LAPIS Semiconductor Co., Ltd. Method for packaging and mounting semiconductor device
EP1014444A1 (en) * 1999-05-14 2000-06-28 Siemens Aktiengesellschaft Integrated circuit with protection layer and fabrication method therefor
US6337258B1 (en) 1999-07-22 2002-01-08 Kabushiki Kaisha Toshiba Method of dividing a wafer

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