JPH0526216B2 - - Google Patents

Info

Publication number
JPH0526216B2
JPH0526216B2 JP58231105A JP23110583A JPH0526216B2 JP H0526216 B2 JPH0526216 B2 JP H0526216B2 JP 58231105 A JP58231105 A JP 58231105A JP 23110583 A JP23110583 A JP 23110583A JP H0526216 B2 JPH0526216 B2 JP H0526216B2
Authority
JP
Japan
Prior art keywords
buffer memory
address
read
request
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58231105A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60123944A (ja
Inventor
Satoshi Koga
Tsutomu Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58231105A priority Critical patent/JPS60123944A/ja
Priority to BR8406089A priority patent/BR8406089A/pt
Priority to CA000468354A priority patent/CA1228678A/en
Priority to AU35921/84A priority patent/AU550540B2/en
Priority to KR8407464A priority patent/KR900000480B1/ko
Priority to ES538096A priority patent/ES8606688A1/es
Priority to EP84402451A priority patent/EP0144268B1/en
Priority to DE3486276T priority patent/DE3486276T2/de
Publication of JPS60123944A publication Critical patent/JPS60123944A/ja
Priority to CA000526259A priority patent/CA1233273A/en
Priority to US07/073,372 priority patent/US4779193A/en
Priority to US07/073,281 priority patent/US4924425A/en
Publication of JPH0526216B2 publication Critical patent/JPH0526216B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP58231105A 1983-11-30 1983-12-07 情報処理装置におけるバツフアメモリ制御方式 Granted JPS60123944A (ja)

Priority Applications (11)

Application Number Priority Date Filing Date Title
JP58231105A JPS60123944A (ja) 1983-12-07 1983-12-07 情報処理装置におけるバツフアメモリ制御方式
BR8406089A BR8406089A (pt) 1983-11-30 1984-11-20 Processo para controlar memoria intermediaria em aparelho de processamento de dados
CA000468354A CA1228678A (en) 1983-11-30 1984-11-21 Method for controlling buffer memory in data processing apparatus
AU35921/84A AU550540B2 (en) 1983-11-30 1984-11-27 Method for controlling buffer memory in data processing apparatus
KR8407464A KR900000480B1 (en) 1983-11-30 1984-11-28 Buffer memory control method into data processing apparatus
ES538096A ES8606688A1 (es) 1983-11-30 1984-11-29 Procedimiento para controlar una memoria intermedia de un aparato de proceso de datos
EP84402451A EP0144268B1 (en) 1983-11-30 1984-11-30 Method for controlling buffer memory in data processing apparatus
DE3486276T DE3486276T2 (de) 1983-11-30 1984-11-30 Verfahren zum Steuern eines Pufferspeichers in einem Datenverarbeitungsgerät.
CA000526259A CA1233273A (en) 1983-11-30 1986-12-23 Method for controlling buffer memory in data processing apparatus
US07/073,372 US4779193A (en) 1983-11-30 1987-07-08 Data processing apparatus for writing calculation result into buffer memory after the writing of the beginning word of the read data
US07/073,281 US4924425A (en) 1983-11-30 1987-07-08 Method for immediately writing an operand to a selected word location within a block of a buffer memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58231105A JPS60123944A (ja) 1983-12-07 1983-12-07 情報処理装置におけるバツフアメモリ制御方式

Publications (2)

Publication Number Publication Date
JPS60123944A JPS60123944A (ja) 1985-07-02
JPH0526216B2 true JPH0526216B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-04-15

Family

ID=16918372

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58231105A Granted JPS60123944A (ja) 1983-11-30 1983-12-07 情報処理装置におけるバツフアメモリ制御方式

Country Status (1)

Country Link
JP (1) JPS60123944A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61224051A (ja) * 1985-03-29 1986-10-04 Fujitsu Ltd バッファメモリ制御方法
JPH07105128A (ja) * 1993-10-07 1995-04-21 Mitsubishi Electric Corp データ転送装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5323052B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1973-09-11 1978-07-12
JPS5489434A (en) * 1977-12-27 1979-07-16 Fujitsu Ltd Memory access control processing system

Also Published As

Publication number Publication date
JPS60123944A (ja) 1985-07-02

Similar Documents

Publication Publication Date Title
EP0144268B1 (en) Method for controlling buffer memory in data processing apparatus
JPH0410102B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPH0526216B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPS61224051A (ja) バッファメモリ制御方法
JPH01251248A (ja) スタックデータ構造用キャッシュ制御方式
JPS6135583B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPH02259945A (ja) ストア処理方式
JP2581144B2 (ja) バス制御装置
JP2636564B2 (ja) キャッシュメモリのムーブイン制御方式
JPS63311548A (ja) キャッシュメモリ制御回路
JPS62127943A (ja) 命令バツフア制御方式
JPH0322053A (ja) ムーブ・イン・バッファ制御方式
JPH0612363A (ja) メモリ制御装置およびマルチプロセッサシステム
JPH03271859A (ja) 情報処理装置
JPS6222165A (ja) 主記憶装置アクセス制御方式
JPS59195753A (ja) デイスク・キヤツシユメモリの制御方式
JPH0332820B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPS6046454B2 (ja) 情報転送装置
JPS6055454A (ja) デ−タ転送制御方式
JPS61211752A (ja) ペ−ジ履歴メモリ装置
JPS5815813B2 (ja) デ−タシヨリソウチ
JPS61235960A (ja) キヤツシユメモリの制御方法
JPH01233536A (ja) キャッシュメモリ書込み装置
JPH02267658A (ja) マルチプロセッサシステム
JPS59212960A (ja) プリフエツチ制御方式