JPH0474743B2 - - Google Patents

Info

Publication number
JPH0474743B2
JPH0474743B2 JP58062294A JP6229483A JPH0474743B2 JP H0474743 B2 JPH0474743 B2 JP H0474743B2 JP 58062294 A JP58062294 A JP 58062294A JP 6229483 A JP6229483 A JP 6229483A JP H0474743 B2 JPH0474743 B2 JP H0474743B2
Authority
JP
Japan
Prior art keywords
data
floating
mantissa
mode
exponent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58062294A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59188740A (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP58062294A priority Critical patent/JPS59188740A/ja
Priority to US06/599,167 priority patent/US4644490A/en
Publication of JPS59188740A publication Critical patent/JPS59188740A/ja
Publication of JPH0474743B2 publication Critical patent/JPH0474743B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G06F7/485—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3884—Pipelining

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
JP58062294A 1983-04-11 1983-04-11 フロ−テイング加算器 Granted JPS59188740A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP58062294A JPS59188740A (ja) 1983-04-11 1983-04-11 フロ−テイング加算器
US06/599,167 US4644490A (en) 1983-04-11 1984-04-11 Floating point data adder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58062294A JPS59188740A (ja) 1983-04-11 1983-04-11 フロ−テイング加算器

Publications (2)

Publication Number Publication Date
JPS59188740A JPS59188740A (ja) 1984-10-26
JPH0474743B2 true JPH0474743B2 (enExample) 1992-11-27

Family

ID=13195948

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58062294A Granted JPS59188740A (ja) 1983-04-11 1983-04-11 フロ−テイング加算器

Country Status (2)

Country Link
US (1) US4644490A (enExample)
JP (1) JPS59188740A (enExample)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60140422A (ja) * 1983-12-28 1985-07-25 Nec Corp 演算処理装置
JPS61213927A (ja) * 1985-03-18 1986-09-22 Hitachi Ltd 浮動小数点演算処理装置
JPH07104771B2 (ja) * 1985-05-10 1995-11-13 株式会社日立製作所 計算機
US4825400A (en) * 1986-01-13 1989-04-25 General Electric Company Floating point accumulator circuit
JPH0650462B2 (ja) * 1986-02-18 1994-06-29 日本電気株式会社 シフト数制御回路
US4751665A (en) * 1986-02-24 1988-06-14 International Business Machines Corporation Systolic super summation device
US4858166A (en) * 1986-09-19 1989-08-15 Performance Semiconductor Corporation Method and structure for performing floating point comparison
ES2026444T3 (es) * 1986-10-31 1992-05-01 International Business Machines Corporation Procedimiento y disposicion de circuitos para la suma de numeros de coma flotante.
JP2558669B2 (ja) * 1986-12-29 1996-11-27 松下電器産業株式会社 浮動小数点演算装置
US4858165A (en) * 1987-06-19 1989-08-15 Digital Equipment Corporation Apparatus and method for acceleration of effective subtraction procedures by the approximation of the absolute value of the exponent argument difference
US4852039A (en) * 1987-06-19 1989-07-25 Digital Equipment Corporation Apparatus and method for accelerating floating point addition and subtraction operations by accelerating the effective subtraction procedure
JPH01204138A (ja) * 1988-02-09 1989-08-16 Nec Corp 演算回路
JP2695178B2 (ja) * 1988-03-11 1997-12-24 富士通株式会社 演算回路
JPH0776911B2 (ja) * 1988-03-23 1995-08-16 松下電器産業株式会社 浮動小数点演算装置
JP2693800B2 (ja) * 1988-12-28 1997-12-24 甲府日本電気株式会社 浮動小数点データ総和演算回路
US4943941A (en) * 1989-01-13 1990-07-24 Bolt Beranek And Newman Inc. Floating point processor employing counter controlled shifting
US4994996A (en) * 1989-02-03 1991-02-19 Digital Equipment Corporation Pipelined floating point adder for digital computer
US5103418A (en) * 1989-11-20 1992-04-07 Motorola, Inc. Dangerous range detector for floating point adder
US5117384A (en) * 1990-01-24 1992-05-26 International Business Machines Corporation Method and apparatus for exponent adder
US5111421A (en) * 1990-02-26 1992-05-05 General Electric Company System for performing addition and subtraction of signed magnitude floating point binary numbers
JPH0520028A (ja) * 1990-12-28 1993-01-29 Matsushita Electric Ind Co Ltd 加減算のための浮動小数点演算装置の仮数部処理回路
EP0551531A1 (en) * 1991-12-20 1993-07-21 International Business Machines Corporation Apparatus for executing ADD/SUB operations between IEEE standard floating-point numbers
JPH0816364A (ja) * 1994-04-26 1996-01-19 Nec Corp カウンタ回路とそれを用いたマイクロプロセッサ
US6941335B2 (en) * 2001-11-29 2005-09-06 International Business Machines Corporation Random carry-in for floating-point operations
CN101438232B (zh) * 2006-05-16 2015-10-21 英特尔公司 不同浮点格式的浮点加法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3551665A (en) * 1966-09-13 1970-12-29 Ibm Floating point binary adder utilizing completely sequential hardware
US3697734A (en) * 1970-07-28 1972-10-10 Singer Co Digital computer utilizing a plurality of parallel asynchronous arithmetic units
US4075704A (en) * 1976-07-02 1978-02-21 Floating Point Systems, Inc. Floating point data processor for high speech operation
JPS54157050A (en) * 1978-05-31 1979-12-11 Matsushita Electric Works Ltd Difference operation circuit
US4229801A (en) * 1978-12-11 1980-10-21 Data General Corporation Floating point processor having concurrent exponent/mantissa operation
US4218751A (en) * 1979-03-07 1980-08-19 International Business Machines Corporation Absolute difference generator for use in display systems
US4562553A (en) * 1984-03-19 1985-12-31 Analogic Corporation Floating point arithmetic system and method with rounding anticipation

Also Published As

Publication number Publication date
US4644490A (en) 1987-02-17
JPS59188740A (ja) 1984-10-26

Similar Documents

Publication Publication Date Title
JPH0474743B2 (enExample)
US5027308A (en) Circuit for adding/subtracting two floating point operands
US5197023A (en) Hardware arrangement for floating-point addition and subtraction
US5010508A (en) Prenormalization for a floating-point adder
US5568412A (en) Rounding-off method and apparatus of floating point arithmetic apparatus for addition/subtraction
US7720898B2 (en) Apparatus and method for adjusting exponents of floating point numbers
US6205462B1 (en) Digital multiply-accumulate circuit that can operate on both integer and floating point numbers simultaneously
JP2689414B2 (ja) 浮動小数点表現変換器
US20100174764A1 (en) Reuse of rounder for fixed conversion of log instructions
US7401107B2 (en) Data processing apparatus and method for converting a fixed point number to a floating point number
EP0332215B1 (en) Operation circuit based on floating-point representation
KR19980082906A (ko) 부동 소수점 숫자의 정수형으로의 변환 방법
JPH0511980A (ja) 桁あふれ検出方式とその回路
JPS63167930A (ja) 浮動小数点演算装置
JP2006318382A (ja) 演算装置および型変換装置
JP2801472B2 (ja) 浮動小数点演算装置
JP2002023997A (ja) 浮動小数点演算のための選択ベースの丸め方法
JP2555135B2 (ja) 演算回路
JPH0216632A (ja) 固定小数点数−浮動小数点数変換回路
JPS63158626A (ja) 演算処理装置
JPH0823810B2 (ja) 浮動小数点演算回路
JPS5960637A (ja) 浮動小数点演算装置
JPH0383126A (ja) 浮動小数点乗算器
JPH0413734B2 (enExample)
JP3124286B2 (ja) 浮動小数点数演算装置