JPH0455333B2 - - Google Patents

Info

Publication number
JPH0455333B2
JPH0455333B2 JP60189759A JP18975985A JPH0455333B2 JP H0455333 B2 JPH0455333 B2 JP H0455333B2 JP 60189759 A JP60189759 A JP 60189759A JP 18975985 A JP18975985 A JP 18975985A JP H0455333 B2 JPH0455333 B2 JP H0455333B2
Authority
JP
Japan
Prior art keywords
pad
bonding
transistor
pads
switching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60189759A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6251231A (ja
Inventor
Kimiaki Sato
Yoshihiro Takemae
Shigeki Nozaki
Masao Nakano
Osami Kodama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60189759A priority Critical patent/JPS6251231A/ja
Publication of JPS6251231A publication Critical patent/JPS6251231A/ja
Publication of JPH0455333B2 publication Critical patent/JPH0455333B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
JP60189759A 1985-08-30 1985-08-30 半導体集積回路装置 Granted JPS6251231A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60189759A JPS6251231A (ja) 1985-08-30 1985-08-30 半導体集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60189759A JPS6251231A (ja) 1985-08-30 1985-08-30 半導体集積回路装置

Publications (2)

Publication Number Publication Date
JPS6251231A JPS6251231A (ja) 1987-03-05
JPH0455333B2 true JPH0455333B2 (it) 1992-09-03

Family

ID=16246700

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60189759A Granted JPS6251231A (ja) 1985-08-30 1985-08-30 半導体集積回路装置

Country Status (1)

Country Link
JP (1) JPS6251231A (it)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2605687B2 (ja) * 1986-04-17 1997-04-30 三菱電機株式会社 半導体装置
KR100465872B1 (ko) * 1997-09-04 2005-05-17 삼성전자주식회사 오픈드레인및풀업회로
JP4246237B2 (ja) 2007-02-05 2009-04-02 株式会社オーバル ポンプユニット式サーボ型容積流量計

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS609134A (ja) * 1983-06-29 1985-01-18 Fujitsu Ltd 半導体装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS609134A (ja) * 1983-06-29 1985-01-18 Fujitsu Ltd 半導体装置

Also Published As

Publication number Publication date
JPS6251231A (ja) 1987-03-05

Similar Documents

Publication Publication Date Title
JP2605687B2 (ja) 半導体装置
JP2000223652A (ja) 半導体チップおよびマルチチップ型半導体装置
US5331200A (en) Lead-on-chip inner lead bonding lead frame method and apparatus
JPH088330B2 (ja) Ｌｏｃ型リードフレームを備えた半導体集積回路装置
KR940001335A (ko) 반도체 집적 회로 장치
JPS62224034A (ja) 半導体装置
JPH04307943A (ja) 半導体装置
KR100194312B1 (ko) 정전 파괴 보호 회로를 구비한 반도체 디바이스
JP2560805B2 (ja) 半導体装置
US4572972A (en) CMOS Logic circuits with all pull-up transistors integrated in separate chip from all pull-down transistors
JP2983620B2 (ja) 半導体装置及びその製造方法
JPH09120974A (ja) 半導体装置
JPH0455333B2 (it)
US6201308B1 (en) Semiconductor chip having a low-noise ground line
JPH0763066B2 (ja) 半導体装置
JPH04349640A (ja) アナログ・デジタル混在集積回路装置実装体
JP2890269B2 (ja) 半導体装置
JP3692186B2 (ja) 半導体装置
US5389577A (en) Leadframe for integrated circuits
JPH06163700A (ja) 集積回路装置
JP3030951B2 (ja) 半導体集積装置
JP2524967Y2 (ja) ワイヤボンデイング実装体
JPH0770666B2 (ja) 集積回路装置実装パツケ−ジ
JP2522455B2 (ja) 半導体集積回路装置
JPS60154644A (ja) 半導体装置