JPH0455333B2 - - Google Patents
Info
- Publication number
- JPH0455333B2 JPH0455333B2 JP60189759A JP18975985A JPH0455333B2 JP H0455333 B2 JPH0455333 B2 JP H0455333B2 JP 60189759 A JP60189759 A JP 60189759A JP 18975985 A JP18975985 A JP 18975985A JP H0455333 B2 JPH0455333 B2 JP H0455333B2
- Authority
- JP
- Japan
- Prior art keywords
- pad
- bonding
- transistor
- pads
- switching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 14
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
〔概要〕
この発明は同一機能を有するボンデイングパツ
ドを複数個有する半導体チツプにおいて、ボンデ
イングパツドとチツプの内部回路との間にパツド
切換手段を設けて、使用しないボンデイングパツ
ドを電気的に切り離すことにより入力容量を低減
したものであり、パツケージの種類によつてボン
デイングパツドを容易に使い分けることができる
ようにしたものである。[Detailed Description of the Invention] [Summary] The present invention provides a pad switching means between the bonding pad and the internal circuit of the chip in a semiconductor chip having a plurality of bonding pads having the same function, so that unused bonding The input capacitance is reduced by electrically separating the pads, and it is possible to easily use different bonding pads depending on the type of package.
本発明は半導体集積回路装置に関し、特に、同
一機能のボンデイングパツド（パツド）を複数個
有する半導体チツプ（チツプ）において、パツケ
ージの種類によりパツドを容易に使い分けること
ができ、かつ使用していないパツドを電気的に切
り離すことにより入力容量を低減するようにした
半導体集積回路装置に関する。
The present invention relates to a semiconductor integrated circuit device, and in particular, in a semiconductor chip (chip) having a plurality of bonding pads (pads) having the same function, it is possible to easily use different bonding pads depending on the type of package, and to remove unused pads. The present invention relates to a semiconductor integrated circuit device in which input capacitance is reduced by electrically disconnecting.
既に知られるように、チツプの周囲に配設され
たパツドとパツケージのフレームポストとの間は
金（Au）製のボンデイングワイヤ（ワイヤ）に
より接続される。そしてフレームはパツケージの
外部端子としてのピンに接続される。この場合、
比較的面積の大なるチツプをセラミツクあるいは
プラスチツクの何種類ものパツケージに搭載する
場合、各々のパツケージごとにフレームの形状が
異なり、このフレームの形状とチツプ内部回路の
回路配置との整合性によりワイヤが届かなかつた
りあるいは長過ぎで接触等の不良原因となること
がある。そのため、第４図に示すようにチツプ内
部に配線ｌにより接続されている複数個のパツド
P1，P2を設けてパツケージの種類により使い分
け、ワイヤＷが最短距離のパツドとフレームＦの
ポストＰとの間で接続可能なようにしている。
As is already known, bonding wires made of gold (Au) connect pads disposed around the chip and frame posts of the package. The frame is then connected to pins serving as external terminals of the package. in this case,
When a chip with a relatively large area is mounted on several types of ceramic or plastic packages, the shape of the frame is different for each package, and the wires may be wired depending on the compatibility between the shape of the frame and the circuit layout of the chip's internal circuitry. If it does not reach or is too long, it may cause contact failure. Therefore, as shown in Fig. 4, there are multiple pads connected by wiring l inside the chip.
P 1 and P 2 are provided and used depending on the type of package, so that the wire W can be connected between the shortest pad and the post P of the frame F.
しかしながら、このような場合、追加したパツ
ドの個数分がけパツド自身の容量C1とその間の
配設の容量C2，C3が増大するという問題がある。
この容量は外部から見て入力容量となるために外
部に対して負荷が重くなり、例えばTTL回路で
はスイツチング特性が悪化する等の種々の影響を
与えている。 However, in such a case, there is a problem in that the capacitance C 1 of the pad itself and the capacitances C 2 and C 3 of the pads disposed between them increase by the number of pads added.
This capacitance becomes an input capacitance when viewed from the outside, so it places a heavy load on the outside, and has various effects such as deterioration of switching characteristics in a TTL circuit, for example.
本発明は同一機能のボンデイングパツドを複数
個有する半導体集積回路装置において、該ボンデ
イングパツドと内部回路との間に使用しないボン
デイングパツドを電気的に切り離すパツド切換手
段を備え、該パツド切換手段は、切換用ボンデイ
ングパツドと、ゲートが該切換用ボンデイングパ
ツドに接続され一端がボンデイングパツドに接続
されたトランジスタと、ゲートがインバータを介
して該切換用ボンデイングパツドに接続され一端
がボンデイングパツドに接続され他端がトランジ
スタの他端に共通接続されたトランジスタと、該
内部回路に接続された該共通接続端とを備え、パ
ツケージの種類に応じて該ボンデイングパツドを
使い分けるようにしたことを特徴とする。
The present invention provides a semiconductor integrated circuit device having a plurality of bonding pads having the same function, comprising pad switching means for electrically separating unused bonding pads between the bonding pads and an internal circuit; The transistor includes a switching bonding pad, a transistor having a gate connected to the switching bonding pad and one end connected to the bonding pad, and a transistor having a gate connected to the switching bonding pad via an inverter and one end connected to the bonding pad. A transistor is connected to the bonding pad and the other end is commonly connected to the other end of the transistor, and the common connection end is connected to the internal circuit, and the bonding pad is used depending on the type of package. It is characterized by
第１図は本発明に係る一実施例半導体チツプの
要部構成図である。第１図において、CHIPは半
導体チツプ、P1，P2はパツド、PCUTは切換用パツ
ド、PVCCは電源用パツドである。また、SWCは
パツド切換回路、Ａは内部回路である。
FIG. 1 is a diagram showing the main part of a semiconductor chip according to an embodiment of the present invention. In FIG. 1, CHIP is a semiconductor chip, P 1 and P 2 are pads, P CUT is a switching pad, and PV CC is a power supply pad. Also, SWC is a pad switching circuit, and A is an internal circuit.
第２図は第１図のパツド切換回路の詳細回路図
である。T1およびT4はデイプレシヨン形Ｎ−チ
ヤネルMOSトランジスタ、T2，T3，T5はエンハ
ンスメント形Ｎ−チヤネルMOSトランジスタで
ある。T3，T5によりインバータ回路を構成する。 FIG. 2 is a detailed circuit diagram of the pad switching circuit of FIG. 1. T1 and T4 are depletion type N-channel MOS transistors, and T2 , T3 , and T5 are enhancement type N-channel MOS transistors. T 3 and T 5 constitute an inverter circuit.
このような構成において、パツド切換回路
SWCの動作を第１，２図を参照しつつ詳細に説
明する。パツドP1と内部回路Ａを接続する場合
には次のようになる。即ち、外部電源VCCとパツ
ドPVCCとのワイヤボンデイングの他にパツド
PCUTともワイヤボンデイングする。これにより配
線l1は電源VCCとなりハイ（Ｈ）レベルとなる。
デイプレシヨン型のトランジスタT1はそのゲー
トが接地電源VSSに接続されており常時オン状態
であるが、オン抵抗を高く設定することにより配
線l1のレベルの低下はほとんどない。トランジス
タT2はそのゲートがＨレベルとなるのでオンし、
同様にトランジスタT3もオンする。トランジス
タT4はデイプレシヨン型のためオン状態である
が、トランジスタT3，T4のオン抵抗を適当に設
定して配線l2のレベルをトランジスタT5のしきい
値にみたないようにすることにより、トランジス
タT5はカツトオフとなる。従つてパツドP1と内
部回路Ａは導通するがパツドP2と内部回路Ａは
遮断される。 In such a configuration, the pad switching circuit
The operation of the SWC will be explained in detail with reference to FIGS. 1 and 2. The connection between pad P1 and internal circuit A is as follows. In other words, in addition to wire bonding between the external power supply V CC and the pad PV CC ,
Wire bond with P CUT . As a result, the wiring l1 becomes the power supply V CC and becomes high (H) level.
The depletion type transistor T1 has its gate connected to the ground power supply VSS and is always on, but by setting the on-resistance high, there is almost no drop in the level of the wiring l1 . Transistor T2 turns on because its gate becomes H level,
Similarly, transistor T3 is also turned on. Transistor T 4 is in the on state because it is a depresion type, but by appropriately setting the on resistance of transistors T 3 and T 4 so that the level of wiring l 2 does not reach the threshold of transistor T 5 . , transistor T5 is cut off. Therefore, pad P1 and internal circuit A are electrically connected, but pad P2 and internal circuit A are cut off.
一方、パツドP2と内部回路Ａを接続する場合
には次のようになる。即ち、外部電源VCCはパツ
ドPVCCとのワイヤボンデイングのみとし、パツ
ドPCUTとVCCを遮断する。これにより配線l1はト
ランジスタT1が前述の如く常時オンしているた
めにＬレベルとなる。従つてトランジスタT2，
T3はカツトオフし、配線l2はトランジスタT4を
通して充電されＨレベルとなる。従つてトランジ
スタT5はオンしパツドP1と内部回路Ａは遮断さ
れるが、パツドP2と内部回路Ａは導通する。 On the other hand, when connecting pad P2 and internal circuit A, the process is as follows. That is, the external power supply V CC is only wire bonded to the pad PV CC , and the pad P CUT and V CC are cut off. As a result, the wiring l1 becomes L level because the transistor T1 is always on as described above. Therefore the transistor T 2 ,
T3 is cut off, and the wiring l2 is charged through the transistor T4 and becomes H level. Therefore, transistor T5 is turned on and pad P1 and internal circuit A are cut off, but pad P2 and internal circuit A are electrically connected.
このようなパツド切換回路は追加のパツドが必
要な個所にのみ設ければよく、また他の追加のパ
ツドと共用することもできる。またパツドPCUTと
VCCとのワイヤボンデイングはマスタスライス工
程にて予めアルミ配線しておき、使用しないパツ
ドが明確になつた段階でそのまゝ残すかあるいは
遮断するようにしてもよい。 Such a pad switching circuit need only be provided where additional pads are needed, and can also be shared with other additional pads. Also with Patsudo P CUT
Wire bonding with V CC may be done in advance with aluminum wiring in the master slicing process, and left as is or cut off when it becomes clear which pads will not be used.
第３図は半導体チツプとフレームの関係を示す
図である。本発明に係るパツド切換回路を備えた
半導体チツプによれば、ボンデイングパツドとフ
レーム間のワイヤボンデイングを最短距離で実施
することができる。 FIG. 3 is a diagram showing the relationship between the semiconductor chip and the frame. According to the semiconductor chip equipped with the pad switching circuit according to the present invention, wire bonding between the bonding pad and the frame can be performed over the shortest distance.
本発明によれば、パツド切換回路を設けること
によつて、多種類のパツケージに対応でき、さら
に追加パツド間の配線による入力容量を低減する
ことができるので外部への影響を軽減することが
でき、かつ最短距離でワイヤボンデイングできる
のでボンデイングワイヤが届かなかつたり長過ぎ
ることによる不良をなくすことができる。
According to the present invention, by providing a pad switching circuit, it is possible to support many types of packages, and furthermore, it is possible to reduce the input capacitance due to wiring between additional pads, thereby reducing the influence on the outside. , and since wire bonding can be performed over the shortest distance, defects caused by the bonding wire not reaching or being too long can be eliminated.
第１図は本発明に係る半導体チツプの要部構成
図、第２図は第１図のパツド切換回路の詳細回路
図、第３図は半導体チツプとフレームとの関係を
示す概要平面図、および第４図は従来の半導体チ
ツプの要部構成図である。
（符号の説明）、Ｗ……ボンデイングワイヤ、
P1，P2，PCUT，PVCC……ボンデイングパツド、
SWC……パツド切換回路。
FIG. 1 is a block diagram of the main parts of a semiconductor chip according to the present invention, FIG. 2 is a detailed circuit diagram of the pad switching circuit of FIG. 1, FIG. 3 is a schematic plan view showing the relationship between the semiconductor chip and the frame, and FIG. 4 is a block diagram of the main parts of a conventional semiconductor chip. (Explanation of symbols), W...bonding wire,
P 1 , P 2 , P CUT , PV CC ... bonding pad,
SWC...Pad switching circuit.
Claims (1)
る半導体集積回路装置において、 該ボンデイングパツドと内部回路との間に、使
用しないボンデイングパツドを電気的に切り離す
パツド切換手段を備え、 該パツド切換手段は、 切換用ボンデイングパツドPCUTと、 ゲートが該切換用ボンデイングパツドに接続さ
れ、一端がボンデイングパツドP1に接続された
トランジスタT2と、 ゲートがインバータT3，T4を介して該切換用
ボンデイングパツドに接続され、一端がボンデイ
ングパツドP2に接続され、他端がトランジスタ
T2の他端に共通接続されたトランジスタT5と、 該内部回路に接続された該共通接続端とを備
え、 パツケージの種類に応じて該ボンデイングパツ
ドを使い分けるようにしたことを特徴とする半導
体集積回路装置。[Scope of Claims] 1. A semiconductor integrated circuit device having a plurality of bonding pads having the same function, comprising pad switching means for electrically separating unused bonding pads between the bonding pads and the internal circuit. , the pad switching means includes a switching bonding pad P CUT , a transistor T 2 whose gate is connected to the switching bonding pad and one end connected to the bonding pad P 1 , and an inverter T 3 whose gate is connected to the bonding pad P 1 . T4 is connected to the switching bonding pad, one end is connected to bonding pad P2 , and the other end is connected to the transistor.
It is characterized by comprising a transistor T5 commonly connected to the other end of T2 , and the common connection end connected to the internal circuit, and the bonding pad is selectively used depending on the type of package. Semiconductor integrated circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60189759A JPS6251231A (en) | 1985-08-30 | 1985-08-30 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60189759A JPS6251231A (en) | 1985-08-30 | 1985-08-30 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6251231A JPS6251231A (en) | 1987-03-05 |
| JPH0455333B2 true JPH0455333B2 (en) | 1992-09-03 |
Family
ID=16246700
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60189759A Granted JPS6251231A (en) | 1985-08-30 | 1985-08-30 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6251231A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2605687B2 (en) * | 1986-04-17 | 1997-04-30 | 三菱電機株式会社 | Semiconductor device |
| KR100465872B1 (en) * | 1997-09-04 | 2005-05-17 | 삼성전자주식회사 | Open Drain and Pull-Up Circuitry |
| JP4246237B2 (en) | 2007-02-05 | 2009-04-02 | 株式会社オーバル | Pump unit type servo type volumetric flow meter |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS609134A (en) * | 1983-06-29 | 1985-01-18 | Fujitsu Ltd | Semiconductor device |
-
1985
- 1985-08-30 JP JP60189759A patent/JPS6251231A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS609134A (en) * | 1983-06-29 | 1985-01-18 | Fujitsu Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6251231A (en) | 1987-03-05 |
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