JPH0347577B2 - - Google Patents

Info

Publication number
JPH0347577B2
JPH0347577B2 JP60181182A JP18118285A JPH0347577B2 JP H0347577 B2 JPH0347577 B2 JP H0347577B2 JP 60181182 A JP60181182 A JP 60181182A JP 18118285 A JP18118285 A JP 18118285A JP H0347577 B2 JPH0347577 B2 JP H0347577B2
Authority
JP
Japan
Prior art keywords
layer
region
source
substrate
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60181182A
Other languages
English (en)
Other versions
JPS61159768A (ja
Inventor
Tsuu Ho Aabingu
Raizuman Jeikabu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS61159768A publication Critical patent/JPS61159768A/ja
Publication of JPH0347577B2 publication Critical patent/JPH0347577B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/131—Reactive ion etching rie

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Bipolar Transistors (AREA)
  • Drying Of Semiconductors (AREA)

Description

【発明の詳細な説明】 Ａ 産業上の利用分野 本発明は電界効果トランジスタの製造方法に関
する。
Ｂ 従来技術及びその問題点 電界効果トランジスタ（FET）の性能を向上
させるための１つの方法は、その寸法を小さくす
る事である。特に、短かいチヤネル長のFETを
製造する時、従来のようにリソグラフイ法により
チヤネル領域を形成しようとすると、回折等のリ
ソグラフイ法特有の限界により、サブミクロン程
度のチヤネル長を持つデバイスを得る事は困難で
あつた。
従つて本発明の目的は、実質的なチヤネル長が
リソグラフイ技術によつて限界付けられないよう
な、新規なFETの製造方法を提供することであ
る。
Ｃ 問題点を解決するための手段 本発明により、下記の方法でFETが製造され
る。
実質的水平面と実質的垂直面とを有する絶縁物
領域を表面上に有するシリコン基体を用意する。
次に所望の不純物濃度を有する層を、実質的水平
面及び実質的垂直面に形成する。次に、反応性イ
オン食刻ステツプを用いて水平面から層を取り除
き、実質的垂直面には層を残す。この時シリコン
基体に至る開孔が形成される。ソース及びドレイ
ンの拡散領域を、開孔を通して熱拡散又はイオン
注入によりシリコン基体に形成する。これらのソ
ース及びドレイン領域は、狭い垂直な層に近接す
る開孔を通して作られる。それからソース及びド
レイン領域に隣接し、ソース及びドレイン領域と
反対の導電性の狭い拡散領域を形成するために、
狭い垂直な層からシリコン基体ヘドーパントが拡
散するように適当な温度に、基体を加熱する。従
つて、ソース及びドレイン領域がＮタイプの場
合、狭い垂直な層のＰタイプのドーパントと基体
の加熱により、ソース及びドレイン領域に隣接す
るＰタイプの拡散が行なわれる。Ｐタイプの拡散
領域は、二重拡散された集積回路装置の実効チヤ
ンネルである。FET装置は、ソース及びドレイ
ン領域の間にゲート電極を、ソース及びドレイン
領域には接点を形成することにより完成する。非
常に正確な精度で制御できる付着層の厚さが、実
効チヤンネルの拡散領域の大きさとなつているこ
とがわかる。
Ｄ 実施例 第１Ａ図乃至第１Ｅ図には、フラツトなドーピ
ング・プロフイルと短かいチヤンネルを有する二
重拡散された電界効果トランジスタ装置を形成す
る方法が示されている。第１Ａ図は、高密度の二
重拡散されたMOS電界効果集積回路を形成する
ために用いられる単結晶シリコン基体のある小さ
な、しかし非常に拡大された部分を示している。
＜100＞結晶方向及び１乃至20Ω・cm程度の抵抗
を有するP-単結晶シリコン基板２２が、準備さ
れる。単結晶シリコン基板２２の他の領域からあ
る領域を分離するために、分離手段２４が提供さ
れている。例えば、分離は部分的な誘電体分離か
又は完全な誘電体分離である。用いられる誘電体
物質は、二酸化シリコン、窒化シリコン、ガラス
等である。高密度集積回路の好ましい分離は、第
１Ａ図に示されているように部分的な誘電体分離
である。当分野には、このタイプの誘電体分離領
域を形成する方法は多くある。米国特許第
3966577号明細書に述べられているプロセスを用
いることが好ましい。上記明細書には、領域２４
の部分的な誘電体分離を形成するプロセスが詳し
く述べられている。
厚さ5000Å程度の二酸化シリコン層２６が、熱
酸化プロセス又は化学気相付着プロセスにより形
成される。この層２６は、約970℃の温度の酸素
又は酸素と水蒸気の雰囲気中で熱的に成長され
る。二酸化シリコンを成長させる第２の方法は、
大気圧又は低い圧力条件で、約450℃の温度の
SiH4、O2又は約800℃の温度のSiH2Cl2、N2Oの
ような化学気相付着プロセスの使用を含む。二酸
化シリコンの代わりに絶縁層又は絶縁化合物が形
成されても良い。
標準のフオト・リソグラフイ及び食刻の技術が
用いられ、第１の絶縁物層２６に開孔が作られ
る。代わりに反応性イオン食刻技術を用いても良
い。層２６の開孔は、二重拡散されるMOS電界
効果装置の所望のソース及びドレイン領域に形成
される。
第２の層２８が、実質的水平面３０及び実質的
垂直面３２に形成される。本実施例のこの層２８
は、前記方法により化学気相付着された二酸化シ
リコン又は多結晶シリコンで構成される。二酸化
シリコンの実施の厚さは、約500乃至20000Åであ
り、好ましくは4000Åであると良い。20000Åよ
り大きい厚さは、電荷移動の問題及び長い食刻時
間を生じる。約1000Å以下の厚さでは、シヨート
の問題を生じる。第１Ｂ図の構造体が層２８の物
質に対する適当な反応性イオン食刻雰囲気中に置
かれる。反応性イオン食刻プロセスにより、層２
８の水平部分が実質的に取り除かれ、第１Ｃ図に
示されているような狭い垂直な領域を提供する。
さて、領域３６を形成するために、Ｎ＋イオン
がソース及びドレイン開孔を通して拡散される。
このステツプは、Ｎドーパントとしてリン、ヒ素
又はアンチモン等を用いて、熱拡散又はイオン注
入の技術により行なわれる。イオン注入又は熱拡
散のドライブ・イン・ステツプの間に、Ｐ＋ドー
パントが層２８から基板２２へ拡散して非常に狭
いＰの実効チヤンネル領域３４が形成される。Ｎ
＋領域がＰ領域３４より深い方が好ましい。この
結果、第１Ｄ図に構造体が示されている。構造体
の好ましい物理的な大きさは、第１Ｄ図のＰ領域
３４がほぼ幅5000Åで深さ2000Åであり、Ｎ＋領
域３６はほぼ深さ3000Åである。
さて、最初に層２６，２８を取り除くことによ
りFET装置が完成する。二酸化シリコン層３７
が、好ましくは前記の化学気相付着プロセスのよ
うな低温プロセスによるか、又は熱酸化により成
長される。8000℃乃至900℃の乾燥酸素雰囲気中
では、リンのドーピングにより過度にドープされ
たＮ＋領域は、わずかにドープされたＮ領域又は
Ｐ領域に比べ実質的により厚く熱酸化されて成長
する。このプロセスの結果、第１Ｅ図に示されて
いるようにＰ領域よりもＮ＋領域の上の方が二酸
化シリコン層が厚くなる。これは、半自己整合
（semi−selfalignment）技術である。アルミニウ
ムのような適当な導体の全面付着と次の画成ステ
ップにより、ゲート電極３８及びソースとドレイ
ン接点３９と４０が形成される。
Ｅ 発明の効果 本発明を用いれば、リソグラフイ技術では達成
不可能な短かいチヤネル長のFET装置を容易に
製造することができる。
【図面の簡単な説明】
第１Ａ図乃至第１Ｅ図は、本発明の１実施例に
従つてFETを製造する工程を示す図である。 ２２……Si基板、２４……分離領域、２６……
絶縁物層、２８……ドーピングされた材料の層、
３４……Ｐ拡散領域（チヤネル領域）、３６……
Ｎ＋拡散領域（ソース及びドレイン）、３８……
ゲート電極、３９……ソース接点、４０……ドレ
イン接点。

Claims (1)

  1. 【特許請求の範囲】 １ シリコン基体上に、実質的に水平な面及び実
    質的に垂直な面を有する領域を形成し、 上記水平面及び垂直面上に、所望のドーパント
    濃度を有する層を形成し、 上記垂直面上に上記ドーパント含有層を残し且
    つ上記シリコン基体上に開口を形成するように、
    反応性イオン・エツチングにより上記水平面上の
    層を実質的に除去し、 上記残つたドーパント含有層に隣接する上記開
    口を通じてソース領域及びドレイン領域を形成
    し、 上記基体を加熱して、上記ドーパントを上記基
    体中に拡散させ、上記ソース領域及びドレイン領
    域に隣接し且つそれらと反対の導電型の拡散領域
    を形成し、 上記拡散領域上を含めて上記ソース領域と上記
    ドレイン領域の間の上にゲート電極を形成する工
    程を含む 電界効果トランジスタの製造方法。
JP60181182A 1978-11-03 1985-08-20 電界効果トランジスタの製造方法 Granted JPS61159768A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US957599 1978-11-03
US05/957,599 US4209350A (en) 1978-11-03 1978-11-03 Method for forming diffusions having narrow dimensions utilizing reactive ion etching

Publications (2)

Publication Number Publication Date
JPS61159768A JPS61159768A (ja) 1986-07-19
JPH0347577B2 true JPH0347577B2 (ja) 1991-07-19

Family

ID=25499826

Family Applications (2)

Application Number Title Priority Date Filing Date
JP13093979A Granted JPS5562725A (en) 1978-11-03 1979-10-12 Method of forming narrow diffused region on silicon substrate
JP60181182A Granted JPS61159768A (ja) 1978-11-03 1985-08-20 電界効果トランジスタの製造方法

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP13093979A Granted JPS5562725A (en) 1978-11-03 1979-10-12 Method of forming narrow diffused region on silicon substrate

Country Status (6)

Country Link
US (1) US4209350A (ja)
EP (1) EP0010633B1 (ja)
JP (2) JPS5562725A (ja)
CA (1) CA1120610A (ja)
DE (1) DE2963852D1 (ja)
IT (1) IT1164518B (ja)

Families Citing this family (65)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4274909A (en) * 1980-03-17 1981-06-23 International Business Machines Corporation Method for forming ultra fine deep dielectric isolation
US4319932A (en) * 1980-03-24 1982-03-16 International Business Machines Corporation Method of making high performance bipolar transistor with polysilicon base contacts
US5202574A (en) * 1980-05-02 1993-04-13 Texas Instruments Incorporated Semiconductor having improved interlevel conductor insulation
US4513303A (en) * 1980-07-08 1985-04-23 International Business Machines Corporation Self-aligned metal field effect transistor integrated circuit
US4400865A (en) * 1980-07-08 1983-08-30 International Business Machines Corporation Self-aligned metal process for integrated circuit metallization
US4359816A (en) * 1980-07-08 1982-11-23 International Business Machines Corporation Self-aligned metal process for field effect transistor integrated circuits
US4758528A (en) * 1980-07-08 1988-07-19 International Business Machines Corporation Self-aligned metal process for integrated circuit metallization
US4488162A (en) * 1980-07-08 1984-12-11 International Business Machines Corporation Self-aligned metal field effect transistor integrated circuits using polycrystalline silicon gate electrodes
US4358340A (en) * 1980-07-14 1982-11-09 Texas Instruments Incorporated Submicron patterning without using submicron lithographic technique
US4394196A (en) * 1980-07-16 1983-07-19 Tokyo Shibaura Denki Kabushiki Kaisha Method of etching, refilling and etching dielectric grooves for isolating micron size device regions
JPS5758356A (en) * 1980-09-26 1982-04-08 Toshiba Corp Manufacture of semiconductor device
US4366613A (en) * 1980-12-17 1983-01-04 Ibm Corporation Method of fabricating an MOS dynamic RAM with lightly doped drain
NL188432C (nl) * 1980-12-26 1992-06-16 Nippon Telegraph & Telephone Werkwijze voor het vervaardigen van een mosfet.
US4438556A (en) * 1981-01-12 1984-03-27 Tokyo Shibaura Denki Kabushiki Kaisha Method of forming doped polycrystalline silicon pattern by selective implantation and plasma etching of undoped regions
US4414737A (en) * 1981-01-30 1983-11-15 Tokyo Shibaura Denki Kabushiki Kaisha Production of Schottky barrier diode
US4691435A (en) * 1981-05-13 1987-09-08 International Business Machines Corporation Method for making Schottky diode having limited area self-aligned guard ring
JPS581878A (ja) * 1981-06-26 1983-01-07 Fujitsu Ltd 磁気バブルメモリ素子の製造方法
JPS5848936A (ja) * 1981-09-10 1983-03-23 Fujitsu Ltd 半導体装置の製造方法
US4419810A (en) * 1981-12-30 1983-12-13 International Business Machines Corporation Self-aligned field effect transistor process
US4430791A (en) * 1981-12-30 1984-02-14 International Business Machines Corporation Sub-micrometer channel length field effect transistor process
US4445267A (en) * 1981-12-30 1984-05-01 International Business Machines Corporation MOSFET Structure and process to form micrometer long source/drain spacing
US4419809A (en) * 1981-12-30 1983-12-13 International Business Machines Corporation Fabrication process of sub-micrometer channel length MOSFETs
NL8105920A (nl) * 1981-12-31 1983-07-18 Philips Nv Halfgeleiderinrichting en werkwijze voor het vervaardigen van een dergelijke halfgeleiderinrichting.
EP0088004A3 (en) * 1982-02-16 1985-05-08 The Bendix Corporation Method for producing oriented islands of single crystal films
US4507171A (en) * 1982-08-06 1985-03-26 International Business Machines Corporation Method for contacting a narrow width PN junction region
US4712125A (en) * 1982-08-06 1987-12-08 International Business Machines Corporation Structure for contacting a narrow width PN junction region
US4464212A (en) * 1982-12-13 1984-08-07 International Business Machines Corporation Method for making high sheet resistivity resistors
JPS59138379A (ja) * 1983-01-27 1984-08-08 Toshiba Corp 半導体装置の製造方法
US4641170A (en) * 1983-12-12 1987-02-03 International Business Machines Corporation Self-aligned lateral bipolar transistors
US4551906A (en) * 1983-12-12 1985-11-12 International Business Machines Corporation Method for making self-aligned lateral bipolar transistors
US4636834A (en) * 1983-12-12 1987-01-13 International Business Machines Corporation Submicron FET structure and method of making
US4546535A (en) * 1983-12-12 1985-10-15 International Business Machines Corporation Method of making submicron FET structure
US4671830A (en) * 1984-01-03 1987-06-09 Xerox Corporation Method of controlling the modeling of the well energy band profile by interdiffusion
US4599789A (en) * 1984-06-15 1986-07-15 Harris Corporation Process of making twin well VLSI CMOS
US4574469A (en) * 1984-09-14 1986-03-11 Motorola, Inc. Process for self-aligned buried layer, channel-stop, and isolation
US4666557A (en) * 1984-12-10 1987-05-19 Ncr Corporation Method for forming channel stops in vertical semiconductor surfaces
US4649638A (en) * 1985-04-17 1987-03-17 International Business Machines Corp. Construction of short-length electrode in semiconductor device
US4714686A (en) * 1985-07-31 1987-12-22 Advanced Micro Devices, Inc. Method of forming contact plugs for planarized integrated circuits
US4843023A (en) * 1985-09-25 1989-06-27 Hewlett-Packard Company Process for forming lightly-doped-drain (LDD) without extra masking steps
GB8527062D0 (en) * 1985-11-02 1985-12-04 Plessey Co Plc Mos transistor manufacture
JPS62277745A (ja) * 1986-05-27 1987-12-02 Toshiba Corp 半導体集積回路
US5063168A (en) * 1986-07-02 1991-11-05 National Semiconductor Corporation Process for making bipolar transistor with polysilicon stringer base contact
US4722908A (en) * 1986-08-28 1988-02-02 Fairchild Semiconductor Corporation Fabrication of a bipolar transistor with a polysilicon ribbon
JPH0650741B2 (ja) * 1986-12-26 1994-06-29 富士通株式会社 半導体装置とその製造方法
US4933295A (en) * 1987-05-08 1990-06-12 Raytheon Company Method of forming a bipolar transistor having closely spaced device regions
JPH0766968B2 (ja) * 1987-08-24 1995-07-19 株式会社日立製作所 半導体装置及びその製造方法
US5179034A (en) * 1987-08-24 1993-01-12 Hitachi, Ltd. Method for fabricating insulated gate semiconductor device
EP0313683A1 (en) * 1987-10-30 1989-05-03 International Business Machines Corporation Method for fabricating a semiconductor integrated circuit structure having a submicrometer length device element
US4818714A (en) * 1987-12-02 1989-04-04 Advanced Micro Devices, Inc. Method of making a high performance MOS device having LDD regions with graded junctions
EP0338102B1 (de) * 1988-04-19 1993-03-10 International Business Machines Corporation Verfahren zur Herstellung von integrierten Halbleiterstrukturen welche Feldeffekttransistoren mit Kanallängen im Submikrometerbereich enthalten
US5015595A (en) * 1988-09-09 1991-05-14 Advanced Micro Devices, Inc. Method of making a high performance MOS device having both P- and N-LDD regions using single photoresist mask
US5064773A (en) * 1988-12-27 1991-11-12 Raytheon Company Method of forming bipolar transistor having closely spaced device regions
US5026663A (en) * 1989-07-21 1991-06-25 Motorola, Inc. Method of fabricating a structure having self-aligned diffused junctions
US5116778A (en) * 1990-02-05 1992-05-26 Advanced Micro Devices, Inc. Dopant sources for cmos device
EP0450503A3 (en) * 1990-04-02 1992-05-20 National Semiconductor Corporation Semiconductor devices with borosilicate glass sidewall spacers and method of fabrication
US5071780A (en) * 1990-08-27 1991-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. Reverse self-aligned transistor integrated circuit
US5175606A (en) * 1990-08-27 1992-12-29 Taiwan Semiconductor Manufacturing Company Reverse self-aligned BiMOS transistor integrated circuit
US5028557A (en) * 1990-08-27 1991-07-02 Taiwan Semiconductor Manufacturing Co., Ltd. Method of making a reverse self-aligned BIMOS transistor integrated circuit
US5235204A (en) * 1990-08-27 1993-08-10 Taiwan Semiconductor Manufacturing Company Reverse self-aligned transistor integrated circuit
US5466615A (en) * 1993-08-19 1995-11-14 Taiwan Semiconductor Manufacturing Company Ltd. Silicon damage free process for double poly emitter and reverse MOS in BiCMOS application
US5518945A (en) * 1995-05-05 1996-05-21 International Business Machines Corporation Method of making a diffused lightly doped drain device with built in etch stop
IL123799A0 (en) * 1995-10-04 1998-10-30 Intel Corp Formation of source/drain from doped glass
US6306702B1 (en) 1999-08-24 2001-10-23 Advanced Micro Devices, Inc. Dual spacer method of forming CMOS transistors with substantially the same sub 0.25 micron gate length
US6372589B1 (en) * 2000-04-19 2002-04-16 Advanced Micro Devices, Inc. Method of forming ultra-shallow source/drain extension by impurity diffusion from doped dielectric spacer
DE10330838B4 (de) 2003-07-08 2005-08-25 Infineon Technologies Ag Elektronisches Bauelement mit Schutzring

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5444483A (en) * 1977-09-14 1979-04-07 Matsushita Electric Ind Co Ltd Mos type semiconductor device and its manufacture

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1464921B2 (de) * 1963-10-03 1971-10-07 Fujitsu Ltd , Kawasaki, Kanagawa (Japan) Verfahren zum herstellen einer halbleiteranordnung
US3730787A (en) * 1970-08-26 1973-05-01 Bell Telephone Labor Inc Method of fabricating semiconductor integrated circuits using deposited doped oxides as a source of dopant impurities
US3966577A (en) * 1973-08-27 1976-06-29 Trw Inc. Dielectrically isolated semiconductor devices
US4124933A (en) * 1974-05-21 1978-11-14 U.S. Philips Corporation Methods of manufacturing semiconductor devices
US4037307A (en) * 1975-03-21 1977-07-26 Bell Telephone Laboratories, Incorporated Methods for making transistor structures
US4026740A (en) * 1975-10-29 1977-05-31 Intel Corporation Process for fabricating narrow polycrystalline silicon members
US4103415A (en) * 1976-12-09 1978-08-01 Fairchild Camera And Instrument Corporation Insulated-gate field-effect transistor with self-aligned contact hole to source or drain
JPS53132275A (en) * 1977-04-25 1978-11-17 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and its production
US4139442A (en) * 1977-09-13 1979-02-13 International Business Machines Corporation Reactive ion etching method for producing deep dielectric isolation in silicon
US4160991A (en) * 1977-10-25 1979-07-10 International Business Machines Corporation High performance bipolar device and method for making same
US4157269A (en) * 1978-06-06 1979-06-05 International Business Machines Corporation Utilizing polysilicon diffusion sources and special masking techniques

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5444483A (en) * 1977-09-14 1979-04-07 Matsushita Electric Ind Co Ltd Mos type semiconductor device and its manufacture

Also Published As

Publication number Publication date
DE2963852D1 (en) 1982-11-18
JPS6250969B2 (ja) 1987-10-28
JPS5562725A (en) 1980-05-12
JPS61159768A (ja) 1986-07-19
EP0010633B1 (de) 1982-10-13
US4209350A (en) 1980-06-24
IT1164518B (it) 1987-04-15
EP0010633A1 (de) 1980-05-14
IT7926808A0 (it) 1979-10-26
CA1120610A (en) 1982-03-23

Similar Documents

Publication Publication Date Title
JPH0347577B2 (ja)
KR100929335B1 (ko) 수직 대체 게이트 접합 전계 효과 트랜지스터
US5641698A (en) Method of fabricating FET device with double spacer
JP4173629B2 (ja) シリコンカーバイドに設けた自己整合パワー電界効果トランジスタ
KR100918779B1 (ko) 수직형 대체 게이트 트랜지스터들과 양립할 수 있는바이폴라 접합 트랜지스터
JPS61179567A (ja) 自己整合積層ｃｍｏｓ構造の製造方法
US6812105B1 (en) Ultra-thin channel device with raised source and drain and solid source extension doping
EP0083784B1 (en) Procedure for manufacturing integrated circuit devices having sub-micrometer dimension elements, and resulting structure
JP2001119026A (ja) ＳｉＧｅチャンネルのＭＯＳトランジスタ及びその製造方法
JPH03178135A (ja) 絶縁ゲート電界効果トランジスタ製造方法
JPH0923010A (ja) 半導体素子及びその製造方法
US5028554A (en) Process of fabricating an MIS FET
JPS60254659A (ja) 電界効果トランジスタ素子及びその製造方法
US6649308B1 (en) Ultra-short channel NMOSFETS with self-aligned silicide contact
JPH0370139A (ja) 光学的記録再生方法
KR100586178B1 (ko) 쇼트키 장벽 관통 트랜지스터 및 그 제조방법
JP3116163B2 (ja) 絶縁ゲート電界効果トランジスタの製造方法
GB2121235A (en) Method for manufacturing an insulated gate field effect transistor device
JPH10321860A (ja) Ｍｏｓトランジスタ及びその製造方法
JPH0298142A (ja) 絶縁ゲート型電界効果トランジスタの製造方法
JP2602589B2 (ja) Ｌｄｄトランジスタの製造方法
JPH06224215A (ja) 半導体装置の製造方法
JPH01155660A (ja) 半導体装置の製造方法
JPH04346476A (ja) Ｍｏｓ型ｆｅｔの製造方法
KR920015619A (ko) 엘리베이티드 소스/드레인형 mos fet의 제조방법