JPH0234462B2 - - Google Patents

Info

Publication number
JPH0234462B2
JPH0234462B2 JP57165432A JP16543282A JPH0234462B2 JP H0234462 B2 JPH0234462 B2 JP H0234462B2 JP 57165432 A JP57165432 A JP 57165432A JP 16543282 A JP16543282 A JP 16543282A JP H0234462 B2 JPH0234462 B2 JP H0234462B2
Authority
JP
Japan
Prior art keywords
conductive pattern
capacitor
lead frame
package
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57165432A
Other languages
English (en)
Other versions
JPS5954249A (ja
Inventor
Tetsushi Wakabayashi
Kyoshi Muratake
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57165432A priority Critical patent/JPS5954249A/ja
Priority to US06/530,046 priority patent/US4598307A/en
Priority to EP83305397A priority patent/EP0104051B1/en
Priority to DE8383305397T priority patent/DE3377314D1/de
Publication of JPS5954249A publication Critical patent/JPS5954249A/ja
Publication of JPH0234462B2 publication Critical patent/JPH0234462B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49589—Capacitor integral with or on the leadframe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Load-Bearing And Curtain Walls (AREA)

Description

【発明の詳細な説明】 発明の技術分野 本発明は、サーデツプ型セラミツクパツケージ
を用いた半導体装置に関し、集積回路に電源、グ
ランド間のバイパスコンデンサを内蔵しようとす
るものである。
技術の背景 半導体集積回路（IC）の高速比、高集積化に
伴ない、電源、グランド間に接続される雑音防
止、誤動作、抑止用バイパスコンデンサの重要性
が益々高まつている。従来のバイパスコンデンサ
はICパツケージを実装するプリント基板上の電
源ラインとグランドライン間に接続されるのが一
般的である。これは外界のノイズが電源ラインに
のつてIC内に入りICが誤動作することを防止す
ることを主眼においているためである。ところ
が、ICが高速且つ高集積化されるにつれてICの
マージンが減り、またICと該コンデンサとの間
の電源ラインに分布するインダクタンス無視でき
なくなり、これによりIC自体の電流パルスが該
コンデンサで充分に吸収されることなく電圧ノイ
ズとなつてIC自身が誤動作する現象が確認され
ている。
発明の目的 本発明は、上記のバイパスコンデンサをICパ
ツケージ上に搭載して内外のノイズを効果的に吸
収しようとするものである。
発明の構成 本発明は、電源供給用の第１の導体パターン
と、グランド電位を有する第２の導電パターンと
の間に信号用導電パターンが配置されてなり、半
導体集積回路チツプが搭載されるベース部が該第
２の導体パターンに接続されるリードフレームを
有するサーデツプ型セラミツクパツケージにおい
て、該第１の導電パターンに隣接して該セラミツ
クパツケージの外部に導出されないフローテイン
グ状態の第３の導電パターンを有し、 該第３の導電パターンはリードフレームの該ベ
ース部に接続され、該セラミツクパツケージの一
部に切欠部を形成して該リードフレームの第１の
導電パターンと第３の導電パターンとを露出し、
該切欠部にバイパス用のチツプコンデンサを載置
し、該第１の導電パターンと第３の導電パターン
との間を当該チツプコンデンサによつて接続する
こと特徴とするが、以下図示の実施例を参照しな
がらこれを詳細に説明する。
発明の実施例 第１図は本発明の一実施例を示す斜視図で、１
はＣ／Ｄ（サーデツプ）型のセラミツクパツケー
ジ、２はそのシールガラス層、３はリード（端子
ピン）、４ａ，４ｂは導体パターン、５はバイパ
スコンデンサとして用いられる多層セラミツク型
のチツプコンデンサ（容量はICチツプによつて
異なるが概ね0.01〜5μF）である。Ｃ／Ｄ型のセ
ラミツクパツケージ１は２枚のセラミツク板１
ａ，１ｂの間に、メタルリードフレーム３（詳細
は第２図に示す）を挾持しガラス層２で融着した
構造で、４ａ，４ｂは長手方向端部がコ字状に切
欠された上層のセラミツク板１ａの該切欠部Ｃに
露出する内部の導体パターン（リードフレームの
一部）である。本例ではこの切欠部にコンデンサ
５を搭載し、且つその両電極５ａ，５ｂを半田等
で導体パターン４ａ，４ｂに接着する。
Ｃ／Ｄ型のセラミツクパツケージ１ではコンデ
ンサ５を電源、グランド間に接続する配線はリー
ドフレームしかない。即ち端子ピン３の電源用ピ
ンとグランド用ピンは通常矩形状パツケージ１の
対角線上にあり、パツケージの上面又は下面にコ
ンデンサを取付けたのでは該端子ピンまでの長い
配線が必要である。また多層セラミツクパツケー
ジのようにパツケージの各層に配線が許容できる
訳ではなく、有り得る配線はリードフレーム１枚
であるから、これを利用するしかない。このリー
ドフレームは、予めエツチングまたはパンチング
でパターニングされた導体パターンを下層のセラ
ミツク板１ｂ上にプリントされた下側ガラス層表
面に貼り付け、そのガラス層を450℃程度で溶融
することで該下側ガラス層に固着し、その後IC
チツプ６（第２図）を搭載し、所要とするワイヤ
ボンドをした後表面を同種の上側ガラス層をプリ
ントしたキヤツプ（上層のセラミツク板）1aで
封止する（電気炉で該ガラス層を溶融する）こと
で、第１図のガラス層２を中央部に挾持したパツ
ケージに一体化されたものである。このとき、予
めキヤツプ１ａの端部（この部分はピン数が増す
につれより多く余る部分である）を図示の如く切
欠しておけばその部分に導体パターン４ａ，４ｂ
が露出する。
第２図はこの導体パターン４ａ，４ｂの説明図
である。通常１６ピンのパツケージでは対角線上
に位置する第８ピンが電源端子で、第16ピンがグ
ランド端子であるが、１ピンと９ピンが使用され
る場合もある。導体パターン４ａがこ第８ピンに
つらなるものとすれば、第16ピンにつらなる導体
パターン４ｃの位置は離れている。４ｂは本発明
により17本目のパターン（ポスト）として導体パ
ターン４ａの隣りに形成したフローテイング状態
の導体パターンである。このパターンは導体パタ
ーン４ａ等と共に形成されるが、後に切断線７で
カツトされてフローテイング状態となり、且つ
ICチツプ６を搭載するベース８がグランドレベ
ルであることから、そこへワイヤボンデイングす
ることでグランド電位とされる。但し、チツプの
背面がグランド電位でない場合はチツプをガラス
等の絶縁材で固定し、18ピンをベースにワイヤボ
ンドし、かつフローテイングパツドもベースにワ
イヤボンデイングする。なおこのリードフレーム
は１枚の導体板をエツチング又はパンチングして
作つた一体物であり、切断線７での切断により周
縁フレーム部（これは各部の支持用であつた）が
除かれ、個々のリードが分離される。
パターン４ａ，４ｂの一部はコンデンサ５の搭
載を容易にするため幅広にしておく。尚、キヤツ
プ１の封止時の熱でパターン４ａ，４ｂの表面は
酸化するのでその酸化膜をエツチングで除去し、
そこへ半田メツキを施こしておく。このようにす
るとコンデンサ５搭載の半田付け処理が容易にな
る。上層セラミツク板１ａに設ける切欠部Ｃは第
３図に示すように周囲が閉じられた開口であつて
もよい。チツプコンデンサ５の厚みは上層セラミ
ツク板のそれと同程度なので、開口の大きさもチ
ツプコンデンサのそれと同程度とすると、チツプ
コンデンサは開口Ｃを埋め、パツケージ外観がよ
くなる。唯、コンデンサを半田付けした後フラツ
クスを洗浄、除去するが、この作業は第１図の１
辺開放型の第１図の切欠部Ｃの方がやり易い。
発明の効果 以上述べたように本発明によれば、サーデツク
型にICパツケージ上に電源、グランド間のバイ
パスコンデンサを実装してしまうので、該コンデ
ンサとIC間の距離が縮まり、内外のノイズによ
る誤動作の防止効果が一層確実になる。またバイ
パスコンデンサを搭載する部分はパツケージで通
常余つている領域であるから、該コンデンサをパ
ツケージ外部に外付けする場合より実装密度が高
まる。
【図面の簡単な説明】
第１図および第２図は本発明の一実施例を示す
斜視図および平面パターン図、第３図は変形例を
示す部分斜視図である。 図中、１はサーデツク型セラミツクパツケー
ジ、１ａはそのキヤツプ、４ａは電源用導体パタ
ーン、４ｂはフローテイング状態の導体パター
ン、５はバイパスコンデンサ、６はICチツプ、
８はベース部分である。

Claims (1)

  1. 【特許請求の範囲】 １ 電源供給用の第１の導体パターンと、グラン
    ド電位を有する第２の導電パターンとの間に信号
    用導電パターンが配置されてなり、半導体集積回
    路チツプが搭載されるベース部が該第２の導体パ
    ターンに接続されるリードフレームを有するサー
    デツプ型セラミツクパツケージにおいて、 該第１の導電パターンに隣接して該セラミツク
    パツケージの外部に導出されないフローテイング
    状態の第３の導電パターンを有し、 該第３の導電パターンはリードフレームの該ベ
    ース部に接続され、 該セラミツクパツケージの一部に切欠部を形成
    して該リードフレームの第１の導電パターンと第
    ３の導電パターンとを露出し、 該切欠部にバイパス用のチツプコンデンサを載
    置し、該第１の導電パターンと第３の導電パター
    ンとの間を当該チツプコンデンサによつて接続す
    ることを特徴とする半導体装置。
JP57165432A 1982-09-22 1982-09-22 半導体装置 Granted JPS5954249A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP57165432A JPS5954249A (ja) 1982-09-22 1982-09-22 半導体装置
US06/530,046 US4598307A (en) 1982-09-22 1983-09-07 Integrated circuit device having package with bypass capacitor
EP83305397A EP0104051B1 (en) 1982-09-22 1983-09-15 Noise protection for a packaged semiconductor device
DE8383305397T DE3377314D1 (en) 1982-09-22 1983-09-15 Noise protection for a packaged semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57165432A JPS5954249A (ja) 1982-09-22 1982-09-22 半導体装置

Publications (2)

Publication Number Publication Date
JPS5954249A JPS5954249A (ja) 1984-03-29
JPH0234462B2 true JPH0234462B2 (ja) 1990-08-03

Family

ID=15812311

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57165432A Granted JPS5954249A (ja) 1982-09-22 1982-09-22 半導体装置

Country Status (4)

Country Link
US (1) US4598307A (ja)
EP (1) EP0104051B1 (ja)
JP (1) JPS5954249A (ja)
DE (1) DE3377314D1 (ja)

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Also Published As

Publication number Publication date
EP0104051A3 (en) 1985-09-18
EP0104051B1 (en) 1988-07-06
JPS5954249A (ja) 1984-03-29
US4598307A (en) 1986-07-01
EP0104051A2 (en) 1984-03-28
DE3377314D1 (en) 1988-08-11

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