JP7482072B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7482072B2 JP7482072B2 JP2021047800A JP2021047800A JP7482072B2 JP 7482072 B2 JP7482072 B2 JP 7482072B2 JP 2021047800 A JP2021047800 A JP 2021047800A JP 2021047800 A JP2021047800 A JP 2021047800A JP 7482072 B2 JP7482072 B2 JP 7482072B2
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- 239000004065 semiconductor Substances 0.000 title claims description 127
- 239000000758 substrate Substances 0.000 claims description 164
- 239000000853 adhesive Substances 0.000 claims description 49
- 230000001070 adhesive effect Effects 0.000 claims description 49
- 239000004642 Polyimide Substances 0.000 claims description 15
- 229920001721 polyimide Polymers 0.000 claims description 15
- 238000010586 diagram Methods 0.000 description 11
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 238000007789 sealing Methods 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
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- 239000010410 layer Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
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- H01L2224/732—Location after the connecting process
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Description
図1は、実施形態の半導体装置の模式断面図である。図2は、実施形態の半導体装置の模式上面図である。
第2実施形態は、第1実施形態の半導体装置100の変形例である。第2実施形態の半導体装置200の断面図を図8に示す。第2実施形態の半導体素子20は、フォトリレーである。図9に半導体素子20の模式斜視図を示す。
受光素子31は、制御回路31aをさらに有することができる。制御回路31aは、フォトダイオードアレイ31bの第1の電極と、第2の電極と、にそれぞれ接続されている。このような構成とすると、ソース・コモン接続されたMOSFET33のそれぞれのゲートに電圧を供給できる。また、制御回路31aは抵抗などを含み、MOSFET33がオンからオフに転じる場合に放電させて立ち下がり時間を短縮することができる。
10a :第1の面
11 :第1電極パッド
12 :第2電極パッド
13 :第1導電性接合剤
14 :第2導電性接合剤
20 :半導体素子
21 :配線基板
22 :第3電極パッド
23 :第4電極パッド
24 :第1スリット
25 :第2スリット
26 :ビア
31 :受光素子
31a :制御回路
31b :フォトダイオードアレイ
32 :発光素子
33 :MOSFET
34 :MOSFET
35 :ダイパッド部
36 :接着層
41 :出力端子部
42 :出力端子部
43 :入力端子部
44 :入力端子部
81 :パッド
90 :第1封止樹脂
91 :第2封止樹脂
100 :半導体装置
200 :半導体装置
BW:ボンディングワイヤ
D :ドレイン
G :ゲート
S :ソース電極
Claims (10)
- 第1電極パッド及び第2電極パッドが設けられた実装基板と、
支持基板、前記支持基板の前記実装基板を向く面に設けられている第3電極パッド及び前記支持基板の前記実装基板を向く面に設けられている第4電極パッドを有し、前記支持基板と前記第3電極パッドに第1スリットが設けられ、前記支持基板と前記第4電極パッドに第2スリットが設けられ、前記実装基板上に設けられた半導体素子と、
前記第1電極パッドと前記第3電極パッドを接続している第1導電性接合剤と、
前記第2電極パッドと前記第4電極パッドを接続している第2導電性接合剤と、
を備え、
前記支持基板に設けられている前記第1スリットの形状と前記第3電極パッドに設けられている前記第1スリットの形状は同じであり、
前記支持基板に設けられている前記第2スリットの形状と前記第4電極パッドに設けられている前記第2スリットの形状は同じであり、
前記支持基板は、厚さが10μm以上120μm以下のポリイミド基板である半導体装置。 - 前記第1スリットは、前記半導体素子の外周辺及び前記第3電極パッドの外周辺から前記支持基板の中央方向に向かって設けられており、
前記第2スリットは、前記半導体素子の外周辺及び前記第4電極パッドの外周辺から前記支持基板の中央方向に向かって設けられている請求項1に記載の半導体装置。 - 第1電極パッド及び第2電極パッドが設けられた実装基板と、
支持基板、前記支持基板の前記実装基板を向く面に設けられている第3電極パッド及び前記支持基板の前記実装基板を向く面に設けられている第4電極パッドを有し、前記支持基板と前記第3電極パッドに第1スリットが設けられ、前記支持基板と前記第4電極パッドに第2スリットが設けられ、前記実装基板上に設けられた半導体素子と、
前記第1電極パッドと前記第3電極パッドを接続している第1導電性接合剤と、
前記第2電極パッドと前記第4電極パッドを接続している第2導電性接合剤と、
を備え、
前記第1スリットは、前記半導体素子の外周辺及び前記第3電極パッドの外周辺から前記支持基板の中央方向に向かって設けられており、
前記第2スリットは、前記半導体素子の外周辺及び前記第4電極パッドの外周辺から前記支持基板の中央方向に向かって設けられていて、
前記第1スリットは、前記支持基板の面方向に延び、
前記第2スリットは、前記支持基板の面方向に延び、
前記支持基板は、厚さが10μm以上120μm以下のポリイミド基板である半導体装置。 - 前記ポリイミド基板の厚さは、10μm以上60μm以下である請求項1ないし3のいずれか1項に記載の半導体装置。
- 前記実装基板の前記半導体素子を向く面から垂直方向に前記第1電極パッドと前記半導体素子を重ねたとき、前記第1電極パッドの一部は、前記実装基板の面方向で前記半導体素子の外周辺より外側にはみ出ていて、
前記第1導電性接合剤は、前記第3電極パッドから前記第1電極パッドの外周辺に向かって傾斜している表面を有し、
前記実装基板の前記半導体素子を向く面から垂直方向に前記第2電極パッドと前記半導体素子を重ねたとき、前記第2電極パッドの一部は、前記実装基板の面方向で前記半導体素子の外周辺より外側にはみ出ていて、
前記第2導電性接合剤は、前記第4電極パッドから前記第2電極パッドの外周辺に向かって傾斜している表面を有する請求項1ないし4のいずれか1項に記載の半導体装置。 - 前記第1スリットの長さは、前記第1スリットの高さの4倍以上であり、
前記第1スリットの長さは、前記第1スリットの幅の4倍以上であり、
前記第2スリットの長さは、前記第2スリットの高さの4倍以上であり、
前記第2スリットの長さは、前記第2スリットの幅の4倍以上である請求項1ないし5のいずれか1項に記載の半導体装置。 - 前記第1スリット及び前記第2スリットは、前記支持基板の中央方向に開口していない請求項1ないし6のいずれか1項に記載の半導体装置。
- 前記半導体素子は、発光素子、受光素子、スイッチング素子、前記スイッチング素子と前記受光素子を接続する第1ボンディングワイヤを含むフォトリレーであり
前記第3電極パッドは、前記スイッチング素子のドレイン電極と接続し、
前記第1スリットは、前記第1ボンディングワイヤの前記スイッチング素子との接続部分の直下に設けられている請求項1ないし7のいずれか1項に記載の半導体装置。 - 前記第1スリットの長さは、前記スイッチング素子の前記第1スリットの開口部がある前記半導体素子の側面から前記スイッチング素子の前記第1スリットの開口部がある前記半導体素子の側面とは反対側の側面までの距離よりも短い請求項8に記載の半導体装置。
- 前記第1導電性接合剤と前記受光素子は、前記実装基板の前記半導体素子を向く面から垂直方向に重ならならず、
前記第2導電性接合剤と前記受光素子は、前記実装基板の前記半導体素子を向く面から垂直方向に重ならならない請求項8又は9に記載の半導体装置。
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JP2005223090A (ja) | 2004-02-04 | 2005-08-18 | Murata Mfg Co Ltd | 実装基板と部品との接続構造 |
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