JP7474782B2 - 内側供給フィンガを有する高出力トランジスタ - Google Patents
内側供給フィンガを有する高出力トランジスタ Download PDFInfo
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- JP7474782B2 JP7474782B2 JP2021562816A JP2021562816A JP7474782B2 JP 7474782 B2 JP7474782 B2 JP 7474782B2 JP 2021562816 A JP2021562816 A JP 2021562816A JP 2021562816 A JP2021562816 A JP 2021562816A JP 7474782 B2 JP7474782 B2 JP 7474782B2
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Description
本願は2019年4月24日に出願された米国特許出願第16/393,280号の優先権を主張し、その内容の全体を参照により本明細書に組み込む。
によって与えられ、上式で、Rorig及びWorigは、それぞれ元のゲート・フィンガ構成(例えば図2Aのゲート・フィンガ210)のゲート抵抗及びゲート・フィンガ幅であり、Wnewは新しい構成のゲート・フィンガ(例えば図5Aのゲート・フィンガ510)の幅である。式1から分かるように、ゲート・フィンガ幅をWから2Wへと大きくすると、ゲート抵抗は2倍になる。ゲート抵抗を大きくする結果、増幅器の重要な仕様であるトランジスタ利得が、より低くなる可能性がある。例えば、ゲート・フィンガ長さWを有するトランジスタが出力電力Pを生成する場合、ゲート・フィンガ510の幅を2倍の2Wにすることで、生成される出力電力は2Pよりも小さくなる。この非線形であるスケーリングはまた、電力増幅器の設計者が所与の出力電力要件に合わせて適正なトランジスタ・ダイのサイズを選択するのを困難にする。抵抗が増加すると増幅器の効率も低下する。
Claims (8)
- 半導体構造上に延在するゲート・フィンガ及びドレイン・フィンガであって、各々が、第1の方向に延在する各軸を有し、
前記ゲート・フィンガに結合されているゲート・ボンド・パッドと、
前記ドレイン・フィンガに結合されているドレイン・ボンド・パッドと、
前記ゲート・フィンガに結合されているゲート相互接続部であって、前記ゲート・ボンド・パッドは前記ゲート相互接続部の内側位置において前記ゲート相互接続部に結合されている、ゲート相互接続部と、
を備え、
前記ゲート・ボンド・パッドは前記ゲート・フィンガ上に延在する、及び/又は、前記ドレイン・ボンド・パッドは前記ドレイン・フィンガ上に延在し、
前記ゲート・ボンド・パッドおよび前記ドレイン・ボンド・パッドは、各々、前記第1の方向と交差する第2の方向に延在する各軸を有し、
前記ゲート相互接続部の前記内側位置は、前記ゲート相互接続部の第1の端部と第2の端部の間の距離の3分の1から3分の2の間にある、トランジスタ・デバイス。 - 前記ゲート・ボンド・パッドと前記ドレイン・ボンド・パッドの間のエリア上に配置されている隔離材を更に備える、請求項1に記載のトランジスタ・デバイス。
- 前記隔離材は導電性隔離材、磁性隔離材、又は損失性誘電体の隔離材である、請求項2に記載のトランジスタ・デバイス。
- 前記隔離材は複数の第3のボンド・ワイヤを備える、請求項2に記載のトランジスタ・デバイス。
- 前記ゲート・ボンド・パッドに結合されている入力ボンド・ワイヤと、
前記ドレイン・ボンド・パッドに結合されている出力ボンド・ワイヤと、を更に備え、
前記隔離材は物理的に前記入力ボンド・ワイヤと前記出力ボンド・ワイヤの間にある、請求項2に記載のトランジスタ・デバイス。 - 前記ゲート・ボンド・パッドは前記ドレイン・フィンガ及び前記ゲート・フィンガ上に延在する、請求項1から5までのいずれか一項に記載のトランジスタ・デバイス。
- 前記ゲート・ボンド・パッドは、多セグメント導電ビアによって前記ゲート相互接続部に結合されている、請求項1に記載のトランジスタ・デバイス。
- 前記ゲート・ボンド・パッドと前記ゲート・フィンガの間にフィールド・プレートを更に備える、請求項1から7までのいずれか一項に記載のトランジスタ・デバイス。
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US16/393,280 US11417746B2 (en) | 2019-04-24 | 2019-04-24 | High power transistor with interior-fed fingers |
PCT/US2020/029442 WO2020219624A1 (en) | 2019-04-24 | 2020-04-23 | High power transistor with interior-fed fingers |
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2020
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- 2020-04-23 KR KR1020237033678A patent/KR20230146112A/ko active Application Filing
- 2020-04-23 JP JP2021562816A patent/JP7474782B2/ja active Active
- 2020-04-23 CN CN202311309365.8A patent/CN117352546A/zh active Pending
- 2020-04-23 KR KR1020217037869A patent/KR102586156B1/ko active IP Right Grant
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KR102586156B1 (ko) | 2023-10-11 |
CN113892187B (zh) | 2023-09-29 |
JP2022529373A (ja) | 2022-06-21 |
US20200343352A1 (en) | 2020-10-29 |
KR20210154227A (ko) | 2021-12-20 |
US20220302271A1 (en) | 2022-09-22 |
WO2020219624A1 (en) | 2020-10-29 |
KR20230146112A (ko) | 2023-10-18 |
EP3959746A1 (en) | 2022-03-02 |
CN113892187A (zh) | 2022-01-04 |
US11417746B2 (en) | 2022-08-16 |
CN117352546A (zh) | 2024-01-05 |
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