JP7287770B2 - 完全自己整合性ビアを形成するための選択的付着の方法 - Google Patents

完全自己整合性ビアを形成するための選択的付着の方法 Download PDF

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JP7287770B2
JP7287770B2 JP2018216745A JP2018216745A JP7287770B2 JP 7287770 B2 JP7287770 B2 JP 7287770B2 JP 2018216745 A JP2018216745 A JP 2018216745A JP 2018216745 A JP2018216745 A JP 2018216745A JP 7287770 B2 JP7287770 B2 JP 7287770B2
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substrate
metal
gas
layer
plasma
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エヌ．タピリー カンダバラ
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Tokyo Electron Ltd
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H10W20/0693—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs by forming self-aligned vias
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    • H10W20/00—Interconnections in chips, wafers or substrates
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    • H10W20/071—Manufacture or treatment of dielectric parts thereof
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