JP7146421B2 - 表示装置 - Google Patents
表示装置 Download PDFInfo
- Publication number
- JP7146421B2 JP7146421B2 JP2018046096A JP2018046096A JP7146421B2 JP 7146421 B2 JP7146421 B2 JP 7146421B2 JP 2018046096 A JP2018046096 A JP 2018046096A JP 2018046096 A JP2018046096 A JP 2018046096A JP 7146421 B2 JP7146421 B2 JP 7146421B2
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- JP
- Japan
- Prior art keywords
- insulating layer
- intaglio pattern
- layer
- display device
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Images
Classifications
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- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
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Description
表示パネルDPの周縁部にある入出力端子部では、
表示素子層DPLに含まれる、厚みの大きい中間絶縁膜VLDが省かれることにより、厚みが比較的小さい、基板側の絶縁膜(特には、ゲートパターン層とデータパターン層の間の層間絶縁膜ILD)と、タッチセンサーTSの層に含まれるタッチ絶縁層TSLとが直接に重ね合わされ、
タッチ絶縁層TSLの上下に、入出力パッドIPD,OPD及び入出力パッドラインIPC,OPLが配置されたものにおいて、
ベンディングの際のストレスなどに起因して、入出力端子部にて、隣り合う入出力パッドIPD,OPDや入出力パッドラインIPC,OPL間に、ショートが生じるのを防止すべく、
A 出力パッドOPDの帯状の配列領域、及び、入力パッドIPDの帯状の配列領域のそれぞれについて、表示領域DA側と、その逆側とから挟み込むように、タッチ絶縁層TSLを省いた領域としての陰刻パターンGRを、パッド配列領域と平行に、帯状に、または帯状の領域内の複数のパターンとして設ける。
B1 中間絶縁膜VLDの残留パターン(「第2中間絶縁膜VLD2」)のほぼ全体に、陰刻パターンGRを設ける(図8~9、図17など)。
B2 中間絶縁膜VLDの残留パターン(「第2中間絶縁膜VLD2」)を、表示領域DA側と、その逆側とから挟み込むように、陰刻パターンGRを設ける(図13、図15~22など)。
B3 または、中間絶縁膜VLDの残留パターン(「第2中間絶縁膜VLD2」)の上に、ドット上に陰刻パターンGRを配列する(図21)。
151 接着物質
ACF 異方性導電フィルム
ACT アクティブ層
BMP バンプ
BR バリアー層
DA 表示領域
DE 出力電極
DM 表示装置
DP 表示パネル
GI ゲート絶縁膜
GE ゲート電極
GR 陰刻パターン
IC 駆動回路チップ
ILD 層間絶縁膜
IPD 入力パッド
NDA 非表示領域
OPD 出力パッド
SE 入力電極
SUB 表示パネルの基板
TCR テスト回路
TS タッチセンサー
TSL タッチ絶縁層
VLD 中間絶縁膜
Claims (27)
- 表示領域、及び、前記表示領域の外側に配置された非表示領域を含む基板と、
前記基板上に配置された信号ラインと、
前記信号ライン上に配置され、平面図で見て前記表示領域内に配置された表示素子を含む表示素子層と、
前記信号ラインに電気的に連結され、平面図で見て前記非表示領域内に配置された出力パッドを含むパッドグループと、
前記信号ラインと前記表示素子層との間に配置され、前記出力パッドを露出させる中間絶縁膜と、
前記表示素子層上に配置されたタッチ電極層と、
前記表示素子層上に配置され、前記タッチ電極層に接触し、平面図で見て前記非表示領域内に陰刻パターンが提供されたタッチ絶縁層と、を含み、
平面図で見て、前記陰刻パターンは、前記出力パッドと前記中間絶縁膜との間に配置される表示装置。 - 前記信号ラインは、第1導電層、及び、前記第1導電層上に配置された第2導電層を含み、
前記表示装置は、前記第1導電層と前記第2導電層との間に配置された層間絶縁膜をさらに含み、
前記層間絶縁膜と前記タッチ絶縁層とは、無機物質を含む請求項1に記載の表示装置。 - 前記タッチ絶縁層と前記層間絶縁膜とは、少なくとも一部の領域で互いに接触し、前記陰刻パターンは、前記層間絶縁膜を露出させる請求項2に記載の表示装置。
- 前記パッドグループに電気的に連結され、前記信号ラインに信号を提供する駆動回路チップと、
前記駆動回路チップに重なり、前記出力パッドに電気的に連結されたテスト回路と、をさらに含む請求項1に記載の表示装置。 - 前記パッドグループは、平面図で見て前記非表示領域内に配置され、前記出力パッドから離隔された入力パッドをさらに含み、
前記中間絶縁膜は、前記パッドグループを露出させる開口部が提供された第1中間絶縁膜、及び、前記第1中間絶縁膜から離隔され、平面図で見て前記入力パッドと前記出力パッドとの間に配置された第2中間絶縁膜を含む請求項1に記載の表示装置。 - 前記陰刻パターンは、前記出力パッドと、前記表示領域に隣接する前記第1中間絶縁膜の開口部の一側面との間に配置された第1陰刻パターンを含む請求項5に記載の表示装置。
- 前記陰刻パターンは、前記第2中間絶縁膜を完全に露出させる第2陰刻パターンをさらに含む請求項6に記載の表示装置。
- 前記陰刻パターンは、前記出力パッドと前記第2中間絶縁膜との間に配置された第2陰刻パターンをさらに含む請求項6に記載の表示装置。
- 前記第1陰刻パターンは、第1方向に延長し、
前記陰刻パターンは、前記第1方向に交差する第2方向に延長される第2陰刻パターンをさらに含む請求項6に記載の表示装置。 - 前記陰刻パターンは、
前記出力パッドと前記第2中間絶縁膜との間に配置された第2陰刻パターンと、
前記第2中間絶縁膜を露出し、前記第2陰刻パターンと離隔された第3陰刻パターンと、をさらに含む請求項6に記載の表示装置。 - 前記第1陰刻パターンは、ジグザグ状に延長された形状を有する請求項6に記載の表示装置。
- 前記陰刻パターンは、前記出力パッドと、前記表示領域に隣接する前記第1中間絶縁膜の前記開口部の前記一側面との間に配置されて、前記第1陰刻パターンから離隔された第2陰刻パターンをさらに含み、
前記第1陰刻パターン及び前記第2陰刻パターンは、前記出力パッドの中の1つから、互いに異なる離隔距離を有する請求項6に記載の表示装置。 - 一連の複数の前記第1陰刻パターンは、第1方向に互いに離隔され、
一連の複数の前記第2陰刻パターンは、前記第1方向に互いに離隔され、
前記各第1陰刻パターンは、前記第1方向にて、隣り合う2つの前記第2陰刻パターンの間に配置される請求項12に記載の表示装置。 - 前記陰刻パターンは、前記第2中間絶縁膜の一部を露出する複数の第2陰刻パターンをさらに含む請求項6に記載の表示装置。
- 前記陰刻パターンは、前記出力パッドの配置領域を完全にカバーするように提供される第1陰刻パターンを含む請求項5に記載の表示装置。
- 前記出力パッドと、前記信号ラインの中の一部とを連結する出力パッドラインをさらに含み、
前記陰刻パターンは、
前記出力パッドと、前記表示領域に隣接する前記第1中間絶縁膜の開口部の一側面との間に配置されるとともに、それぞれが、互いに隣接する2つの前記出力パッドラインの間に配置された第1陰刻パターンを含む請求項5に記載の表示装置。 - 前記第1陰刻パターンの深さは、前記タッチ絶縁層の厚さより大きい請求項16に記載の表示装置。
- 前記陰刻パターンは、
前記出力パッドと、前記表示領域に隣接する前記第1中間絶縁膜の開口部の一側面との間に配置されるとともに、前記第1陰刻パターンと重なる第2陰刻パターンをさらに含む請求項16に記載の表示装置。 - 前記第1陰刻パターンの深さは、前記第2陰刻パターンの深さより大きい請求項18に記載の表示装置。
- 平面図で見て、前記駆動回路チップと重なるとともに、前記出力パッドと前記テスト回路との間に配置されたダミーパッドをさらに含む請求項4に記載の表示装置。
- 前記第2中間絶縁膜には、前記入力パッドの側の縁、及び、前記出力パッドの側の縁に近接して配置されるホールが備えられる請求項5に記載の表示装置。
- 層間絶縁膜をさらに含み、
前記信号ラインは、第1導電層、及び、前記第1導電層上に配置された第2導電層を含み、
前記層間絶縁膜は、前記第1導電層と前記第2導電層との間に配置され、
前記ホールは、前記層間絶縁膜を貫通する請求項21に記載の表示装置。 - 表示領域、及び、前記表示領域の外側に配置された非表示領域を含む基板と、
前記基板上に配置された信号ラインと、
前記信号ライン上に配置され、平面図で見て前記表示領域内に配置された表示素子を含む表示素子層と、
前記信号ラインに電気的に連結され、平面図で見て前記非表示領域内に配置された出力パッドを含むパッドグループと、
前記パッドグループに接触し、前記信号ラインに信号を提供する駆動回路チップと、
前記表示素子層上に配置されたタッチ電極層と、
前記表示素子層上に配置され、平面図で見て前記非表示領域内に陰刻パターンが提供されたタッチ絶縁層と、を含み、
前記陰刻パターンは、前記パッドグループと重ならずに、前記駆動回路チップと重なる表示装置。 - 前記信号ラインは、第1導電層、及び、前記第1導電層上に配置された第2導電層を含み、
前記表示装置は、前記第1導電層と前記第2導電層との間に配置された層間絶縁膜をさらに含み、
前記層間絶縁膜と前記タッチ絶縁層とは、無機物質を含む請求項23に記載の表示装置。 - 前記タッチ絶縁層と前記層間絶縁膜は、少なくとも一部の領域で互いに接触し、前記陰刻パターンは、前記層間絶縁膜を露出する請求項24に記載の表示装置。
- 前記駆動回路チップに重なり、前記出力パッドに電気的に連結されたテスト回路をさらに含み、
前記パッドグループは、平面図で見て、前記非表示領域内に配置されており、前記テスト回路を挟んで前記出力パッドと対向する入力パッドをさらに含む請求項23に記載の表示装置。 - 表示領域、及び、前記表示領域の外側に配置された非表示領域とを含む基板と、
前記基板上に配置され、平面図で見て前記表示領域内に配置された表示素子を含む表示素子層と、
前記基板上に配置され、前記表示素子のための駆動信号を伝える信号ラインと、
前記基板上に配置され、前記信号ラインに電気的に連結され、平面図で見て前記非表示領域内に配置された出力パッドを含むパッドグループと、
前記表示素子層上に配置されたタッチ電極層と、
前記表示素子層上に配置され、前記タッチ電極層に接触するタッチ絶縁層と、を含み、
前記非表示領域中にて、前記タッチ絶縁層には陰刻パターンが提供され、前記陰刻パターンは、前記パッドグループと重ならない表示装置。
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EP3376350B1 (en) | 2020-10-14 |
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EP3376350A1 (en) | 2018-09-19 |
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US20230350524A1 (en) | 2023-11-02 |
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JP7357740B2 (ja) | 2023-10-06 |
US11720213B2 (en) | 2023-08-08 |
US11360621B2 (en) | 2022-06-14 |
US20200235192A1 (en) | 2020-07-23 |
CN108573997A (zh) | 2018-09-25 |
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JP2022177213A (ja) | 2022-11-30 |
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