JP7103256B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP7103256B2
JP7103256B2 JP2019023694A JP2019023694A JP7103256B2 JP 7103256 B2 JP7103256 B2 JP 7103256B2 JP 2019023694 A JP2019023694 A JP 2019023694A JP 2019023694 A JP2019023694 A JP 2019023694A JP 7103256 B2 JP7103256 B2 JP 7103256B2
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terminal
semiconductor chip
semiconductor
gate wiring
electrode
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English (en)
Japanese (ja)
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JP2020136315A5 (https=
JP2020136315A (ja
Inventor
晋 山田
悟 杉田
健治 小宮
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Denso Corp
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Denso Corp
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Priority to JP2019023694A priority Critical patent/JP7103256B2/ja
Priority to PCT/JP2020/000817 priority patent/WO2020166251A1/ja
Priority to CN202080013456.5A priority patent/CN113491008B/zh
Publication of JP2020136315A publication Critical patent/JP2020136315A/ja
Publication of JP2020136315A5 publication Critical patent/JP2020136315A5/ja
Priority to US17/394,278 priority patent/US11749731B2/en
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/20Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251Source or drain electrodes for field-effect devices
    • H10D64/258Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/20Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311Gate electrodes for field-effect devices
    • H10D64/411Gate electrodes for field-effect devices for FETs
    • H10D64/511Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • HELECTRICITY
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    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48Insulating materials thereof
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    • H10W40/00Arrangements for thermal protection or thermal control
    • H10W40/70Fillings or auxiliary members in containers or in encapsulations for thermal protection or control
    • H10W40/77Auxiliary members characterised by their shape
    • H10W40/778Auxiliary members characterised by their shape in encapsulations
    • HELECTRICITY
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    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
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    • H10W76/00Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10Containers or parts thereof
    • H10W76/12Containers or parts thereof characterised by their shape
    • H10W76/13Containers comprising a conductive base serving as an interconnection
    • H10W76/138Containers comprising a conductive base serving as an interconnection having another interconnection being formed by a cover plate parallel to the conductive base, e.g. sandwich type
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411Insulated-gate bipolar transistors [IGBT]
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    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126Top-view geometrical layouts of the regions or the junctions
    • H10D62/127Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/20Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251Source or drain electrodes for field-effect devices
    • H10D64/252Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
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    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40Leadframes
    • H10W70/411Chip-supporting parts, e.g. die pads
    • H10W70/415Leadframe inner leads serving as die pads
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40Leadframes
    • H10W70/421Shapes or dispositions
    • H10W70/442Shapes or dispositions of multiple leadframes in a single chip
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    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40Leadframes
    • H10W70/461Leadframes specially adapted for cooling
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    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40Leadframes
    • H10W70/481Leadframes for devices being provided for in groups H10D8/00 - H10D48/00
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    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • H10W72/07331Connecting techniques
    • H10W72/07336Soldering or alloying
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    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • H10W72/07351Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07354Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in dispositions
    • HELECTRICITY
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    • H10W72/341Dispositions of die-attach connectors, e.g. layouts
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    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • H10W72/351Materials of die-attach connectors
    • H10W72/352Materials of die-attach connectors comprising metals or metalloids, e.g. solders
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/59Bond pads specially adapted therefor
    • HELECTRICITY
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    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/853On the same surface
    • H10W72/865Die-attach connectors and bond wires
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    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires
    • HELECTRICITY
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    • H10W72/00Interconnections or connectors in packages
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    • H10W72/921Structures or relative sizes of bond pads
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    • HELECTRICITY
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    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/941Dispositions of bond pads
    • H10W72/944Dispositions of multiple bond pads
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    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
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    • H10W90/00Package configurations
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    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
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    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

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  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
JP2019023694A 2019-02-13 2019-02-13 半導体装置 Active JP7103256B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2019023694A JP7103256B2 (ja) 2019-02-13 2019-02-13 半導体装置
PCT/JP2020/000817 WO2020166251A1 (ja) 2019-02-13 2020-01-14 半導体装置
CN202080013456.5A CN113491008B (zh) 2019-02-13 2020-01-14 半导体装置
US17/394,278 US11749731B2 (en) 2019-02-13 2021-08-04 Semiconductor device

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Application Number Priority Date Filing Date Title
JP2019023694A JP7103256B2 (ja) 2019-02-13 2019-02-13 半導体装置

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Publication Number Publication Date
JP2020136315A JP2020136315A (ja) 2020-08-31
JP2020136315A5 JP2020136315A5 (https=) 2020-12-24
JP7103256B2 true JP7103256B2 (ja) 2022-07-20

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US (1) US11749731B2 (https=)
JP (1) JP7103256B2 (https=)
CN (1) CN113491008B (https=)
WO (1) WO2020166251A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2023088006A (ja) * 2021-12-14 2023-06-26 キオクシア株式会社 半導体装置及び半導体装置の製造方法
JP2024152328A (ja) * 2023-04-14 2024-10-25 株式会社豊田中央研究所 半導体装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004111885A (ja) 2002-07-23 2004-04-08 Toshiba Corp 半導体装置
JP2013045973A (ja) 2011-08-25 2013-03-04 Panasonic Corp 半導体装置
JP2014116473A (ja) 2012-12-10 2014-06-26 Toyota Motor Corp 半導体装置
WO2015029159A1 (ja) 2013-08-28 2015-03-05 三菱電機株式会社 半導体装置
JP2018093114A (ja) 2016-12-06 2018-06-14 株式会社東芝 半導体装置

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Publication number Priority date Publication date Assignee Title
JP2002311454A (ja) * 2001-04-16 2002-10-23 Matsushita Electric Ind Co Ltd 液晶画像表示装置と画像表示装置用半導体装置の製造方法
JP3622705B2 (ja) * 2001-06-21 2005-02-23 松下電器産業株式会社 表示装置用半導体装置の製造方法
JP2010212589A (ja) * 2009-03-12 2010-09-24 Renesas Electronics Corp 半導体装置の製造方法
JP5755533B2 (ja) 2011-08-26 2015-07-29 ルネサスエレクトロニクス株式会社 半導体装置
JP2014160779A (ja) * 2013-02-20 2014-09-04 Toyota Motor Corp 半導体装置
JP2014175647A (ja) * 2013-03-13 2014-09-22 Renesas Electronics Corp 半導体装置およびその製造方法
DE112014001487B4 (de) * 2013-10-03 2021-03-04 Fuji Electric Co., Ltd. Halbleitermodul
JP6224454B2 (ja) * 2013-12-27 2017-11-01 株式会社豊田中央研究所 縦型半導体装置
JP6246617B2 (ja) * 2014-02-27 2017-12-13 株式会社豊田中央研究所 表面電極を備えている半導体チップ
JP6617292B2 (ja) * 2014-05-23 2019-12-11 パナソニックIpマネジメント株式会社 炭化珪素半導体装置
JP2016167527A (ja) 2015-03-10 2016-09-15 株式会社日立製作所 半導体モジュール及びその製造方法
US9620440B1 (en) * 2016-02-25 2017-04-11 Texas Instruments Incorporated Power module packaging with dual side cooling

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004111885A (ja) 2002-07-23 2004-04-08 Toshiba Corp 半導体装置
JP2013045973A (ja) 2011-08-25 2013-03-04 Panasonic Corp 半導体装置
JP2014116473A (ja) 2012-12-10 2014-06-26 Toyota Motor Corp 半導体装置
WO2015029159A1 (ja) 2013-08-28 2015-03-05 三菱電機株式会社 半導体装置
JP2018093114A (ja) 2016-12-06 2018-06-14 株式会社東芝 半導体装置

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US20210367048A1 (en) 2021-11-25
WO2020166251A1 (ja) 2020-08-20
US11749731B2 (en) 2023-09-05
CN113491008B (zh) 2024-01-16
JP2020136315A (ja) 2020-08-31
CN113491008A (zh) 2021-10-08

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