CN113491008B - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN113491008B
CN113491008B CN202080013456.5A CN202080013456A CN113491008B CN 113491008 B CN113491008 B CN 113491008B CN 202080013456 A CN202080013456 A CN 202080013456A CN 113491008 B CN113491008 B CN 113491008B
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semiconductor
gate wiring
semiconductor device
active regions
electrode
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CN113491008A (zh
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山田晋
杉田悟
小宫健治
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Denso Corp
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Denso Corp
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Abstract

半导体装置具备半导体芯片(10、10a～10c)、设在半导体芯片的背面侧的第1导电性部件(30)和设在半导体芯片的表面侧的第2导电性部件(20、40)。半导体芯片具备：半导体基板(11、11a)，具有形成有元件的多个有源区域(a1～a4、a11～a16)和配置在有源区域间及有源区域的外周的不形成元件的非有源区域(na1～na5)；表层电极(14)，在多个有源区域上及多个有源区域间的非有源区域上连续地配置；以及第1栅极布线(12)和第2栅极布线(13)，作为设在非有源区域的表面侧的栅极布线，上述第1栅极布线(12)配置在表层电极的周边，上述第2栅极布线(13)配置在与表层电极对置的位置。

Description

半导体装置
关联申请的相互参照
本申请基于2019年2月13日提出的日本专利申请第2019－23694号，这里引用其记载内容。
技术领域
本发明涉及半导体装置。
背景技术
以往，如在专利文献1中公开的那样，有具备形成有多个有源区域和非有源区域的半导体基板的半导体装置。
现有技术文献
专利文献
专利文献1：日本特开2016－167527号公报
发明内容
专利文献1的半导体装置在非有源区域上形成栅极布线，在非有源区域的两旁的有源区域上连接表层电极。该情况下，半导体装置有可能表层电极滑动而与栅极布线短路。并且，半导体装置在表层电极和栅极布线短路的情况下电特性下降。
本发明的目的在于，提供能够提高电性能的半导体装置。
根据本发明的一技术方案，半导体装置具备：半导体芯片；第1导电性部件，设在半导体芯片的背面侧；以及第2导电性部件，设在半导体芯片的背面的相反面即表面侧。半导体芯片具备：半导体基板，具有形成有元件的多个有源区域和配置在有源区域间及有源区域的外周的没有形成元件的非有源区域；表层电极，在多个有源区域上及多个有源区域间的非有源区域上连续地配置；以及第1栅极布线和第2栅极布线，作为设在非有源区域的表面侧的栅极布线，上述第1栅极布线配置在表层电极的周边，上述第2栅极布线配置在与表层电极对置的位置。
根据上述结构，由于表层电极跨第2栅极布线而设置，所以与表层电极在栅极布线上被分割的情况相比，能够抑制表层电极在第2栅极布线上滑动。由此，本发明能够抑制表层电极与第2栅极布线短路。
附图说明
图1是表示实施方式的半导体装置的概略结构的剖视图。
图2是表示实施方式的半导体芯片的概略结构的平面图。
图3是沿着图2的III－III线的剖视图。
图4是图3的IV部分的放大剖视图。
图5是表示变形例1的半导体芯片的概略结构的平面图。
图6是表示变形例2的半导体芯片的概略结构的平面图。
图7是表示变形例3的半导体芯片的概略结构的平面图。
具体实施方式
以下，参照附图说明用来实施本发明的多个形态。在各形态中，有时对于与在先前形态中说明过的事项对应的部分赋予相同的标号而省略重复的说明。在各形态中，在仅说明结构的一部分的情况下，关于结构的其他部分，能够参照并应用先前说明过的其他形态。另外，以下将相互正交的3个方向表示为X方向、Y方向、Z方向。
如图1所示，半导体装置100具备半导体芯片10、接线柱(terminal)20、散热件31、41、主端子32、42、信号端子50、线材60、封固树脂部70。这样的半导体装置100作为形成构成三相逆变器的6个臂中的1个的所谓1in1封装而被周知，例如被植入到车辆的逆变器电路中。
第1散热件31是第1端子部件30的一部分。第1端子部件30的第1散热件31和第1主端子32被构成为一体物。详细地讲，第1端子部件30可以说具备第1主端子32和Z方向的厚度比第1主端子32厚的第1散热件31。第1端子部件30设在半导体芯片10的背面侧。第1端子部件30相当于第1导电性部件。
第1端子部件30以导热性及导电性优良的金属(例如铝或铜等)为主成分而构成。即，第1端子部件30被用作散热部件及导电路径，所以为了确保导热性及导电性，可以说以金属为主成分而构成。此外，第1端子部件30也可以是含有导热性及导电性优良的金属的合金。
第1散热件31是用来将从半导体芯片10产生的热散热的部位。详细地讲，第1散热件31为了将形成于半导体基板11的功率晶体管的热散热而设置。第1散热件31相当于第1散热部。如图1、图3所示，第1散热件31经由第1连接部81而与半导体芯片10的背面侧的电极(例如漏极电极)连接。由此，第1散热件31与半导体芯片10电连接及机械连接。第1连接部81能够采用焊料等导电性的连接部件。另外，在图2、图3中，为了使附图容易观察，省略了第2端子部件40、封固树脂部70的图示。
此外，如图1所示，第1散热件31的与半导体芯片10对置的面的相反面从封固树脂部70的背面侧露出而成为散热面。在本实施方式中，封固树脂部70的背面和第1散热件31的散热面大致共面。
由此，半导体装置100中，从半导体芯片10产生的热被传递到第1散热件31，并从第1散热件31的散热面散热。这样，半导体装置100即使半导体芯片10发热也能够抑制因热而在半导体芯片10中发生不良状况。
另外，第1散热件31的与半导体芯片10对置的对置面以及将该对置面与散热面相连的侧面被封固树脂部70覆盖。即，第1散热件31以与半导体芯片10对置的对置面及侧面接触到封固树脂部70的状态而被封固树脂部70覆盖。另外，第1散热件31的与半导体芯片10对置的对置面中，设有第1连接部81的区域的周边被封固树脂部70覆盖。
如图1所示，第1散热件31与第1主端子32相连。第1主端子32是从第1散热件31突出的部位。第1主端子32经由第1散热件31而与半导体芯片10的漏极电极电连接。由此，可以说第1散热件31除了作为散热部件的功能以外还具有作为导电路径的功能。换言之，第1散热件31起到将漏极电极和第1主端子32电连接的功能。
第1主端子32从第1散热件31向Y方向延伸设置，并且向与之后说明的第2主端子42相同的一侧延伸设置。并且，第1主端子32从封固树脂部70的侧面中的与第2主端子42相同的面向外部突出。即，第1主端子32的一部分被封固树脂部70覆盖，其他部位从封固树脂70突出。
另外，本发明的第1端子部件30不限于上述结构，也可以分体地构成第1散热件31和第1主端子32，并将第1散热件31和第1主端子32用导电性的连接部件连接。该情况下，也能够将第1散热件31看作第1导电性部件。
接线柱20和第2端子部件40设在半导体芯片10的表面侧。接线柱20和第2端子部件40相当于第2导电性部件。接线柱20和第2端子部件40以导热性及导电性优良的金属(例如铝或铜等)为主成分而构成。即，接线柱20和第2端子部件40由于被用作散热部件及导电路径，所以为了确保导热性及导电性，可以说以金属为主成分而构成。此外，接线柱20和第2端子部件40也可以是含有导热性及导电性优良的金属的合金。
如图1所示，接线柱20介于半导体芯片10与第2散热件41之间。接线柱20为了抑制之后说明的线材60与第2散热件41接触而设置。接线柱20位于半导体芯片10和第2散热件41的导热路径及导电路径的中途。接线柱20呈大致方柱状，更详细地讲，呈大致四方柱状(换言之大致长方体状)。由此，接线柱20的与电极14对置的对置面以及与第2散热件41对置的对置面为平坦面。在本实施方式中，作为一例而采用一个块状的接线柱20。换言之，接线柱20呈板状。
如图3所示，接线柱20与半导体芯片10的表面侧的电极14(例如源极电极)对置而配置。接线柱20通过第2连接部82而与电极14电连接及机械连接。第2连接部82能够采用焊料等导电性的连接部件。
此外，如图2所示，接线柱20在XY平面中呈矩形状。接线柱20跨两个电极14设置。此外，如图3所示，接线柱20与多个有源区域a1～a4对置而设置。由此，如图3所示，接线柱20不仅配置在多个有源区域a1～a4上，也配置在非有源区域na2～na4上。接线柱20例如不是与各电极14的表面侧的整个区域连接而是与一部分连接。但是，接线柱20也可以与各电极14的表面侧的整个区域连接。
第2散热件41是第2端子部件40的一部分。第2端子部件40的第2散热件41和第2主端子42被构成为一体物。详细地讲，第2端子部件40可以说具备第2主端子42和Z方向的厚度比第2主端子42厚的第2散热件41。第2端子部件40隔着接线柱20而设在半导体芯片10的表面侧。
第2散热件41是用来将从半导体芯片10产生的热散热的部位。详细地讲，第2散热件41为了将形成于半导体基板11的功率晶体管的热散热而设置。第2散热件41相当于第2散热部。如图1、图3所示，第2散热件41经由焊料等导电性的连接部件而与接线柱20电连接及机械连接。即，第2散热件41经由第2连接部82及接线柱20等而与电极14连接。由此，接线柱20将第2散热件41与电极14电连接。这样，第2散热件41与半导体芯片10电连接。
此外，如图1所示，第2散热件41的与半导体芯片10对置的面的相反面从封固树脂部70的背面侧露出而成为散热面。在本实施方式中，封固树脂部70的表面和第2散热件41的散热面大致共面。
由此，半导体装置100中，从半导体芯片10产生的热被传递到第2散热件41，并从第2散热件41的散热面散热。这样，半导体装置100即使半导体芯片10发热也能够抑制因热而在半导体芯片10中发生不良状况。
另外，第2散热件41的与接线柱20对置的对置面以及将该对置面与散热面相连的侧面被封固树脂部70覆盖。即，第2散热件41以与接线柱20对置的对置面及侧面接触到封固树脂部70的状态而被封固树脂部70覆盖。另外，第2散热件41的与接线柱20对置的对置面中，设有连接部件的区域的周边被封固树脂部70覆盖。
第2散热件41与第2主端子42相连。第2主端子42是从第2散热件41突出的部位。第2主端子42从封固树脂部70的侧面中的与第1主端子32相同的面向外部突出。第2主端子42经由第2散热件41而与半导体芯片10的电极14电连接。由此，第2散热件41可以说具有作为散热部的功能和作为导电路径的功能。换言之，第2散热件41起到将电极14和第2主端子42电连接的功能。
另外，本发明的第2端子部件40不限于上述结构，也可以将第2散热件41和第2主端子42分体而构成，并将第2散热件41和第2主端子42用导电性的连接部件连接。该情况下，也能够将第2散热件41看作第2导电性部件。
接线柱20能够由与两个散热件31、41相同的材料构成。由此，半导体装置100能够在半导体芯片10的表面侧及背面侧确保导热性及导电性。
进而，接线柱20的线膨胀系数可以与两个散热件31、41及半导体基板11不同。该情况下，接线柱20的线膨胀系数α1优选为两个散热件31、41的线膨胀系数α2与半导体基板11的线膨胀系数α3之间的值。详细地讲，这些线膨胀系数的关系优选为α3<α1<α2。这样，半导体装置100能够通过接线柱20、两个散热件31、41、半导体基板11的线膨胀系数差来抑制翘曲。随之，半导体装置100能够抑制施加于半导体基板11的应力、施加于半导体芯片10与第1散热件31之间的连接部及半导体芯片10与接线柱20之间的连接部的应力。
信号端子50如图1所示，经由线材60而与焊盘16电连接。线材60例如通过键合而与信号端子50及焊盘16连接。信号端子50的一部分被封固树脂70覆盖，其他部位从封固树脂70突出。信号端子50从封固树脂部70的侧面中的与第1主端子32及第2主端子42相反的面向外部突出。
这样，半导体装置100在Z方向上依次层叠配置有第1端子部件30、半导体芯片10、接线柱20、第2端子部件40。此外，半导体芯片10、接线柱20、第1端子部件30、第2端子部件40、信号端子50、线材60为一体化的构造体。并且，该构造体以端子32、42、50的一部分及散热面露出的状态被封固树脂部70覆盖。
封固树脂部70例如由环氧类树脂构成。封固树脂部70的平面形状大致为矩形，具有与Z方向正交的一面、与一面相反的背面、以及将一面与背面相连的侧面。半导体装置100的半导体芯片10及各连接部位由封固树脂部70保护。
这里，对半导体芯片10进行说明。半导体芯片10具备半导体基板11、栅极布线12、13、电极14、绝缘部15等。半导体基板11以硅或碳化硅等为主成分而构成。即，半导体基板11能够采用硅半导体或宽带隙半导体。在本实施方式中，作为一例，采用以碳化硅为主成分、作为功率晶体管而形成有MOSFET的半导体基板11。另外，半导体基板11还能够采用碳化硅以外的宽带隙半导体。
此外，半导体基板11形成有绝缘栅双极型晶体管(IGBT)、MOSFET等功率晶体管。功率晶体管由于通过动作而发热，所以可以说是发热元件。半导体芯片10如图2所示，平面形状大致为矩形。
MOSFET是所谓纵型构造，以在Z方向上流动电流。半导体基板11在Z方向的一面侧(表面侧)形成有作为源极电极的电极14，在与源极电极相反的背面侧形成有漏极电极。漏极电极形成在背面的大致整面。
如图2所示，在半导体基板11的一面侧形成有多个焊盘16。焊盘16是信号用的电极。半导体芯片10具有多个焊盘16。多个焊盘16在Y方向上形成在与电极14的形成区域相反侧的端部，且在X方向上排列。一个焊盘16例如用于栅极电极而与栅极布线连接。
此外，如图3所示，半导体基板11具有形成有作为元件的MOSFET的区域即多个有源区域a1～a4、以及没有形成元件的区域即非有源区域na1～na5。
各有源区域a1～a4形成有与电极14连接的区域。此外，各有源区域a1～a4也可以说是流动漏极电流的区域或MOSFET的动作区域。在本实施方式中，作为一例而采用在X方向上的四处形成有多个有源区域a1～a4的例子。即，半导体基板11在X方向上排列形成有在Y方向上延伸设置的多个有源区域a1～a4。各有源区域a1～a4隔开间隔而形成。
另外，作为一例，本发明采用形成有四个有源区域a1～a4的例子。但是，本发明不限于此，也可以形成两个有源区域，也可以形成五个以上的有源区域。
在非有源区域na1～na5上，配置之后说明的栅极布线。非有源区域na1～na5配置在有源区域间及有源区域的外周。在非有源区域na1～na5，形成保护环等耐压构造部等。
第2非有源区域na2形成在第1有源区域a1与第2有源区域a2之间。第3非有源区域na3形成在第2有源区域a2与第3有源区域a3之间。第4非有源区域na4形成在第3有源区域a3与第4有源区域a4之间。第1非有源区域na1和第5非有源区域na5形成在有源区域a1～a4的外周。
另外，在图3中，对在有源区域a1～a4的外周形成的非有源区域赋予了标号na1、na5。但是，第1非有源区域na1和第5非有源区域na5能够看作将有源区域a1～a4的外周包围的连续的非有源区域。由此，在本实施方式中，可以说形成有四个非有源区域na1～na5。但是，本发明不限于此，形成有与有源区域的个数对应的数量的非有源区域即可。
如图2、图3所示，在非有源区域na1～na5上形成有栅极布线12、13。栅极布线12、13是用来对MOSFET的栅极施加电压的布线。栅极布线12、13与焊盘16电连接。栅极布线12、13被作为绝缘层的绝缘部15覆盖。
作为栅极布线，半导体芯片10形成有第1栅极布线12和第2栅极布线13。第1栅极布线12在作为多晶硅布线的多晶硅层12a上层叠有作为金属布线的铝层12b。另一方面，第2栅极布线13虽然具有作为多晶硅布线的多晶硅层，但是不具有铝层等金属布线。即，第2栅极布线13能够看作从第1栅极布线12去除了铝层12b的布线。因此，第2栅极布线13的Z方向的厚度比第1栅极布线12薄。
第1栅极布线12形成在第1非有源区域na1、第3非有源区域na3、第5非有源区域na5上。由此，第1栅极布线12以将电极14包围的方式形成。另一方面，第2栅极布线13形成在第2非有源区域na2和第4非有源区域na4上。
电极14相当于表层电极。如图2、图3所示，电极14配置在有源区域a1～a4的表面侧，与有源区域a1～a4电连接。在本实施方式中，采用了形成有与第1有源区域a1及第2有源区域a2电连接的电极14、以及与第3有源区域a3及第4有源区域a4电连接的电极14这两个的例子。
此外，电极14隔着绝缘部15地跨第2栅极布线13而设置。如图4所示，电极14包括与有源区域a1～a4连接的连接部141、以及配置在第2栅极布线13上并在两个连接部141间相连的桥接部142。连接部141和桥接部142连续地设置。即，电极14可以说是连接部141和桥接部142一体连续地形成的电极层。
桥接部142隔着绝缘部15而配置在第2栅极布线13上。这样，电极14由于也设在第2栅极布线13及绝缘部15上，所以局部地成为与第2栅极布线13及绝缘部15的量相应地隆起的形状。由此，第2栅极布线13以被电极14夹着的方式形成。此外，第2栅极布线13也可以说被半导体基板11和电极14包围。
另外，在图4中，为了将有源区域a1、a2与非有源区域na2区别，仅半导体基板11的表面的阴影不同。由此，有源区域a1、a2和非有源区域na2并不是形成于半导体基板11的表面。
如以上这样，半导体装置100中，电极14跨第2栅极布线13而设置。因此，与电极14在栅极布线上被分割了的情况相比，半导体装置100能够抑制电极在第2栅极布线13上滑动。由此，半导体装置100能够抑制电极14与第2栅极布线13短路。
此外，第2栅极布线13与第1栅极布线12不同，虽然具有多晶硅布线但是不具有金属布线。因此，即使电极14滑动，半导体装置100也能够抑制电极14与第2栅极布线13短路。即，即使在X方向上电极14进行了滑动，半导体装置100也能够抑制电极14与第2栅极布线13短路。这样，半导体装置100能够提高电性能。
进而，如上述那样，电极14在电极表面设有第2连接部82。因此，电极14的电极表面可以被施以用来提高与第2连接部82的接合力的表面处理。表面处理是防氧化处理、用于提高焊料的浸润性的处理等。在本实施方式中，作为表面处理的一例而施以了镀覆处理。由此，电极14在电极表面形成有镀层143。由此，与没有施以表面处理的情况相比，半导体装置100能够提高半导体芯片10与接线柱20的连接状态。
此外，在本实施方式中，采用使接线柱20与第1栅极布线12的一部分对置地设置的例子。如图2所示，配置在电极14间的第1栅极布线12被配置在接线柱20的对置区域。但是，接线柱20也可以设在不与第1栅极布线12对置的位置。即，第1栅极布线12也可以不设在接线柱20的对置区域，而是仅设在接线柱20的对置区域的周边。
另外，第1栅极布线12及第2栅极布线13的结构并不限定于上述。第1栅极布线12是在非有源区域的表面侧设置的栅极布线、且配置在电极14的周边即可。即，第1栅极布线12不设在与电极14对置的位置(对置区域)即可。另一方面，第2栅极布线13是在非有源区域的表面侧设置的栅极布线、且设在与电极14对置的位置即可。即，第2栅极布线13设在半导体基板11与电极14之间即可。
以上，对本发明的一实施方式进行了说明。但是，本发明完全不受上述实施方式限制，在不脱离本发明的主旨的范围中能够进行各种变形。以下，作为本发明的其他形态，对变形例1～3进行说明。上述实施方式及变形例1～3能够分别单独地实施，但是也能够适当组合而实施。本发明并不限定于在实施方式中表示的组合，能够通过各种组合来实施。
(变形例1)
变形例1的半导体装置中，半导体芯片10a的结构与上述实施方式不同。如图5所示，半导体芯片10a设有感温二极管17。此外，在本实施方式中，作为一例而采用在接线柱20的对置区域设有感温二极管17的例子。感温二极管17为了检测半导体基板11的温度而设置。
感温二极管17设在非导通区域。即，感温二极管17设在非有源区域。此外，感温二极管17在阳极侧经由第1布线17a而电连接着第1焊盘16a，在阴极侧经由第2布线17b而电连接着第2焊盘16b。
变形例1的半导体装置能够起到与半导体装置100同样的效果。进而，变形例1的半导体装置能够输出半导体基板11的温度。
(变形例2)
变形例2的半导体装置中，半导体芯片10b的结构与变形例1不同。如图6所示，半导体芯片10b在不与接线柱20对置的位置设有感温二极管17。即，半导体芯片10b在接线柱20的对置区域的周边设有感温二极管17。变形例2的半导体装置能够起到与变形例1的半导体装置同样的效果。
(变形例3)
变形例3的半导体装置中，半导体基板11a的结构与上述实施方式不同。如图7所示，半导体芯片10c具备半导体基板11a。半导体基板11a形成有第1有源区域a11、第2有源区域a12、第3有源区域a13、第4有源区域a14、第5有源区域a15、第6有源区域a16。半导体基板11a在这些有源区域a11～a16之间和周围形成有非有源区域。
半导体基板11a在Y方向上排列配置有第1有源区域a11、第3有源区域a13、第5有源区域a15，在Y方向上排列配置有第2有源区域a12、第4有源区域a14、第6有源区域a16。此外，半导体基板11a在X方向上排列配置有第1有源区域a11和第2有源区域a12。同样，半导体基板11a在X方向上排列配置有第3有源区域a13和第4有源区域a14。并且，半导体基板11a在X方向上排列配置有第5有源区域a15和第6有源区域a16。
电极14设在三处。第一个电极14跨第1有源区域a11和第2有源区域a12而设置。第二个电极14跨第3有源区域a13和第4有源区域a14而设置。并且，第三个电极14跨第5有源区域a15和第6有源区域a16而设置。
另外，以下，将在Y方向上排列配置的第1有源区域a11、第3有源区域a13、第5有源区域a15一起称作第1有源列。同样，将第2有源区域a12、第4有源区域a14、第6有源区域a16一起称作第2有源列。此外，将第1有源区域a11和第2有源区域a12称作第1有源行，将第3有源区域a13和第4有源区域a14称作第2有源行，将第5有源区域a15和第6有源区域a16称作第3有源行。
第1栅极布线12配置在有源区域a11～s16的周围、第1有源行与第2有源行之间、以及第2有源行与第3有源行之间形成的非有源区域上。另一方面，第2栅极布线13配置在第1有源列与第2有源列之间形成的非有源区域上。
另外，关于半导体芯片10c，也可以代替第1有源行与第2有源行之间以及第2有源行与第3有源行之间的第1栅极布线12而配置有第2栅极布线13。由此，半导体装置即使电极14不仅在X方向上滑动而且还在Y方向上滑动，也能够抑制电极14与第2栅极布线13短路。
变形例3的半导体装置能够起到与半导体装置100同样的效果。此外，半导体装置中，在非有源区域上将电极14分割的情况下，如果半导体基板的体积相同，则有源区域的分割数越多，电极14与栅极布线短路的可能性越高。但是，变形例3的半导体装置由于如上述那样构成，所以即使有源区域的分割数较多也能够抑制短路。

Claims (18)

1.一种半导体装置，其特征在于，
具备：
半导体芯片(10、10a～10c)；
第1导电性部件(30)，设在上述半导体芯片的背面侧；以及
第2导电性部件，设在上述半导体芯片的背面的相反面即表面侧；
上述半导体芯片具备：
半导体基板(11、11a)，具有形成有元件的多个有源区域(a1～a4、a11～a16)和配置在上述有源区域间及上述有源区域的外周的没有形成上述元件的非有源区域(na1～na5)；
表层电极(14)，在多个上述有源区域上及多个上述有源区域间的上述非有源区域上连续地配置；以及
第1栅极布线(12)和第2栅极布线(13)，是在上述非有源区域的上述表面侧设置的栅极布线，上述第1栅极布线(12)配置在上述表层电极的周边，上述第2栅极布线(13)配置在与上述表层电极对置的位置，
上述第1栅极布线具有多晶硅布线和金属布线，上述第2栅极布线不具有金属布线而具有多晶硅布线。
2.如权利要求1所述的半导体装置，其特征在于，
上述第1导电性部件包括将从上述半导体芯片产生的热散热的第1散热部(31)；
上述第2导电性部件包括将从上述半导体芯片产生的热散热的第2散热部(41)。
3.如权利要求2所述的半导体装置，其特征在于，
上述第2导电性部件在上述第2散热部与上述半导体芯片之间具有将上述表层电极与上述第2散热部电连接的接线柱(20)；
上述接线柱的线膨胀系数是上述第1散热部及上述第2散热部与上述半导体基板之间的值。
4.如权利要求3所述的半导体装置，其特征在于，
上述半导体芯片在不与上述接线柱对置的位置设有感温二极管(17)。
5.如权利要求3或4所述的半导体装置，其特征在于，
上述接线柱设在不与上述第1栅极布线对置的位置。
6.如权利要求1～3中任一项所述的半导体装置，其特征在于，
上述半导体芯片在非导通区域设有感温二极管(17)。
7.如权利要求1～4中任一项所述的半导体装置，其特征在于，
上述半导体基板是硅半导体。
8.如权利要求1～4中任一项所述的半导体装置，其特征在于，
上述半导体基板是宽带隙半导体。
9.如权利要求1～4中任一项所述的半导体装置，其特征在于，
上述表层电极在电极表面设有导电性的连接部件；
上述电极表面被施以了用来提高与上述连接部件之间的接合力的表面处理。
10.如权利要求1～4中任一项所述的半导体装置，其特征在于，
上述表层电极具有：
连接部(141)，是配置在多个上述有源区域中的隔着上述第2栅极布线而相邻的至少2个有源区域上的部分，与上述至少2个有源区域连接；以及
桥接部(142)，是位于上述非有源区域上的部分，并且隔着绝缘部(15)而配置在上述第2栅极布线上，与上述连接部相连。
11.一种半导体装置，其特征在于，
具备：
半导体芯片(10、10a～10c)；
第1导电性部件(30)，设在上述半导体芯片的背面侧；以及
第2导电性部件，设在上述半导体芯片的背面的相反面即表面侧；
上述半导体芯片具备：
半导体基板(11、11a)，具有形成有元件的多个有源区域(a1～a4、a11～a16)和配置在上述有源区域间及上述有源区域的外周的没有形成上述元件的非有源区域(na1～na5)；
表层电极(14)，在多个上述有源区域上及多个上述有源区域间的上述非有源区域上连续地配置；以及
第1栅极布线(12)和第2栅极布线(13)，是在上述非有源区域的上述表面侧设置的栅极布线，上述第1栅极布线(12)配置在上述表层电极的周边，上述第2栅极布线(13)配置在与上述表层电极对置的位置，
上述第1导电性部件包括将从上述半导体芯片产生的热散热的第1散热部(31)；
上述第2导电性部件包括将从上述半导体芯片产生的热散热的第2散热部(41)，在上述第2散热部与上述半导体芯片之间具有将上述表层电极与上述第2散热部电连接的接线柱(20)；
上述接线柱的线膨胀系数是上述第1散热部及上述第2散热部与上述半导体基板之间的值。
12.如权利要求11所述的半导体装置，其特征在于，
上述半导体芯片在不与上述接线柱对置的位置设有感温二极管(17)。
13.如权利要求11或12所述的半导体装置，其特征在于，
上述接线柱设在不与上述第1栅极布线对置的位置。
14.如权利要求11所述的半导体装置，其特征在于，
上述半导体芯片在非导通区域设有感温二极管(17)。
15.如权利要求11或12所述的半导体装置，其特征在于，
上述半导体基板是硅半导体。
16.如权利要求11或12所述的半导体装置，其特征在于，
上述半导体基板是宽带隙半导体。
17.如权利要求11或12所述的半导体装置，其特征在于，
上述表层电极在电极表面设有导电性的连接部件；
上述电极表面被施以了用来提高与上述连接部件之间的接合力的表面处理。
18.如权利要求11或12所述的半导体装置，其特征在于，
上述表层电极具有：
连接部(141)，是配置在多个上述有源区域中的隔着上述第2栅极布线而相邻的至少2个有源区域上的部分，与上述至少2个有源区域连接；以及
桥接部(142)，是位于上述非有源区域上的部分，并且隔着绝缘部(15)而配置在上述第2栅极布线上，与上述连接部相连。
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