WO2020166251A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2020166251A1
WO2020166251A1 PCT/JP2020/000817 JP2020000817W WO2020166251A1 WO 2020166251 A1 WO2020166251 A1 WO 2020166251A1 JP 2020000817 W JP2020000817 W JP 2020000817W WO 2020166251 A1 WO2020166251 A1 WO 2020166251A1
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WIPO (PCT)
Prior art keywords
semiconductor device
semiconductor
terminal
active
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2020/000817
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English (en)
French (fr)
Japanese (ja)
Inventor
晋 山田
悟 杉田
健治 小宮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
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Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to CN202080013456.5A priority Critical patent/CN113491008B/zh
Publication of WO2020166251A1 publication Critical patent/WO2020166251A1/ja
Priority to US17/394,278 priority patent/US11749731B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
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    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
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    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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    • H10D64/251—Source or drain electrodes for field-effect devices
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    • H10W70/40—Leadframes
    • H10W70/481—Leadframes for devices being provided for in groups H10D8/00 - H10D48/00
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    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07354—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in dispositions
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Definitions

  • the present disclosure relates to semiconductor devices.
  • Patent Document 1 there is a semiconductor device including a semiconductor substrate in which a plurality of active regions and inactive regions are formed.
  • the gate wiring is formed on the inactive region, and the surface layer electrodes are connected to the active regions on both sides of the inactive region.
  • the surface electrode may slide and short-circuit with the gate wiring. Then, in the semiconductor device, when the surface layer electrode and the gate wiring are short-circuited, the electrical characteristics are deteriorated.
  • the present disclosure aims to provide a semiconductor device capable of improving electrical performance.
  • a semiconductor device includes a semiconductor chip, a first conductive member provided on the back surface side of the semiconductor chip, and a second conductive member provided on the front surface side opposite to the back surface of the semiconductor chip. And a conductive member.
  • a semiconductor chip is a semiconductor substrate having a plurality of active regions in which elements are formed, and non-active regions in which no elements are formed, which are arranged between active regions and around the active region, and a plurality of active regions.
  • the present disclosure can suppress the surface layer electrode from short-circuiting with the second gate wiring.
  • FIG. 3 is a cross-sectional view showing a schematic configuration of a semiconductor device in an embodiment. It is a top view showing a schematic structure of a semiconductor chip in an embodiment.
  • FIG. 3 is a sectional view taken along line III-III in FIG. 2. It is an expanded sectional view of the IV portion of FIG.
  • FIG. 9 is a plan view showing a schematic configuration of a semiconductor chip in Modification 1.
  • FIG. 9 is a plan view showing a schematic configuration of a semiconductor chip in Modification 2.
  • FIG. 11 is a plan view showing a schematic configuration of a semiconductor chip in Modification 3;
  • the semiconductor device 100 includes a semiconductor chip 10, terminals 20, heat sinks 31, 41, main terminals 32, 42, signal terminals 50, wires 60, and a sealing resin portion 70.
  • a semiconductor device 100 is known as a so-called 1-in-1 package that constitutes one of the six arms that configure a three-phase inverter, and is incorporated in an inverter circuit of a vehicle, for example.
  • the first heat sink 31 is a part of the first terminal member 30.
  • the first terminal member 30 includes a first heat sink 31 and a first main terminal 32 that are integrally formed. More specifically, it can be said that the first terminal member 30 includes the first main terminal 32 and the first heat sink 31 that is thicker in the Z direction than the first main terminal 32.
  • the first terminal member 30 is provided on the back surface side of the semiconductor chip 10.
  • the first terminal member 30 corresponds to the first conductive member.
  • the first terminal member 30 is mainly composed of a metal (for example, aluminum or copper) having excellent thermal conductivity and electrical conductivity. That is, since the first terminal member 30 is used as a heat dissipation member and an electric conduction path, it can be said that the first terminal member 30 is mainly composed of a metal in order to ensure thermal conductivity and electric conductivity.
  • the first terminal member 30 may be an alloy containing a metal having excellent thermal conductivity and electrical conductivity.
  • the first heat sink 31 is a part for radiating the heat generated from the semiconductor chip 10. Specifically, the first heat sink 31 is provided to radiate the heat of the power transistor formed on the semiconductor substrate 11. The first heat sink 31 corresponds to the first heat dissipation section. As shown in FIGS. 1 and 3, the first heat sink 31 is connected to an electrode (for example, a drain electrode) on the back surface side of the semiconductor chip 10 via the first connection portion 81. Therefore, the first heat sink 31 is electrically and mechanically connected to the semiconductor chip 10.
  • the first connecting portion 81 can employ a conductive connecting member such as solder. 2 and 3, the second terminal member 40 and the sealing resin portion 70 are not shown in order to make the drawings easy to see.
  • the surface of the first heat sink 31 opposite to the surface facing the semiconductor chip 10 is exposed from the back surface side of the encapsulation resin portion 70 and serves as a heat dissipation surface.
  • the back surface of the sealing resin portion 70 and the heat radiation surface of the first heat sink 31 are substantially flush with each other.
  • the heat generated from the semiconductor chip 10 is transferred to the first heat sink 31 and is radiated from the heat radiation surface of the first heat sink 31. In this way, the semiconductor device 100 can suppress the occurrence of defects in the semiconductor chip 10 due to heat even if the semiconductor chip 10 generates heat.
  • the surface of the first heat sink 31 facing the semiconductor chip 10 and the side surface connecting the facing surface and the heat radiation surface are covered with the sealing resin portion 70. That is, the first heat sink 31 is covered with the sealing resin portion 70 in a state where the sealing resin portion 70 is in contact with the surface and the side surface facing the semiconductor chip 10.
  • the surface of the first heat sink 31 facing the semiconductor chip 10 is covered with the sealing resin portion 70 around the area where the first connection portion 81 is provided.
  • the first heat sink 31 is connected to the first main terminal 32.
  • the first main terminal 32 is a portion protruding from the first heat sink 31.
  • the first main terminal 32 is electrically connected to the drain electrode of the semiconductor chip 10 via the first heat sink 31. Therefore, it can be said that the first heat sink 31 has a function as an electric conduction path in addition to a function as a heat dissipation member. In other words, the first heat sink 31 has a function of electrically relaying the drain electrode and the first main terminal 32.
  • the first main terminal 32 extends from the first heat sink 31 in the Y direction and on the same side as the second main terminal 42 described later. Then, the first main terminal 32 projects to the outside from the same side of the side surface of the sealing resin portion 70 as the second main terminal 42. That is, part of the first main terminal 32 is covered with the sealing resin portion 70, and the other portions project from the sealing resin 70.
  • the first terminal member 30 of the present disclosure is not limited to the above configuration, the first heat sink 31 and the first main terminal 32 are configured as separate bodies, and the first heat sink 31 and the first main terminal 32 are conductive. It may be connected by a connecting member.
  • the first heat sink 31 can be regarded as the first conductive member.
  • the terminal 20 and the second terminal member 40 are provided on the front surface side of the semiconductor chip 10.
  • the terminal 20 and the second terminal member 40 correspond to the second conductive member.
  • the terminal 20 and the second terminal member 40 are mainly composed of a metal (for example, aluminum or copper) having excellent heat conductivity and electric conductivity. That is, since the terminal 20 and the second terminal member 40 are used as a heat dissipation member and an electric conduction path, it can be said that they are composed mainly of metal in order to ensure thermal conductivity and electric conductivity.
  • the terminal 20 and the second terminal member 40 may be an alloy containing a metal having excellent thermal conductivity and electrical conductivity.
  • the terminal 20 is interposed between the semiconductor chip 10 and the second heat sink 41.
  • the terminal 20 is provided to prevent the wire 60, which will be described later, from coming into contact with the second heat sink 41.
  • the terminal 20 is located in the middle of the heat conduction path and the electric conduction path between the semiconductor chip 10 and the second heat sink 41.
  • the terminal 20 has a substantially prismatic shape, more specifically, a substantially square pillar shape (in other words, a substantially rectangular parallelepiped shape). Therefore, in the terminal 20, the surface facing the electrode 14 and the surface facing the second heat sink 41 are flat surfaces.
  • one block-shaped terminal 20 is adopted. In other words, the terminal 20 has a plate shape.
  • the terminal 20 is arranged to face the electrode 14 (for example, source electrode) on the front surface side of the semiconductor chip 10.
  • the terminal 20 is electrically and mechanically connected to the electrode 14 by the second connecting portion 82.
  • the second connecting portion 82 can employ a conductive connecting member such as solder.
  • the terminal 20 has a rectangular shape on the XY plane.
  • the terminal 20 is provided across the two electrodes 14.
  • the terminal 20 is provided so as to face the plurality of active areas a1 to a4. Therefore, as shown in FIG. 3, the terminals 20 are arranged not only on the plurality of active areas a1 to a4 but also on the inactive areas na2 to na4.
  • the terminal 20 is connected to, for example, a part of the surface of each electrode 14 rather than the entire area. However, the terminal 20 may be connected to the entire area on the front surface side of each electrode 14.
  • the second heat sink 41 is a part of the second terminal member 40.
  • the second terminal member 40 is configured by integrally forming the second heat sink 41 and the second main terminal 42. More specifically, it can be said that the second terminal member 40 includes the second main terminal 42 and the second heat sink 41 that is thicker in the Z direction than the second main terminal 42.
  • the second terminal member 40 is provided on the front surface side of the semiconductor chip 10 via the terminal 20.
  • the second heat sink 41 is a part for radiating the heat generated from the semiconductor chip 10. Specifically, the second heat sink 41 is provided to radiate the heat of the power transistor formed on the semiconductor substrate 11.
  • the second heat sink 41 corresponds to the second heat dissipation section. As shown in FIGS. 1 and 3, the second heat sink 41 is electrically and mechanically connected to the terminal 20 via a conductive connecting member such as solder. That is, the second heat sink 41 is connected to the electrode 14 via the second connecting portion 82, the terminal 20, and the like. Therefore, the terminal 20 electrically connects the second heat sink 41 and the electrode 14. In this way, the second heat sink 41 is electrically connected to the semiconductor chip 10.
  • the surface opposite to the surface facing the semiconductor chip 10 is exposed from the back surface side of the encapsulation resin portion 70 and serves as a heat dissipation surface.
  • the surface of the sealing resin portion 70 and the heat radiation surface of the second heat sink 41 are substantially flush with each other.
  • the semiconductor device 100 the heat generated from the semiconductor chip 10 is transferred to the second heat sink 41 and radiated from the heat radiation surface of the second heat sink 41. In this way, the semiconductor device 100 can suppress the occurrence of defects in the semiconductor chip 10 due to heat even if the semiconductor chip 10 generates heat.
  • the second heat sink 41 has a surface facing the terminal 20 and a side surface connecting the facing surface and the heat radiation surface covered with the sealing resin portion 70. That is, the second heat sink 41 is covered with the sealing resin portion 70 in a state where the sealing resin portion 70 is in contact with the surface facing the terminal 20 and the side surface. The surface of the second heat sink 41 facing the terminal 20 is covered with the sealing resin portion 70 around the area where the connection member is provided.
  • the second main terminal 42 is connected to the second heat sink 41.
  • the second main terminal 42 is a portion protruding from the second heat sink 41.
  • the second main terminal 42 projects to the outside from the same side surface of the encapsulating resin portion 70 as the first main terminal 32.
  • the second main terminal 42 is electrically connected to the electrode 14 of the semiconductor chip 10 via the second heat sink 41. Therefore, it can be said that the second heat sink 41 has a function as a heat dissipation portion and a function as an electric conduction path. In other words, the second heat sink 41 has a function of electrically relaying the electrode 14 and the second main terminal 42.
  • the second terminal member 40 of the present disclosure is not limited to the above configuration, the second heat sink 41 and the second main terminal 42 are configured as separate bodies, and the second heat sink 41 and the second main terminal 42 are conductive. It may be connected by a connecting member.
  • the second heat sink 41 can be regarded as the first conductive member.
  • the terminal 20 can be made of the same material as both heat sinks 31 and 41. Thereby, the semiconductor device 100 can ensure thermal conductivity and electrical conductivity on the front surface side and the back surface side of the semiconductor chip 10.
  • the terminal 20 may have a coefficient of linear expansion different from that of the heat sinks 31 and 41 and the semiconductor substrate 11.
  • the linear expansion coefficient ⁇ 1 of the terminal 20 is preferably a value between the linear expansion coefficient ⁇ 2 of the heat sinks 31 and 41 and the linear expansion coefficient ⁇ 3 of the semiconductor substrate 11. More specifically, the relationship between these linear expansion coefficients is preferably ⁇ 3 ⁇ 1 ⁇ 2.
  • the semiconductor device 100 can suppress warpage due to the difference in linear expansion coefficient between the terminal 20, both heat sinks 31 and 41, and the semiconductor substrate 11. Accordingly, the semiconductor device 100 can suppress the stress applied to the semiconductor substrate 11, the stress applied to the connecting portion between the semiconductor chip 10 and the first heat sink 31, and the stress applied to the connecting portion between the semiconductor chip 10 and the terminal 20. ..
  • the signal terminal 50 is electrically connected to the pad 16 via a wire 60, as shown in FIG.
  • the wire 60 is connected to the signal terminal 50 and the pad 16 by, for example, bonding.
  • a part of the signal terminal 50 is covered with the sealing resin 70, and the other parts of the signal terminal 50 project from the sealing resin 70.
  • the signal terminal 50 projects to the outside from the side surface of the sealing resin portion 70, which is opposite to the surface opposite to the first main terminal 32 and the second main terminal 42.
  • the first terminal member 30, the semiconductor chip 10, the terminal 20, and the second terminal member 40 are stacked in this order in the Z direction. Moreover, the semiconductor chip 10, the terminal 20, the first terminal member 30, the second terminal member 40, the signal terminal 50, and the wire 60 form an integrated structure. The structure is covered with the sealing resin portion 70 with a part of the terminals 32, 42, 50 and the heat radiation surface exposed.
  • the sealing resin part 70 is made of, for example, an epoxy resin.
  • the sealing resin portion 70 has a substantially rectangular shape in a plan view, and has one surface orthogonal to the Z direction, a back surface opposite to the one surface, and a side surface connecting the one surface and the back surface. In the semiconductor device 100, the semiconductor chip 10 and each connection point are protected by the sealing resin portion 70.
  • the semiconductor chip 10 includes a semiconductor substrate 11, gate wirings 12 and 13, electrodes 14, an insulating portion 15, and the like.
  • the semiconductor substrate 11 is mainly composed of silicon or silicon carbide. That is, the semiconductor substrate 11 can employ a silicon semiconductor or a wide band gap semiconductor.
  • a semiconductor substrate 11 having silicon carbide as a main component and a MOSFET formed as a power transistor is adopted.
  • the semiconductor substrate 11 may be a wide band gap semiconductor other than silicon carbide.
  • the semiconductor substrate 11 is formed with power transistors such as insulated gate bipolar transistors (IGBTs) and MOSFETs. Since the power transistor emits heat when it operates, it can be said to be a heating element. As shown in FIG. 2, the semiconductor chip 10 has a substantially rectangular plane shape.
  • IGBTs insulated gate bipolar transistors
  • MOSFETs MOSFETs
  • the MOSFET has a so-called vertical structure so that a current flows in the Z direction.
  • the semiconductor substrate 11 has an electrode 14 as a source electrode formed on one surface side (front surface side) in the Z direction, and a drain electrode formed on the back surface side opposite to the source electrode.
  • the drain electrode is formed on almost the entire back surface.
  • a plurality of pads 16 are formed on one surface side of the semiconductor substrate 11.
  • the pad 16 is a signal electrode.
  • the semiconductor chip 10 has a plurality of pads 16.
  • the plurality of pads 16 are formed side by side in the X direction at the end opposite to the formation region of the electrode 14 in the Y direction.
  • One pad 16 is connected to a gate wiring, for example, for a gate electrode.
  • the semiconductor substrate 11 has a plurality of active regions a1 to a4, which are regions in which MOSFETs, which are elements, are formed, and inactive regions na1 to na5, which are regions in which no elements are formed.
  • Each active area a1 to a4 has an area to which the electrode 14 is connected. Further, each of the active regions a1 to a4 can be said to be a region in which a drain current flows or a MOSFET operating region.
  • a plurality of active regions a1 to a4 are formed at four locations in the X direction is adopted. That is, in the semiconductor substrate 11, a plurality of active regions a1 to a4 extending in the Y direction are formed side by side in the X direction. The active areas a1 to a4 are formed with a space therebetween.
  • the present disclosure adopts, as an example, an example in which four active areas a1 to a4 are formed.
  • the present disclosure is not limited to this, and two active regions may be formed, or five or more active regions may be formed.
  • Gate lines which will be described later, are arranged on the non-active areas na1 to na5.
  • the non-active areas na1 to na5 are arranged between the active areas and on the outer periphery of the active area.
  • a breakdown voltage structure portion such as a guard ring is formed in the non-active regions na1 to na5.
  • the second non-active area na2 is formed between the first active area a1 and the second active area a2.
  • the third non-active area na3 is formed between the second active area a2 and the third active area a3.
  • the fourth non-active area na4 is formed between the third active area a3 and the fourth active area a4.
  • the first inactive region na1 and the fifth inactive region na5 are formed on the outer periphery of the active regions a1 to a4.
  • reference numerals na1 and na5 are given to the inactive areas formed on the outer periphery of the active areas a1 to a4.
  • the first inactive region na1 and the fifth inactive region na5 can be regarded as continuous inactive regions surrounding the outer circumferences of the active regions a1 to a4. Therefore, in this embodiment, it can be said that four inactive regions na1 to na5 are formed.
  • the present disclosure is not limited to this, and it suffices that the number of inactive regions is formed according to the number of active regions.
  • gate wirings 12 and 13 are formed on the non-active areas na1 to na5.
  • the gate wirings 12 and 13 are wirings for applying a voltage to the gate of the MOSFET.
  • the gate wirings 12 and 13 are electrically connected to the pad 16.
  • the gate wirings 12 and 13 are covered with an insulating portion 15 as an insulating layer.
  • the semiconductor chip 10 has a first gate wiring 12 and a second gate wiring 13 formed as gate wiring.
  • the first gate wiring 12 includes a polysilicon layer 12a serving as a polysilicon wiring and an aluminum layer 12b serving as a metal wiring stacked on the polysilicon layer 12a.
  • the second gate wiring 13 has a polysilicon layer as a polysilicon wiring but does not have a metal wiring such as an aluminum layer. That is, the second gate wiring 13 can be regarded as a wiring obtained by removing the aluminum layer 12b from the first gate wiring 12. Therefore, the second gate wiring 13 has a smaller thickness in the Z direction than the first gate wiring 12.
  • the first gate wiring 12 is formed on the first inactive region na1, the third inactive region na3, and the fifth inactive region na5. Therefore, the first gate wiring 12 is formed so as to surround the electrode 14.
  • the second gate wiring 13 is formed on the second inactive region na2 and the fourth inactive region na4.
  • the electrode 14 corresponds to the surface electrode. As shown in FIGS. 2 and 3, the electrode 14 is arranged on the surface side of the active regions a1 to a4 and electrically connected to the active regions a1 to a4. In the present embodiment, two electrodes, that is, the electrode 14 electrically connected to the first active region a1 and the second active region a2, and the electrode 14 electrically connected to the third active region a3 and the fourth active region a4 are provided. The formed example is adopted.
  • the electrode 14 is provided across the second gate wiring 13 via the insulating portion 15. As shown in FIG. 4, the electrode 14 includes a connection part 141 connected to the active regions a1 to a4, and a bridge part 142 arranged on the second gate line 13 and continuous between the two connection parts 141. .. The connection part 141 and the bridge part 142 are continuously provided. That is, the electrode 14 can be said to be an electrode layer in which the connecting portion 141 and the bridging portion 142 are continuously formed.
  • the bridge portion 142 is arranged on the second gate wiring 13 via the insulating portion 15.
  • the electrode 14 is also provided on the second gate wiring 13 and the insulating portion 15, and thus has a partially raised shape corresponding to the second gate wiring 13 and the insulating portion 15. Therefore, the second gate wiring 13 is formed so as to be sandwiched by the electrodes 14. It can also be said that the second gate wiring 13 is surrounded by the semiconductor substrate 11 and the electrode 14.
  • the electrode 14 is provided across the second gate wiring 13. Therefore, the semiconductor device 100 can suppress the sliding of the electrode on the second gate wiring 13 as compared with the case where the electrode 14 is divided on the gate wiring. Therefore, the semiconductor device 100 can suppress the electrode 14 from short-circuiting with the second gate wiring 13.
  • the second gate wiring 13 has polysilicon wiring but does not have metal wiring. Therefore, the semiconductor device 100 can suppress the electrode 14 from short-circuiting with the second gate wiring 13 even if the electrode 14 slides. That is, the semiconductor device 100 can suppress the electrode 14 from short-circuiting with the second gate wiring 13 even if the electrode 14 slides in the X direction. Thus, the semiconductor device 100 can improve the electrical performance.
  • the electrode 14 is provided with the second connecting portion 82 on the electrode surface. Therefore, the electrode surface of the electrode 14 may be subjected to a surface treatment for improving the bonding force with the second connecting portion 82.
  • the surface treatment is an antioxidant treatment, a treatment for improving the wettability of solder, or the like.
  • plating treatment is performed as an example of surface treatment. Therefore, the electrode 14 has the plating layer 143 formed on the surface of the electrode. Thereby, the semiconductor device 100 can improve the connection state between the semiconductor chip 10 and the terminal 20 as compared with the case where the surface treatment is not performed.
  • the terminal 20 and a part of the first gate wiring 12 are provided so as to face each other is adopted.
  • the first gate wiring 12 arranged between the electrodes 14 is arranged in a region facing the terminal 20.
  • the terminal 20 may be provided at a position that does not face the first gate wiring 12. That is, the first gate wiring 12 may not be provided in the facing region of the terminal 20, but may be provided only around the facing region of the terminal 20.
  • the configurations of the first gate wiring 12 and the second gate wiring 13 are not limited to the above.
  • the first gate wiring 12 is a gate wiring provided on the front surface side of the inactive region, and may be arranged around the electrode 14. That is, the first gate wiring 12 may not be provided at a position (opposing region) facing the electrode 14.
  • the second gate wiring 13 and the gate wiring provided on the surface side of the inactive region may be provided at a position facing the electrode 14. That is, the second gate wiring 13 may be provided between the semiconductor substrate 11 and the electrode 14.
  • Modification 1 The semiconductor device of Modification 1 is different from the above embodiment in the configuration of the semiconductor chip 10a. As shown in FIG. 5, the semiconductor chip 10a is provided with a temperature sensitive diode 17. Further, in the present embodiment, as an example, the temperature sensing diode 17 is provided in the area facing the terminal 20. The temperature sensitive diode 17 is provided to detect the temperature of the semiconductor substrate 11.
  • the temperature sensitive diode 17 is provided in the non-conductive area. That is, the temperature sensitive diode 17 is provided in the inactive region.
  • the first pad 16a is electrically connected to the anode side via the first wiring 17a
  • the second pad 16b is electrically connected to the cathode side via the second wiring 17b. Has been done.
  • the semiconductor device of Modification 1 can achieve the same effect as the semiconductor device 100. Furthermore, the semiconductor device of Modification 1 can output the temperature of the semiconductor substrate 11.
  • Modification 2 The semiconductor device of Modification 2 is different from that of Modification 1 in the configuration of the semiconductor chip 10b. As shown in FIG. 6, the semiconductor chip 10 b is provided with the temperature sensitive diode 17 at a position not facing the terminal 20. That is, in the semiconductor chip 10b, the temperature sensitive diode 17 is provided around the area facing the terminal 20.
  • the semiconductor device of Modification 2 can achieve the same effect as the semiconductor device of Modification 1.
  • the semiconductor device of Modification 3 is different from the above embodiment in the configuration of the semiconductor substrate 11a.
  • the semiconductor chip 10c includes a semiconductor substrate 11a.
  • the semiconductor substrate 11a has a first active region a11, a second active region a12, a third active region a13, a fourth active region a14, a fifth active region a15, and a sixth active region a16.
  • the semiconductor substrate 11a has inactive regions formed between and around these active regions a11 to a16.
  • the first active region a11, the third active region a13, and the fifth active region a15 are arranged side by side in the Y direction
  • the second active region a12, the fourth active region a14, and the sixth active region a16 are Y. They are arranged side by side.
  • the first active region a11 and the second active region a12 are arranged side by side in the X direction.
  • the third active region a13 and the fourth active region a14 are arranged side by side in the X direction.
  • the fifth active region a15 and the sixth active region a16 are arranged side by side in the X direction.
  • the electrodes 14 are provided at three locations.
  • the first electrode 14 is provided over the first active region a11 and the second active region a12.
  • the second electrode 14 is provided over the third active region a13 and the fourth active region a14.
  • the third electrode 14 is provided over the fifth active region a15 and the sixth active region a16.
  • the first active area a11, the third active area a13, and the fifth active area a15 arranged side by side in the Y direction are collectively referred to as a first active row.
  • the second active area a12, the fourth active area a14, and the sixth active area a16 are collectively referred to as a second active row.
  • the first active area a11 and the second active area a12 are the first active row
  • the third active area a13 and the fourth active area a14 are the second active row
  • the fifth active area a15 and the sixth active area a16 are the third. Called active row.
  • the first gate line 12 is on the inactive region formed around the active areas a11 to s16, between the first active row and the second active row, and between the second active row and the third active row. It is located in.
  • the second gate wiring 13 is arranged on the inactive region formed between the first active column and the second active column.
  • the second gate wiring 13 is provided in place of the first gate wiring 12 between the first active row and the second active row and between the second active row and the third active row. It may be arranged. Accordingly, the semiconductor device can prevent the electrode 14 from short-circuiting with the second gate wiring 13 even if the electrode 14 slides not only in the X direction but also in the Y direction.
  • the semiconductor device of Modification 3 can achieve the same effects as the semiconductor device 100. Further, in the semiconductor device, when the electrodes 14 are divided on the non-active region, the electrode 14 and the gate wiring may be short-circuited as the number of divisions of the active region is increased, if the semiconductor substrate has the same physical size. Becomes higher. However, since the semiconductor device of Modification 3 is configured as described above, a short circuit can be suppressed even if the number of divisions of the active region increases.

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
PCT/JP2020/000817 2019-02-13 2020-01-14 半導体装置 Ceased WO2020166251A1 (ja)

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JP2020136315A (ja) 2020-08-31
CN113491008A (zh) 2021-10-08

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