JP7097964B2 - 配線基板 - Google Patents
配線基板 Download PDFInfo
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- JP7097964B2 JP7097964B2 JP2020527479A JP2020527479A JP7097964B2 JP 7097964 B2 JP7097964 B2 JP 7097964B2 JP 2020527479 A JP2020527479 A JP 2020527479A JP 2020527479 A JP2020527479 A JP 2020527479A JP 7097964 B2 JP7097964 B2 JP 7097964B2
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- conductor layer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
- H05K3/4655—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern by using a laminate characterized by the insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09609—Via grid, i.e. two-dimensional array of vias or holes in a single plane
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
3 ビルドアップ用絶縁層
8 ビアホール
9 第1導体層
10 第2導体層
11 第3導体層
11a 張り出し部
12 第4導体層
13 ビアランド
Claims (7)
- 絶縁層と、
該絶縁層上に設けられた電極と、を備え、
前記電極は、
該絶縁層の表面に位置しており、ニッケルおよびクロム;周期表の4族に属する金属;
あるいは周期表の6族に属する金属のいずれか一つを含む第1導体層と、
該第1導体層上の外周縁よりも内側に位置する銅を含む第2導体層と、
前記第1導体層および前記第2導体層を被覆する状態で前記絶縁層の表面に位置するニ
ッケルを含む第3導体層と、
該第3導体層を被覆する状態で位置する金を含む第4導体層と、
を有しており、
前記第3導体層は、前記第1導体層の外周縁よりも外側に張り出しているとともに前記絶縁層との間に隙間を有して位置する張り出し部を有しており、
前記第4導体層は、前記張り出し部を含む前記第3導体層を被覆しており、前記隙間にも位置して前記絶縁層に亘り、前記張り出し部の外周縁よりも外側に張り出している、ことを特徴とする配線基板。 - 前記絶縁層は、該絶縁層の下側に位置するビアランドを底部とするビアホールを有して
おり、前記第1導体層は、前記ビアホールの開口周囲および前記ビアホールの内側におけ
る前記絶縁層表面に位置している請求項1に記載の配線基板。 - 平面視において、前記張り出し部が位置する前記絶縁層の表面粗さは、前記第1導体層
が位置する前記絶縁層の表面粗さよりも大きい請求項1または2に記載の配線基板。 - 前記張り出し部が位置する前記絶縁層の表面粗さが0.05~0.2μmであり、前記
第1導体層が位置する前記絶縁層の表面粗さが0.02~0.1μmである請求項3に記
載の配線基板。 - 前記絶縁層が、コア用絶縁層と、該コア用絶縁層の上面および下面に位置するビルドア
ップ用絶縁層とを含み、前記電極が前記上面および下面のビルドアップ用絶縁層の一方ま
たは両方に位置する請求項1~4のいずれかに記載の配線基板。 - 前記第3導体層の最表面が、パラジウム膜で形成されている請求項1~5のいずれかに
記載の配線基板。 - コア用絶縁層と、
該コア用絶縁層の上面および下面に位置するビルドアップ用絶縁層と、
最上層のビルドアップ用絶縁層の上面に位置する第1電極と、
最下層のビルドアップ用絶縁層の下面に位置する第2電極と、を備え、
前記第1電極は、
前記最上層のビルドアップ用絶縁層の表面に位置しており、ニッケルおよびクロム;周
期表の4族に属する金属;あるいは周期表の6族に属する金属のいずれか一つを含む第1
導体層と、
該第1導体層上の外周縁よりも内側に位置する銅を含む第2導体層と、
前記第1導体層および前記第2導体層を被覆する状態で前記絶縁層の表面に位置するニ
ッケルを含む第3導体層と、
該第3導体層を被覆する状態で位置する金を含む第4導体層と、
を有しており、
前記第3導体層は、前記第1導体層の外周縁よりも外側に張り出しているとともに前記絶縁層との間に隙間を有して位置する張り出し部を有しており、
前記第4導体層は、前記張り出し部を含む前記第3導体層を被覆しており、前記隙間にも位置して前記絶縁層に亘り、前記張り出し部の外周縁よりも外側に張り出している、ことを特徴とする配線基板。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018121022 | 2018-06-26 | ||
JP2018121022 | 2018-06-26 | ||
PCT/JP2019/024729 WO2020004271A1 (ja) | 2018-06-26 | 2019-06-21 | 配線基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2020004271A1 JPWO2020004271A1 (ja) | 2021-06-24 |
JP7097964B2 true JP7097964B2 (ja) | 2022-07-08 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2020527479A Active JP7097964B2 (ja) | 2018-06-26 | 2019-06-21 | 配線基板 |
Country Status (7)
Country | Link |
---|---|
US (1) | US11602048B2 (ja) |
EP (1) | EP3817525A4 (ja) |
JP (1) | JP7097964B2 (ja) |
KR (1) | KR102493591B1 (ja) |
CN (1) | CN112219458B (ja) |
TW (1) | TWI703682B (ja) |
WO (1) | WO2020004271A1 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
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CN114080088B (zh) * | 2020-08-10 | 2024-05-31 | 鹏鼎控股(深圳)股份有限公司 | 电路板及其制备方法 |
GB2609810A (en) * | 2021-01-28 | 2023-02-15 | Boe Technology Group Co Ltd | Wiring substrate, array substrate, and light emitting module |
JP2022178590A (ja) * | 2021-05-20 | 2022-12-02 | Tdk株式会社 | 電子部品 |
TW202325108A (zh) * | 2021-12-09 | 2023-06-16 | 群創光電股份有限公司 | 電子裝置 |
TW202341824A (zh) * | 2022-01-31 | 2023-10-16 | 日商京瓷股份有限公司 | 配線基板 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002185108A (ja) | 2000-12-11 | 2002-06-28 | Kyocera Corp | 配線基板 |
US20060000877A1 (en) | 2004-06-30 | 2006-01-05 | Phoenix Precision Technology Corporation | Method for fabricating electrical connection structure of circuit board |
JP2009117542A (ja) | 2007-11-05 | 2009-05-28 | Panasonic Electric Works Co Ltd | 回路基板及びその製造方法 |
JP2015216344A (ja) | 2014-04-21 | 2015-12-03 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
Family Cites Families (18)
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JP2886317B2 (ja) * | 1990-10-05 | 1999-04-26 | 富士通株式会社 | 配線基板およびその製造方法 |
JPH0992964A (ja) | 1995-09-25 | 1997-04-04 | Ibiden Co Ltd | プリント配線板の製造方法 |
JP2003243802A (ja) * | 2002-02-21 | 2003-08-29 | Matsushita Electric Ind Co Ltd | プリント配線板の製造方法とプリント配線板およびそれを用いた電子部品の実装方法 |
US6815126B2 (en) * | 2002-04-09 | 2004-11-09 | International Business Machines Corporation | Printed wiring board with conformally plated circuit traces |
JP2004111471A (ja) * | 2002-09-13 | 2004-04-08 | Kyocera Corp | 配線基板 |
JP2004165573A (ja) * | 2002-11-15 | 2004-06-10 | Kyocera Corp | 配線基板の製造方法 |
JP4721827B2 (ja) * | 2005-08-29 | 2011-07-13 | 京セラ株式会社 | 配線基板の製造方法 |
JP2007165816A (ja) * | 2005-11-15 | 2007-06-28 | Mitsui Mining & Smelting Co Ltd | プリント配線基板、その製造方法およびその使用方法 |
CN101310571A (zh) * | 2005-11-15 | 2008-11-19 | 三井金属矿业株式会社 | 印刷线路板及其制造方法和使用方法 |
JP2008258520A (ja) * | 2007-04-09 | 2008-10-23 | Shinko Electric Ind Co Ltd | 配線基板の製造方法及び配線基板 |
US7719363B2 (en) * | 2008-08-01 | 2010-05-18 | Nuvoton Technology Corporation | Method and apparatus for output amplifier protection |
KR101627574B1 (ko) * | 2008-09-22 | 2016-06-21 | 쿄세라 코포레이션 | 배선 기판 및 그 제조 방법 |
JP5150553B2 (ja) * | 2009-04-16 | 2013-02-20 | 日本特殊陶業株式会社 | 配線基板及びその製造方法 |
US8535993B2 (en) * | 2010-09-17 | 2013-09-17 | Infineon Technologies Ag | Semiconductor device and method using a sacrificial layer |
JP2013197245A (ja) * | 2012-03-19 | 2013-09-30 | Ibiden Co Ltd | プリント配線板 |
JP5942074B2 (ja) * | 2012-06-29 | 2016-06-29 | 京セラ株式会社 | 配線基板 |
KR20150002492A (ko) | 2013-06-28 | 2015-01-07 | 쿄세라 서킷 솔루션즈 가부시키가이샤 | 배선 기판 |
JP2015144152A (ja) * | 2014-01-31 | 2015-08-06 | 京セラサーキットソリューションズ株式会社 | 配線基板の製造方法 |
-
2019
- 2019-06-21 KR KR1020207033919A patent/KR102493591B1/ko active IP Right Grant
- 2019-06-21 EP EP19826035.8A patent/EP3817525A4/en active Pending
- 2019-06-21 CN CN201980035278.3A patent/CN112219458B/zh active Active
- 2019-06-21 US US17/057,776 patent/US11602048B2/en active Active
- 2019-06-21 JP JP2020527479A patent/JP7097964B2/ja active Active
- 2019-06-21 WO PCT/JP2019/024729 patent/WO2020004271A1/ja unknown
- 2019-06-26 TW TW108122382A patent/TWI703682B/zh active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002185108A (ja) | 2000-12-11 | 2002-06-28 | Kyocera Corp | 配線基板 |
US20060000877A1 (en) | 2004-06-30 | 2006-01-05 | Phoenix Precision Technology Corporation | Method for fabricating electrical connection structure of circuit board |
JP2009117542A (ja) | 2007-11-05 | 2009-05-28 | Panasonic Electric Works Co Ltd | 回路基板及びその製造方法 |
JP2015216344A (ja) | 2014-04-21 | 2015-12-03 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20210227691A1 (en) | 2021-07-22 |
US11602048B2 (en) | 2023-03-07 |
WO2020004271A1 (ja) | 2020-01-02 |
KR20210003219A (ko) | 2021-01-11 |
TWI703682B (zh) | 2020-09-01 |
KR102493591B1 (ko) | 2023-01-31 |
JPWO2020004271A1 (ja) | 2021-06-24 |
EP3817525A4 (en) | 2022-03-30 |
CN112219458B (zh) | 2024-06-11 |
TW202006901A (zh) | 2020-02-01 |
CN112219458A (zh) | 2021-01-12 |
EP3817525A1 (en) | 2021-05-05 |
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