JP6836022B2 - 半導体基板、半導体基板の製造方法及び半導体素子の製造方法 - Google Patents
半導体基板、半導体基板の製造方法及び半導体素子の製造方法 Download PDFInfo
- Publication number
- JP6836022B2 JP6836022B2 JP2020559573A JP2020559573A JP6836022B2 JP 6836022 B2 JP6836022 B2 JP 6836022B2 JP 2020559573 A JP2020559573 A JP 2020559573A JP 2020559573 A JP2020559573 A JP 2020559573A JP 6836022 B2 JP6836022 B2 JP 6836022B2
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- layer
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- semiconductor
- removal layer
- etching
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- 239000004065 semiconductor Substances 0.000 title claims description 172
- 239000000758 substrate Substances 0.000 title claims description 141
- 238000004519 manufacturing process Methods 0.000 title claims description 24
- 238000005530 etching Methods 0.000 claims description 119
- 239000000463 material Substances 0.000 claims description 42
- 238000000034 method Methods 0.000 claims description 26
- 238000005304 joining Methods 0.000 claims description 17
- 238000005520 cutting process Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 271
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 14
- 239000010409 thin film Substances 0.000 description 12
- 239000000203 mixture Substances 0.000 description 10
- 239000000243 solution Substances 0.000 description 9
- 239000011368 organic material Substances 0.000 description 8
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 238000002474 experimental method Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 230000003746 surface roughness Effects 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910010272 inorganic material Inorganic materials 0.000 description 2
- 239000011147 inorganic material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 229910000041 hydrogen chloride Inorganic materials 0.000 description 1
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000001000 micrograph Methods 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 150000007524 organic acids Chemical class 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
- H01L21/30612—Etching of AIIIBV compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
- H01L21/30612—Etching of AIIIBV compounds
- H01L21/30621—Vapour phase etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02387—Group 13/15 materials
- H01L21/02392—Phosphides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02387—Group 13/15 materials
- H01L21/02395—Arsenides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02463—Arsenides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02502—Layer structure consisting of two layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02543—Phosphides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02546—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68363—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Recrystallisation Techniques (AREA)
- Weting (AREA)
- Drying Of Semiconductors (AREA)
- Led Devices (AREA)
- Bipolar Transistors (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Cleaning Or Drying Semiconductors (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2021016416A JP7441525B2 (ja) | 2018-12-10 | 2021-02-04 | 半導体基板、半導体基板の製造方法及び半導体素子の製造方法 |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2018230683 | 2018-12-10 | ||
| JP2018230683 | 2018-12-10 | ||
| PCT/JP2019/040926 WO2020121649A1 (ja) | 2018-12-10 | 2019-10-17 | 半導体基板、半導体基板の製造方法及び半導体素子の製造方法 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2021016416A Division JP7441525B2 (ja) | 2018-12-10 | 2021-02-04 | 半導体基板、半導体基板の製造方法及び半導体素子の製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPWO2020121649A1 JPWO2020121649A1 (ja) | 2021-02-15 |
| JP6836022B2 true JP6836022B2 (ja) | 2021-02-24 |
Family
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Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2020559573A Active JP6836022B2 (ja) | 2018-12-10 | 2019-10-17 | 半導体基板、半導体基板の製造方法及び半導体素子の製造方法 |
| JP2021016416A Active JP7441525B2 (ja) | 2018-12-10 | 2021-02-04 | 半導体基板、半導体基板の製造方法及び半導体素子の製造方法 |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2021016416A Active JP7441525B2 (ja) | 2018-12-10 | 2021-02-04 | 半導体基板、半導体基板の製造方法及び半導体素子の製造方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US11894272B2 (enExample) |
| JP (2) | JP6836022B2 (enExample) |
| CN (1) | CN113169049B (enExample) |
| TW (2) | TWI743610B (enExample) |
| WO (1) | WO2020121649A1 (enExample) |
Family Cites Families (35)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0646026Y2 (ja) | 1987-08-19 | 1994-11-24 | 沖電気工業株式会社 | メンブレンキ−ボ−ドの防塵構造 |
| JP2560601B2 (ja) * | 1993-03-12 | 1996-12-04 | 日本電気株式会社 | 元素半導体基板上の金属膜/化合物半導体積層構造の製造方法 |
| JP3377022B2 (ja) * | 1997-01-23 | 2003-02-17 | 日本電信電話株式会社 | ヘテロ接合型電界効果トランジスタの製造方法 |
| JP3371871B2 (ja) * | 1999-11-16 | 2003-01-27 | 日本電気株式会社 | 半導体装置の製造方法 |
| JP3716906B2 (ja) * | 2000-03-06 | 2005-11-16 | 日本電気株式会社 | 電界効果トランジスタ |
| KR100438895B1 (ko) * | 2001-12-28 | 2004-07-02 | 한국전자통신연구원 | 고전자 이동도 트랜지스터 전력 소자 및 그 제조 방법 |
| JP3813123B2 (ja) | 2002-12-25 | 2006-08-23 | 株式会社沖データ | 半導体装置及びledヘッド |
| JP4315744B2 (ja) * | 2003-06-25 | 2009-08-19 | 株式会社沖データ | 積層体及び半導体装置の製造方法 |
| JP2005191022A (ja) * | 2003-12-24 | 2005-07-14 | Matsushita Electric Ind Co Ltd | 電界効果トランジスタ及びその製造方法 |
| US7205176B2 (en) * | 2004-05-24 | 2007-04-17 | Taiwan Semiconductor Manufacturing Company | Surface MEMS mirrors with oxide spacers |
| JP4518886B2 (ja) * | 2004-09-09 | 2010-08-04 | シャープ株式会社 | 半導体素子の製造方法 |
| US20060208265A1 (en) * | 2005-03-17 | 2006-09-21 | Hitachi Cable, Ltd. | Light emitting diode and light emitting diode array |
| KR101430587B1 (ko) | 2006-09-20 | 2014-08-14 | 더 보오드 오브 트러스티스 오브 더 유니버시티 오브 일리노이즈 | 전사가능한 반도체 구조들, 디바이스들 및 디바이스 컴포넌트들을 만들기 위한 릴리스 방안들 |
| JP4200389B2 (ja) * | 2007-02-22 | 2008-12-24 | セイコーエプソン株式会社 | 光素子 |
| JP4466668B2 (ja) | 2007-03-20 | 2010-05-26 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
| JP2008270794A (ja) * | 2007-03-29 | 2008-11-06 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
| JP4871973B2 (ja) | 2009-04-28 | 2012-02-08 | 株式会社沖データ | 半導体薄膜素子の製造方法並びに半導体ウエハ、及び、半導体薄膜素子 |
| JP2011249776A (ja) * | 2010-04-30 | 2011-12-08 | Sumitomo Chemical Co Ltd | 半導体基板、半導体基板の製造方法、電子デバイス、および電子デバイスの製造方法 |
| JP5893246B2 (ja) * | 2010-11-08 | 2016-03-23 | キヤノン株式会社 | 面発光レーザ及び面発光レーザアレイ、面発光レーザの製造方法及び面発光レーザアレイの製造方法、面発光レーザアレイを備えた光学機器 |
| JP2013183125A (ja) * | 2012-03-05 | 2013-09-12 | Sharp Corp | 化合物半導体素子エピタキシャル成長基板 |
| JP2013211355A (ja) * | 2012-03-30 | 2013-10-10 | Oki Data Corp | 3端子発光素子、3端子発光素子アレイ、プリントヘッドおよび画像形成装置 |
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| KR102282141B1 (ko) * | 2014-09-02 | 2021-07-28 | 삼성전자주식회사 | 반도체 발광소자 |
| WO2016079929A1 (ja) * | 2014-11-21 | 2016-05-26 | 信越半導体株式会社 | 発光素子及び発光素子の製造方法 |
| US9299615B1 (en) * | 2014-12-22 | 2016-03-29 | International Business Machines Corporation | Multiple VT in III-V FETs |
| US9444019B1 (en) * | 2015-09-21 | 2016-09-13 | Epistar Corporation | Method for reusing a substrate for making light-emitting device |
| US9461159B1 (en) * | 2016-01-14 | 2016-10-04 | Northrop Grumman Systems Corporation | Self-stop gate recess etching process for semiconductor field effect transistors |
| US9685539B1 (en) * | 2016-03-14 | 2017-06-20 | International Business Machines Corporation | Nanowire isolation scheme to reduce parasitic capacitance |
| JP6729275B2 (ja) * | 2016-10-12 | 2020-07-22 | 信越半導体株式会社 | 発光素子及び発光素子の製造方法 |
| WO2019134075A1 (en) * | 2018-01-03 | 2019-07-11 | Xiamen Sanan Integrated Circuit Co., Ltd. | Consumer semiconductor laser |
| JP6431631B1 (ja) | 2018-02-28 | 2018-11-28 | 株式会社フィルネックス | 半導体素子の製造方法 |
| US10461154B1 (en) * | 2018-06-21 | 2019-10-29 | International Business Machines Corporation | Bottom isolation for nanosheet transistors on bulk substrate |
| US11087974B2 (en) * | 2018-10-08 | 2021-08-10 | The Regents Of The University Of Michigan | Preparation of compound semiconductor substrate for epitaxial growth via non-destructive epitaxial lift-off |
-
2019
- 2019-10-17 WO PCT/JP2019/040926 patent/WO2020121649A1/ja not_active Ceased
- 2019-10-17 CN CN201980076538.1A patent/CN113169049B/zh active Active
- 2019-10-17 JP JP2020559573A patent/JP6836022B2/ja active Active
- 2019-12-04 TW TW108144217A patent/TWI743610B/zh active
- 2019-12-04 TW TW110133490A patent/TWI804977B/zh active
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2021
- 2021-02-04 JP JP2021016416A patent/JP7441525B2/ja active Active
- 2021-05-25 US US17/330,369 patent/US11894272B2/en active Active
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2023
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| Publication number | Publication date |
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| JPWO2020121649A1 (ja) | 2021-02-15 |
| WO2020121649A1 (ja) | 2020-06-18 |
| TW202038301A (zh) | 2020-10-16 |
| CN113169049B (zh) | 2022-07-05 |
| TWI804977B (zh) | 2023-06-11 |
| US11894272B2 (en) | 2024-02-06 |
| CN113169049A (zh) | 2021-07-23 |
| US12183636B2 (en) | 2024-12-31 |
| JP2021077909A (ja) | 2021-05-20 |
| US20240120238A1 (en) | 2024-04-11 |
| US20210280467A1 (en) | 2021-09-09 |
| TWI743610B (zh) | 2021-10-21 |
| JP7441525B2 (ja) | 2024-03-01 |
| TW202147392A (zh) | 2021-12-16 |
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