JP6780933B2 - 端子構造、端子構造の製造方法、及び配線基板 - Google Patents

端子構造、端子構造の製造方法、及び配線基板 Download PDF

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Publication number
JP6780933B2
JP6780933B2 JP2015247602A JP2015247602A JP6780933B2 JP 6780933 B2 JP6780933 B2 JP 6780933B2 JP 2015247602 A JP2015247602 A JP 2015247602A JP 2015247602 A JP2015247602 A JP 2015247602A JP 6780933 B2 JP6780933 B2 JP 6780933B2
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Japan
Prior art keywords
layer
opening
wiring
protective insulating
insulating layer
Prior art date
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JP2015247602A
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English (en)
Japanese (ja)
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JP2017112318A (ja
JP2017112318A5 (enExample
Inventor
朋幸 下平
朋幸 下平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
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Priority to JP2015247602A priority Critical patent/JP6780933B2/ja
Priority to US15/373,107 priority patent/US9893002B2/en
Publication of JP2017112318A publication Critical patent/JP2017112318A/ja
Publication of JP2017112318A5 publication Critical patent/JP2017112318A5/ja
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/66—Conductive materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/141—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being on at least the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
    • H10W90/794—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2015247602A 2015-12-18 2015-12-18 端子構造、端子構造の製造方法、及び配線基板 Active JP6780933B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2015247602A JP6780933B2 (ja) 2015-12-18 2015-12-18 端子構造、端子構造の製造方法、及び配線基板
US15/373,107 US9893002B2 (en) 2015-12-18 2016-12-08 Terminal structure and wiring substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015247602A JP6780933B2 (ja) 2015-12-18 2015-12-18 端子構造、端子構造の製造方法、及び配線基板

Publications (3)

Publication Number Publication Date
JP2017112318A JP2017112318A (ja) 2017-06-22
JP2017112318A5 JP2017112318A5 (enExample) 2018-11-22
JP6780933B2 true JP6780933B2 (ja) 2020-11-04

Family

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JP2015247602A Active JP6780933B2 (ja) 2015-12-18 2015-12-18 端子構造、端子構造の製造方法、及び配線基板

Country Status (2)

Country Link
US (1) US9893002B2 (enExample)
JP (1) JP6780933B2 (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10128175B2 (en) * 2013-01-29 2018-11-13 Taiwan Semiconductor Manufacturing Company Packaging methods and packaged semiconductor devices
CN106601710B (zh) * 2015-10-19 2021-01-29 富士电机株式会社 半导体装置以及半导体装置的制造方法
US20180138115A1 (en) * 2016-11-11 2018-05-17 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
WO2018182595A1 (en) * 2017-03-29 2018-10-04 Intel Corporation Embedded die microelectronic device with molded component
US10515888B2 (en) * 2017-09-18 2019-12-24 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and method for manufacturing the same
JP6951219B2 (ja) * 2017-11-29 2021-10-20 新光電気工業株式会社 配線基板、半導体装置、及び配線基板の製造方法
US10651052B2 (en) * 2018-01-12 2020-05-12 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
JP7112873B2 (ja) * 2018-04-05 2022-08-04 新光電気工業株式会社 配線基板、半導体パッケージ及び配線基板の製造方法
US10903151B2 (en) * 2018-05-23 2021-01-26 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US20200066626A1 (en) * 2018-08-21 2020-02-27 Intel Corporation Pocket structures, materials, and methods for integrated circuit package supports
JP7370926B2 (ja) * 2020-04-24 2023-10-30 新光電気工業株式会社 端子構造、配線基板及び端子構造の製造方法
JP2022161152A (ja) 2021-04-08 2022-10-21 イビデン株式会社 プリント配線板およびプリント配線板の製造方法
WO2023132231A1 (ja) * 2022-01-07 2023-07-13 株式会社村田製作所 半導体装置
JP2024008020A (ja) * 2022-07-07 2024-01-19 新光電気工業株式会社 配線基板及び配線基板の製造方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07112041B2 (ja) * 1986-12-03 1995-11-29 シャープ株式会社 半導体装置の製造方法
US5795818A (en) * 1996-12-06 1998-08-18 Amkor Technology, Inc. Integrated circuit chip to substrate interconnection and method
JP2003152319A (ja) * 1996-12-27 2003-05-23 Ibiden Co Ltd プリント配線板
KR100343138B1 (ko) * 1999-06-25 2002-07-05 윤종용 기입 마스킹 기능을 갖는 반도체 메모리 장치 및 그 기입 마스킹 방법
TW490821B (en) * 2000-11-16 2002-06-11 Orient Semiconductor Elect Ltd Application of wire bonding technique on manufacture of wafer bump and wafer level chip scale package
TWI378544B (en) * 2007-07-19 2012-12-01 Unimicron Technology Corp Package substrate with electrically connecting structure
US8089156B2 (en) * 2007-10-24 2012-01-03 Panasonic Corporation Electrode structure for semiconductor chip with crack suppressing dummy metal patterns
WO2010046235A1 (en) 2008-10-21 2010-04-29 Atotech Deutschland Gmbh Method to form solder deposits on substrates
CN102474989A (zh) * 2009-10-06 2012-05-23 株式会社藤仓 电路基板
TWI395279B (zh) * 2009-12-30 2013-05-01 財團法人工業技術研究院 微凸塊結構
KR101695353B1 (ko) * 2010-10-06 2017-01-11 삼성전자 주식회사 반도체 패키지 및 반도체 패키지 모듈
JP2012129369A (ja) 2010-12-15 2012-07-05 Ngk Spark Plug Co Ltd 配線基板
WO2014071815A1 (zh) * 2012-11-08 2014-05-15 南通富士通微电子股份有限公司 半导体器件及其形成方法
CN102915986B (zh) * 2012-11-08 2015-04-01 南通富士通微电子股份有限公司 芯片封装结构
JP6057681B2 (ja) * 2012-11-21 2017-01-11 新光電気工業株式会社 配線基板及びその製造方法
JP6232249B2 (ja) * 2013-02-27 2017-11-15 新光電気工業株式会社 半導体装置及び半導体装置の製造方法
US9159683B2 (en) * 2014-02-10 2015-10-13 GlobalFoundries, Inc. Methods for etching copper during the fabrication of integrated circuits
CN105633046A (zh) * 2014-11-20 2016-06-01 三星电子株式会社 半导体装置和包括该半导体装置的半导体封装

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Publication number Publication date
US9893002B2 (en) 2018-02-13
JP2017112318A (ja) 2017-06-22
US20170179012A1 (en) 2017-06-22

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