JP6057681B2 - 配線基板及びその製造方法 - Google Patents
配線基板及びその製造方法 Download PDFInfo
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- JP6057681B2 JP6057681B2 JP2012255040A JP2012255040A JP6057681B2 JP 6057681 B2 JP6057681 B2 JP 6057681B2 JP 2012255040 A JP2012255040 A JP 2012255040A JP 2012255040 A JP2012255040 A JP 2012255040A JP 6057681 B2 JP6057681 B2 JP 6057681B2
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- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0373—Conductors having a fine structure, e.g. providing a plurality of contact points with a structured tool
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/07—Electric details
- H05K2201/0753—Insulation
- H05K2201/0769—Anti metal-migration, e.g. avoiding tin whisker growth
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/099—Coating over pads, e.g. solder resist partly over pads
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
- H05K2201/2072—Anchoring, i.e. one structure gripping into another
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
- H05K2203/0594—Insulating resist or coating with special shaped edges
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1184—Underetching, e.g. etching of substrate under conductors or etching of conductor under dielectrics; Means for allowing or controlling underetching
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
Description
図3〜図7は実施形態の配線基板の製造方法を示す図、図8は実施形態の配線基板を示す図である。以下、実施形態の配線基板の製造方法を説明しながら配線基板の構造について説明する。
前述した実施形態では、バリア金属層としてニッケル層50を例示したが、ニッケル層50の代わりに、コバルト(Co)層などの他のバリア金属層を同様に形成してもよい。
Claims (10)
- 表面に凹部が形成された接続パッドと、
前記接続パッドの凹部の上に開口部を備え、前記開口部の側壁の下端から前記開口部の内側に向けて突出する突出部を有する保護絶縁層と、
前記開口部内の前記接続パッドの上に形成された金属層と、
前記金属層の上に形成されたバンプ電極とを有し、
前記金属層の周縁は、中央よりも盛り上がっており、前記金属層の周縁の高さが最も高い部分は、前記保護絶縁層の開口部の側壁から内側に離れた位置に配置されていることを特徴とする配線基板。 - 前記金属層は、前記接続パッドの上と前記突出部の上とに形成されていることを特徴とする請求項1に記載の配線基板。
- 前記金属層は、無電解めっき層又は電解めっき層であることを特徴とする請求項1又は2に記載の配線基板。
- 前記接続パッドは銅から形成され、前記金属層はニッケルから形成され、前記バンプ電極ははんだから形成されることを特徴とする請求項1乃至3のいずれか一項に記載の配線基板。
- 前記保護絶縁層は、ネガ型の感光性樹脂から形成されることを特徴とする請求項1乃至4のいずれか一項に記載の配線基板。
- 接続パッドを備えた配線基板を用意する工程と、
前記接続パッドの上に開口部を備え、前記開口部の側壁の下端から前記開口部の内側に向けて突出する突出部を有する保護絶縁層を前記配線基板の上に形成する工程と、
前記開口部を通して前記接続パッドの表面に、前記突出部の下面を露出させて凹部を形成する工程と、
前記接続パッドの上に金属層を形成する工程と、
前記金属層の上にバンプ電極を形成する工程とを有し、
前記金属層の周縁は、中央よりも盛り上がって形成され、前記金属層の周縁の高さが最も高い部分は、前記保護絶縁層の開口部の側壁から内側に離れた位置に配置されることを特徴とする配線基板の製造方法。 - 前記金属層を形成する工程において、
前記金属層は、前記接続パッドの上と前記突出部の上とに形成されることを特徴とする請求項6に記載の配線基板の製造方法。 - 前記金属層を形成する工程において、
前記金属層は、無電解めっき又は電解めっきによって形成されることを特徴とする請求項6又は7に記載の配線基板の製造方法。 - 前記接続パッドは銅から形成され、前記金属層はニッケルから形成され、前記バンプ電極ははんだから形成されることを特徴とする請求項6乃至8のいずれか一項に記載の配線基板の製造方法。
- 前記保護絶縁層を形成する工程において、
ネガ型の感光性樹脂をフォトリソグラフィによってパターニングすることを特徴とする請求項6乃至9のいずれか一項に記載の配線基板の製造方法。
Priority Applications (2)
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JP2012255040A JP6057681B2 (ja) | 2012-11-21 | 2012-11-21 | 配線基板及びその製造方法 |
US14/084,038 US9210807B2 (en) | 2012-11-21 | 2013-11-19 | Wiring substrate |
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JP2012255040A JP6057681B2 (ja) | 2012-11-21 | 2012-11-21 | 配線基板及びその製造方法 |
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JP2014103295A JP2014103295A (ja) | 2014-06-05 |
JP2014103295A5 JP2014103295A5 (ja) | 2015-11-26 |
JP6057681B2 true JP6057681B2 (ja) | 2017-01-11 |
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Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
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US10163828B2 (en) * | 2013-11-18 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and fabricating method thereof |
US9468103B2 (en) * | 2014-10-08 | 2016-10-11 | Raytheon Company | Interconnect transition apparatus |
US9660333B2 (en) | 2014-12-22 | 2017-05-23 | Raytheon Company | Radiator, solderless interconnect thereof and grounding element thereof |
JP6780933B2 (ja) * | 2015-12-18 | 2020-11-04 | 新光電気工業株式会社 | 端子構造、端子構造の製造方法、及び配線基板 |
JP2017123459A (ja) | 2016-01-08 | 2017-07-13 | サムソン エレクトロ−メカニックス カンパニーリミテッド. | プリント回路基板 |
JP2017228565A (ja) | 2016-06-20 | 2017-12-28 | ソニー株式会社 | 基板装置、電子機器及び基板装置の製造方法 |
JP6775391B2 (ja) * | 2016-11-18 | 2020-10-28 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
JP6766960B2 (ja) * | 2017-05-26 | 2020-10-14 | 株式会社村田製作所 | 多層配線基板、電子機器、及び、多層配線基板の製造方法 |
JP7112873B2 (ja) | 2018-04-05 | 2022-08-04 | 新光電気工業株式会社 | 配線基板、半導体パッケージ及び配線基板の製造方法 |
US11315844B2 (en) * | 2018-04-26 | 2022-04-26 | Kyocera Corporation | Electronic device mounting board, electronic package, and electronic module |
CN113170579A (zh) * | 2019-02-21 | 2021-07-23 | 华为技术有限公司 | 封装结构及其制备方法 |
JP2020141015A (ja) * | 2019-02-27 | 2020-09-03 | 京セラ株式会社 | 配線基板 |
JP7266454B2 (ja) * | 2019-04-25 | 2023-04-28 | 新光電気工業株式会社 | 配線基板、積層型配線基板、及び配線基板の製造方法 |
JP7370926B2 (ja) | 2020-04-24 | 2023-10-30 | 新光電気工業株式会社 | 端子構造、配線基板及び端子構造の製造方法 |
JP2022082186A (ja) | 2020-11-20 | 2022-06-01 | イビデン株式会社 | 配線基板 |
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JP2001060760A (ja) | 1999-06-18 | 2001-03-06 | Mitsubishi Electric Corp | 回路電極およびその形成方法 |
JP2001264667A (ja) * | 2000-03-15 | 2001-09-26 | Sony Corp | 光スキャニング装置 |
JP3726046B2 (ja) * | 2000-12-19 | 2005-12-14 | 日本電気株式会社 | 回路基板及びそれを用いた電子機器 |
TWI230994B (en) * | 2004-02-25 | 2005-04-11 | Via Tech Inc | Circuit carrier |
JP4185892B2 (ja) * | 2004-06-08 | 2008-11-26 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
JP5142967B2 (ja) * | 2008-12-10 | 2013-02-13 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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US9210807B2 (en) | 2015-12-08 |
US20140138134A1 (en) | 2014-05-22 |
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