JP2019186243A - 配線基板、半導体パッケージ及び配線基板の製造方法 - Google Patents
配線基板、半導体パッケージ及び配線基板の製造方法 Download PDFInfo
- Publication number
- JP2019186243A JP2019186243A JP2018070751A JP2018070751A JP2019186243A JP 2019186243 A JP2019186243 A JP 2019186243A JP 2018070751 A JP2018070751 A JP 2018070751A JP 2018070751 A JP2018070751 A JP 2018070751A JP 2019186243 A JP2019186243 A JP 2019186243A
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- Prior art keywords
- bump
- connection terminal
- wiring board
- diameter
- columnar electrode
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- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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Abstract
Description
第1の実施形態について説明する。第1の実施形態は配線基板に関する。
先ず、配線基板の構造について説明する。図3は、第1の実施形態に係る配線基板の構造を示す断面図である。
次に、配線基板の製造方法について説明する。図4〜図6は、第1の実施形態に係る配線基板の製造方法を示す断面図である。
次に、第2の実施形態について説明する。第2の実施形態は半導体パッケージに関する。図10は、第2の実施形態に係る半導体パッケージ500を示す断面図である。
101 コア配線基板
102 コア基板
200 ソルダレジスト層
210 第1の接続端子
211 第1のポスト
212 第1のバンプ
220 第2の接続端子
221 第2のポスト
222 第2のバンプ
300 半導体チップ
311 第3の接続端子
312 第3のバンプ
321 第4の接続端子
322 第4のバンプ
330 アンダーフィル樹脂
500 半導体パッケージ
Claims (4)
- 配線基板の一方の面に設けられた第1の接続端子及び第2の接続端子、
を有し、
前記第1の接続端子は、
第1の直径を有し、表面が平坦又は凸状の第1の柱状電極と、
前記第1の柱状電極上の第1のバンプと、
を有し、
前記第2の接続端子は、
前記第1の直径よりも大きな第2の直径を有し、表面が凹状の第2の柱状電極と、
前記第2の柱状電極上の第2のバンプと、
を有し、
前記第1のバンプ及び前記第2のバンプの融点は、前記第1の柱状電極及び前記第2の柱状電極の融点よりも低いことを特徴とする配線基板。 - 前記第1の柱状電極及び前記第2の柱状電極は、銅若しくはニッケル又はこれらの両方を含み、
前記第1のバンプ及び前記第2のバンプは、錫又ははんだを含むことを特徴とする請求項1に記載の配線基板。 - 請求項1又は2に記載の配線基板と、
前記配線基板に実装された半導体チップと、
を有し、
前記半導体チップは、
前記第1の接続端子に接続された第3の接続端子と、
前記第2の接続端子に接続された第4の接続端子と、
を有することを特徴とする半導体パッケージ。 - 配線基板の一方の面に、電解めっき法により、第1の直径を有し、表面が平坦又は凸状の第1の柱状電極と、前記第1の直径よりも大きな第2の直径を有し、表面が凹状の第2の柱状電極と、を形成する工程と、
電解めっき法により、前記第1の柱状電極上の第1のバンプと、前記第2の柱状電極上の第2のバンプと、を形成する工程と、
を有し、
前記第1のバンプ及び前記第2のバンプの融点は、前記第1の柱状電極及び前記第2の柱状電極の融点よりも低く、
前記第1のバンプ及び前記第2のバンプの形成後に、前記第1のバンプ及び前記第2のバンプの融点以上、前記第1の柱状電極及び前記第2の柱状電極の融点未満の温度でリフローを行う工程を有することを特徴とする配線基板の製造方法。
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