JP6775349B2 - 不揮発性記憶装置の製造方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims description 38
- 238000003860 storage Methods 0.000 title claims description 13
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- 238000005530 etching Methods 0.000 claims description 36
- 239000011810 insulating material Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 14
- 238000010030 laminating Methods 0.000 claims description 4
- 230000008859 change Effects 0.000 description 52
- 239000007769 metal material Substances 0.000 description 43
- 230000006870 function Effects 0.000 description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 238000010586 diagram Methods 0.000 description 12
- 229910044991 metal oxide Inorganic materials 0.000 description 11
- 150000004706 metal oxides Chemical class 0.000 description 11
- 238000001020 plasma etching Methods 0.000 description 10
- 238000000231 atomic layer deposition Methods 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 229910052681 coesite Inorganic materials 0.000 description 6
- 229910052906 cristobalite Inorganic materials 0.000 description 6
- 229910052682 stishovite Inorganic materials 0.000 description 6
- 229910052905 tridymite Inorganic materials 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 4
- 150000004770 chalcogenides Chemical class 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004166 TaN Inorganic materials 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052798 chalcogen Inorganic materials 0.000 description 1
- 150000001787 chalcogens Chemical class 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052711 selenium Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 229910052714 tellurium Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
- H10B63/24—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes of the Ovonic threshold switching type
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
- H10B63/845—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays the switching components being connected to a common vertical conductor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Shaping switching materials
- H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Shaping switching materials
- H10N70/066—Shaping switching materials by filling of openings, e.g. damascene method
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/823—Device geometry adapted for essentially horizontal current flow, e.g. bridge type devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8833—Binary metal oxides, e.g. TaOx
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Description
図1は、実施例1におけるReRAM10の概略構造の一例を示す縦断面図である。図2は、図1に示したReRAM10のA−A断面の一例を示す図である。図2に示したReRAM10のB−B断面が、図1に対応している。実施例1におけるReRAM10は、複数の電極層11と、複数のセレクタ層12と、複数の電極層16と、複数のメモリセル17とを有する。それぞれの電極層11は、図1のX方向およびY方向に複数配置され、図1のZ方向に延在する。電極層11は、例えばビット線として機能する。電極層11は、第1の配線の一例である。また、X方向は第1の方向の一例であり、Y方向は第2の方向の一例であり、Z方向は第3の方向の一例である。
次に、本実施例におけるReRAM10の製造手順について、図3〜図14を参照しながら説明する。図3は、実施例1におけるReRAM10の製造手順の一例を示すフローチャートである。
図16は、実施例2におけるReRAM10の概略構造の一例を示す縦断面図である。図17は、図16に示したReRAM10のF−F断面の一例を示す図である。図17に示したReRAM10のG−G断面が、図16に対応する。実施例2におけるReRAM10は、複数の電極層11と、複数のセレクタ層12と、複数の電極層16と、複数のメモリセル17とを有する。それぞれのメモリセル17は、セレクタ層12側に配置された中間導電層13と、電極層16側に配置された抵抗変化層14とを有する。なお、以下に説明する点を除き、図16および図17において、図1および図2と同じ符号を付した構成は、図1および図2に示した構成と同一または同様の機能を有するため説明を省略する。
次に、本実施例におけるReRAM10の製造手順について、図18〜図28を参照しながら説明する。図18は、実施例2におけるReRAM10の製造手順の一例を示すフローチャートである。
なお、本発明は、上記した実施例に限定されるものではなく、その要旨の範囲内で数々の変形が可能である。
11 電極層
12 セレクタ層
13 中間導電層
14 抵抗変化層
15 絶縁層
16 電極層
17 メモリセル
Claims (1)
- 絶縁層と犠牲層とが交互に積層された多層膜に、前記多層膜の積層方向に第1の開口を形成するステップと、
前記第1の開口の内側壁に沿って、第1の層を積層するステップと、
前記第1の開口内に導電性を有する第1の材料を充填するステップと、
前記多層膜において、前記第1の開口が形成された位置とは異なる位置に、前記多層膜の積層方向に第2の開口を形成するステップと、
前記犠牲層を除去するステップと、
前記犠牲層が配置されていた前記絶縁層の間に導電性を有する第2の材料を充填するステップと、
前記第2の開口の位置において、それぞれの前記絶縁層が露出するように前記第2の材料をエッチングすることにより再び前記第2の開口を形成するステップと、
前記第2の開口の内側壁において、前記多層膜の面方向に前記第2の材料をエッチングするステップと、
前記絶縁層の間に第2の層を形成するための第3の材料を充填するステップと、
それぞれの前記絶縁層が露出するように、前記第2の開口内に充填された前記第3の材料をエッチングすることにより再び前記第2の開口を形成するステップと、
前記第2の開口の内側壁において、前記多層膜の面方向に前記第3の材料をエッチングすることにより前記第2の層を形成するステップと、
前記第2の開口内に導電性を有する第4の材料を充填するステップと、
前記第2の開口の位置において、それぞれの前記絶縁層が露出するように前記第4の材料をエッチングすることにより再び前記第2の開口を形成するステップと、
前記第2の開口内に絶縁材料を充填するステップと
を含み、
前記第1の層は、印加された電圧に応じて変化する抵抗値をデータとして保持するメモリ層、および、前記メモリ層の選択および非選択を制御するセレクタ層のいずれか一方であり、
前記第2の層は、前記メモリ層および前記セレクタ層のいずれか他方であることを特徴とする不揮発性記憶装置の製造方法。
Priority Applications (3)
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JP2016156135A JP6775349B2 (ja) | 2016-08-09 | 2016-08-09 | 不揮発性記憶装置の製造方法 |
KR1020170098676A KR102367026B1 (ko) | 2016-08-09 | 2017-08-03 | 불휘발성 기억 장치 및 불휘발성 기억 장치의 제조 방법 |
US15/670,368 US20180047787A1 (en) | 2016-08-09 | 2017-08-07 | Nonvolatile Storage Device and Method of Fabricating Nonvolatile Storage Device |
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JP2016156135A JP6775349B2 (ja) | 2016-08-09 | 2016-08-09 | 不揮発性記憶装置の製造方法 |
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JP2018026418A JP2018026418A (ja) | 2018-02-15 |
JP6775349B2 true JP6775349B2 (ja) | 2020-10-28 |
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US (1) | US20180047787A1 (ja) |
JP (1) | JP6775349B2 (ja) |
KR (1) | KR102367026B1 (ja) |
Families Citing this family (9)
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WO2019218106A1 (zh) * | 2018-05-14 | 2019-11-21 | 中国科学院微电子研究所 | 1s1r存储器集成结构及其制备方法 |
KR102546686B1 (ko) | 2018-07-17 | 2023-06-23 | 삼성전자주식회사 | 가변 저항 메모리 장치 |
KR102578801B1 (ko) | 2018-08-29 | 2023-09-18 | 삼성전자주식회사 | 가변 저항 메모리 장치 |
JP2020047850A (ja) | 2018-09-20 | 2020-03-26 | キオクシア株式会社 | 半導体記憶装置 |
US11335730B2 (en) | 2019-12-03 | 2022-05-17 | International Business Machines Corporation | Vertical resistive memory device with embedded selectors |
US11201193B2 (en) * | 2020-01-24 | 2021-12-14 | Qualcomm Incorporated | Vertically stacked multilayer high-density RRAM |
WO2022032550A1 (en) * | 2020-08-13 | 2022-02-17 | Yangtze Advanced Memory Industrial Innovation Center Co., Ltd | Novel integration scheme to form vertical 3d x-point memory with lower cost |
FR3131438A1 (fr) * | 2021-12-23 | 2023-06-30 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Ensemble comprenant au moins deux sélecteurs et deux mémoires résistives non-volatiles, matrice et procédé de fabrication associés |
FR3131437A1 (fr) * | 2021-12-23 | 2023-06-30 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Ensemble comprenant au moins deux mémoires résistives non-volatiles et deux sélecteurs, matrice et procédé de fabrication associés |
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US8409915B2 (en) * | 2010-09-20 | 2013-04-02 | Micron Technology, Inc. | Methods of forming memory cells |
JP5919010B2 (ja) * | 2012-02-06 | 2016-05-18 | 株式会社日立製作所 | 半導体記憶装置およびその製造方法 |
US20150162383A1 (en) * | 2012-06-28 | 2015-06-11 | Intellectual Discovery Co., Ltd. | Vertical resistive random access memory device, and method for manufacturing same |
JP5996324B2 (ja) * | 2012-08-07 | 2016-09-21 | シャープ株式会社 | 不揮発性半導体記憶装置とその製造方法 |
KR20140068627A (ko) * | 2012-11-28 | 2014-06-09 | 삼성전자주식회사 | 가변저항막을 갖는 저항 메모리 소자 및 그 제조방법 |
US9768234B2 (en) * | 2014-05-20 | 2017-09-19 | Crossbar, Inc. | Resistive memory architecture and devices |
US9583539B2 (en) * | 2014-08-19 | 2017-02-28 | Sandisk Technologies Llc | Word line connection for memory device and method of making thereof |
US20170025022A1 (en) * | 2015-03-23 | 2017-01-26 | AerWaze | Process to Enable Prioritization of Air Space in an Environment with Unmanned Aerial Vehicles |
US10290680B2 (en) * | 2015-10-30 | 2019-05-14 | Sandisk Technologies Llc | ReRAM MIM structure formation |
US9741764B1 (en) * | 2016-02-22 | 2017-08-22 | Samsung Electronics Co., Ltd. | Memory device including ovonic threshold switch adjusting threshold voltage thereof |
US9825098B2 (en) * | 2016-03-04 | 2017-11-21 | Toshiba Memory Corporation | Semiconductor memory device |
-
2016
- 2016-08-09 JP JP2016156135A patent/JP6775349B2/ja active Active
-
2017
- 2017-08-03 KR KR1020170098676A patent/KR102367026B1/ko active IP Right Grant
- 2017-08-07 US US15/670,368 patent/US20180047787A1/en not_active Abandoned
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JP2018026418A (ja) | 2018-02-15 |
KR102367026B1 (ko) | 2022-02-24 |
KR20180018349A (ko) | 2018-02-21 |
US20180047787A1 (en) | 2018-02-15 |
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