WO2019218106A1 - 1s1r存储器集成结构及其制备方法 - Google Patents

1s1r存储器集成结构及其制备方法 Download PDF

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WO2019218106A1
WO2019218106A1 PCT/CN2018/086668 CN2018086668W WO2019218106A1 WO 2019218106 A1 WO2019218106 A1 WO 2019218106A1 CN 2018086668 W CN2018086668 W CN 2018086668W WO 2019218106 A1 WO2019218106 A1 WO 2019218106A1
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material layer
integrated structure
memory
layer
tube
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PCT/CN2018/086668
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English (en)
French (fr)
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罗庆
吕杭炳
刘明
许晓欣
路程
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中国科学院微电子研究所
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Priority to PCT/CN2018/086668 priority Critical patent/WO2019218106A1/zh
Publication of WO2019218106A1 publication Critical patent/WO2019218106A1/zh
Priority to US16/786,346 priority patent/US11205750B2/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx

Definitions

  • the present disclosure belongs to the field of microelectronics manufacturing and memory technology, and in particular, to a 1S1R memory integrated structure and a method for fabricating the same.
  • Memory plays an important role in the semiconductor market and can be generally classified into volatile memory and non-volatile memory. Volatile memory means that the information of the memory must be maintained at the time of power-on, and the information stored will be lost when the power is not applied. The main feature of the non-volatile memory is that it can be stored for a long time without power. Information. With the increasing popularity of portable electronic devices, non-volatile memory is becoming more and more important in embedded applications. Due to the explosive expansion of emerging markets such as the Internet of Things, artificial intelligence, smart cars and virtual reality, storing and computing big data in electronic terminals requires high-density embedded memory. Devices such as resistive memory or phase change memory are considered to be the most promising memory for future embedded applications because of their simple structure, easy integration, and low power consumption.
  • the resistive memory and the phase change memory are both a metal/dielectric layer/metal (MIM) capacitor structure, and the device acts in a high resistance state (HRS) and a low resistance state (Low Resistance State) by an electrical signal. Reversible conversion between LRS) to implement storage functions. Due to its simple structure, it is very advantageous to realize a high-density cross-array structure.
  • the cross-array of a single R structure has a read-through crosstalk problem due to the presence of a low-impedance current leakage path. To solve this problem, a strobe must be connected in series with R, such as a transistor (1T1R structure) or a diode (1D1R structure).
  • the 1T1R structure cannot be used for three-dimensional integration because the transistor needs to occupy the area of the substrate silicon.
  • the gate (1S) and the two-terminal memory (1R) have the same device area (as shown in Figure 1), which imposes very high requirements on the on-state current density of the gate.
  • the on-state current density of the gate is required to be greater than 1 MA/cm 2 or even 10 MA/cm 2 .
  • Most of the strobes are difficult to meet the requirements of their high on-state current density, which has become a major problem limiting the large-scale integration of memory at both ends.
  • the present disclosure provides a 1S1R memory integrated structure and a method of fabricating the same to at least partially solve the above-mentioned technical problems.
  • a 1S1R memory integrated structure including: a word line metal, a resistive material layer, a strobe tube lower electrode, a strobe tube material layer, a strobe tube upper electrode, a interconnect line, and a bit line. a metal; wherein the gate material layer is in the shape of a groove, and the upper electrode of the gate is formed in the groove.
  • the word line metal is the memory lower electrode
  • the gate lower electrode is simultaneously the memory upper electrode and the interconnect line.
  • the layer of resistive material is on the word line metal or on the upper electrode of the gating tube.
  • the area of the gate material layer is greater than the area of the resistive material layer.
  • the word lines, bit lines, interconnect lines, resistive material layers, and gate material layers are formed by electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, or sputtering processes;
  • the material of the word line, the bit line and the interconnect line is W or Cu;
  • the thickness of the resistive material layer is between 5 nm and 60 nm, and the material comprises one or a combination of ZrO 2 , HfO 2 , TiO 2 , SiO 2 , Ta 2 O 5 and Y 2 O 3 ;
  • the thickness of the material layer of the strobe tube is between 5 nm and 60 nm, and the material is a metal oxide or an ion-electron mixed conductive (MIEC) material; the metal oxide includes ZrO 2 , HfO 2 , TiO 2 , SiO 2 , One or a combination of Ta 2 O 5 , Y 2 O 3 , NbO x and VO 2 .
  • MIEC ion-electron mixed conductive
  • a method for fabricating a 1S1R memory integrated structure including:
  • An interconnection line and a bit line metal are sequentially formed on the upper electrode of the strobe tube.
  • a method for fabricating a 1S1R memory integrated structure including:
  • a resistive material layer, an interconnection line, and a bit line metal are sequentially formed on the upper electrode of the strobe tube.
  • the word line metal is the memory lower electrode, and the gate lower electrode is simultaneously the memory upper electrode and the interconnection line; the area of the gate material layer formed is larger than the The area of the resistive material layer.
  • the insulating layer in the step of etching the insulating layer, is etched to an upper surface of the interconnecting line, and a bottom surface of the recessed structure formed thereby is flush with a surface of the interconnecting line .
  • the word lines, bit lines, interconnect lines, resistive material layers, and gate material layers are formed by electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, or sputtering processes;
  • the word line, the bit line, and the interconnect line are made of W or Cu;
  • the thickness of the resistive material layer is between 5 nm and 60 nm, and the material comprises one or a combination of ZrO 2 , HfO 2 , TiO 2 , SiO 2 , Ta 2 O 5 and Y 2 O 3 ;
  • the thickness of the material layer of the strobe tube is between 5 nm and 60 nm, and the material is a metal oxide or an ion-electron mixed conductive (MIEC) material; the metal oxide includes ZrO 2 , HfO 2 , TiO 2 , SiO 2 , One or a combination of Ta 2 O 5 , Y 2 O 3 , NbO x and VO 2 ;
  • MIEC ion-electron mixed conductive
  • the material of the insulating layer is SiO 2 .
  • the 1S1R memory integrated structure and the preparation method of the present disclosure by changing the integration position of the strobe tube, the device area of the strobe tube is much larger than the device area of the memory, and the requirement for the on-state current density of the strobe tube is remarkably reduced.
  • the 1S1R memory integrated structure and the manufacturing method of the present disclosure can effectively suppress leakage current in the cross array without increasing the overall size of the integrated structure.
  • the 1S1R memory integrated structure and the preparation method of the present disclosure effectively increase the device area of the strobe tube compared to the conventional 1S1R integrated structure, so that the strobe tube can provide a larger current.
  • FIG. 1 is a schematic diagram of an integrated structure of a conventional 1S1R memory.
  • FIG. 2 is a schematic diagram of an integrated structure of a 1S1R memory according to an embodiment of the present disclosure.
  • 3-7 are schematic diagrams showing a preparation process of a 1S1R memory integrated structure according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of an integrated structure of a 1S1R memory according to still another embodiment of the present disclosure.
  • 101-interconnect line (gate on upper electrode), M0-gate lower electrode; 201-gate material layer, 301-interconnect line, 401-resistive material layer; 102-interconnect line, 202-gate Material layer, 302-interconnect line (gate lower electrode, memory upper electrode), 402-resistive material layer, 502-insulation layer, 602-deep trench, M1-word line metal (memory lower electrode), M2-select The upper electrode, the M3-bit line metal, the 103-interconnect line, the 203-gate material layer, the 303-interconnect line (the strobe lower electrode, the memory upper electrode), and the 403-resistive material layer.
  • the present disclosure provides a 1S1R memory integrated structure, including: a word line metal, a resistive material layer, a strobe tube lower electrode, a strobe tube material layer, a strobe tube upper electrode, an interconnection line, and a bit line metal;
  • the layer of the through-tube material is in the shape of a groove, and the upper electrode of the gate is formed in the groove.
  • the present disclosure also provides a method for preparing a 1S1R memory integrated structure, including:
  • An interconnection line and a bit line metal are sequentially formed on the upper electrode of the strobe tube.
  • the present disclosure also provides a method for preparing another 1S1R memory integrated structure, including:
  • a resistive material layer, an interconnection line, and a bit line metal are sequentially formed on the upper electrode of the strobe tube.
  • the word line, the bit line, the interconnect line, the resistive material layer and the strobing tube material layer may be formed by electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition or sputtering.
  • the word line metal is the memory lower electrode
  • the gate lower electrode is simultaneously the memory upper electrode and the interconnection line.
  • the layer of resistive material may be located on the word line metal or on the upper electrode of the gating tube.
  • the area of the gate material layer is larger than the area of the resistive material layer.
  • the 1S1R memory integrated structure includes, in order from bottom to top, a memory word line metal M1 (which is a memory lower electrode), a resistive material layer 402, and a gate lower electrode 302 ( At the same time, as the resistive memory upper electrode and interconnection line), the gate material layer 202, the gate upper electrode M2, the interconnection line 102 and the bit line metal M3.
  • a memory word line metal M1 which is a memory lower electrode
  • a resistive material layer 402 which is a memory lower electrode
  • a gate lower electrode 302 At the same time, as the resistive memory upper electrode and interconnection line), the gate material layer 202, the gate upper electrode M2, the interconnection line 102 and the bit line metal M3.
  • the gate material layer 202 has a groove shape, and the gate upper electrode M2 is filled in the groove of the gate material layer 202, and the gate tube is The top surface of the electrode M2 is flush with the top surfaces of both sides of the groove of the gate material layer 202.
  • the bottom surface of the strobe tube material layer has a larger dimension than the bottom surface of each of the metal electrodes and the interconnecting wires.
  • the metal electrodes M1, M2, the bit line metal M3, and the interconnection lines 302 and 102 may be made of a metal element such as W, Cu, etc., by electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer. Prepared by deposition or sputtering methods.
  • the resistive material layer 402 is formed on the lower electrode M1 and can be prepared by electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition or sputtering.
  • the material of the resistive material layer comprises one or a combination of completely proportioned metal oxides such as ZrO 2 , HfO 2 , TiO 2 , SiO 2 , Ta 2 O 5 , Y 2 O 3 , etc., and the thickness is between 5 nm. Between -60 nm, preferably, the thickness is 36 nm.
  • the strobe tube material layer 202 is formed on the strobe tube lower electrode 302 and is made of metal oxide or ion-electron mixed conductive (MIEC) material.
  • the gate material layer 202 may be one of metal oxides such as ZrO 2 , HfO 2 , TiO 2 , SiO 2 , Ta 2 O 5 , Y 2 O 3 , NbO x , VO 2 or The combination is formed, and may also be formed of other compound materials such as ion-electron mixed conductive (MIEC) materials.
  • the layer of the material of the strobe tube can be prepared by electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition or sputtering, and has a thickness of between 5 nm and 60 nm, preferably a thickness of 38 nm.
  • the outer side wall of the metal M3 is covered with an insulating layer 602, and the material of the insulating layer may be SiO 2 .
  • the insulating layer can also be prepared by electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition or sputtering.
  • the method for preparing the 1S1R memory integrated structure includes:
  • Step 1 Form the lower electrode M1, the resistive material layer 402, and the interconnect line 302 using a standard CMOS process, as shown in FIG.
  • the lower electrode M1, the resistive material layer 402 and the interconnecting line 302 can be prepared by one of electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, and sputtering.
  • the material of the resistive material layer 402 may be one of a completely proportioned metal oxide such as ZrO 2 , HfO 2 , TiO 2 , SiO 2 , Ta 2 O 5 , Y 2 O 3 , etc., and the material thickness is 5 nm to 60nm.
  • Step 2 An insulating layer 502 is grown on the interconnect 302, as shown in FIG.
  • the material of the insulating layer may be SiO 2 .
  • the insulating layer 502 is grown by one of electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, and sputtering.
  • Step 3 Etching the insulating layer to form a deep trench 602 on the insulating layer, as shown in FIG.
  • the insulating layer is etched to an upper surface of the interconnecting line, and a bottom surface of the deep trench 602 thus formed is flush with a surface of the interconnecting line.
  • Step 4 The gate material layer 202 is prepared by one of electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, and sputtering. The structure shown in Fig. 6 is then obtained by a smoothing process.
  • the gate material layer may be formed of one of metal oxides such as ZrO 2 , HfO 2 , TiO 2 , SiO 2 , Ta 2 O 5 , Y 2 O 3 , NbO x , VO 2 , etc. It can be formed from other compounds such as ion-electron mixed conductive (MIEC) materials.
  • metal oxides such as ZrO 2 , HfO 2 , TiO 2 , SiO 2 , Ta 2 O 5 , Y 2 O 3 , NbO x , VO 2 , etc. It can be formed from other compounds such as ion-electron mixed conductive (MIEC) materials.
  • MIEC ion-electron mixed conductive
  • Step 5 The upper electrode M2 is grown on the gate material layer 202, and then the structure shown in Fig. 7 is obtained by a smoothing process.
  • Step 6 The interconnect line 102 and the bit line metal M3 are implemented by standard CMOS process means, and the 1S1R memory integrated structure is obtained, as shown in FIG. 2 .
  • the metal electrodes M1, M2, the bit line metal M3, and the interconnection lines 303 and 103 may be made of a metal element such as W, Cu, etc., by electron beam evaporation, chemical vapor deposition, pulsed laser deposition. Prepared by atomic layer deposition or sputtering.
  • the 1S1R memory integrated structure includes, in order from bottom to top, a memory word line metal and a lower electrode M1, and a lower electrode 303 (also serves as a memory upper electrode and an interconnection line). ), the gate material layer 203, the gate upper electrode M2, the resistive material layer 403, the interconnect line 103, and the bit line metal M3.
  • the resistive material layer is formed on the upper electrode of the strobe tube in the present embodiment, and the resistive material layer is formed on the word line metal in the previous embodiment.
  • the other components of the 1S1R memory integrated structure of the present embodiment are the same as those of the foregoing embodiment, and the corresponding preparation methods are similar to the foregoing preparation methods, and are not described herein again.

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Abstract

本公开提出了一种1S1R存储器集成结构及其制备方法；其中，所述1S1R存储器集成结构，包括：字线金属、阻变材料层、选通管下电极、选通管材料层、选通管上电极、互联线及位线金属；其中，所述选通管材料层呈凹槽形，所述选通管上电极形成于所述凹槽内。本公开1S1R存储器集成结构及制备方法，通过选通管集成位置的改变，使得选通管的器件面积远大于存储器的器件面积，显著降低了对选通管开态电流密度的要求。

Description

1S1R存储器集成结构及其制备方法 技术领域
本公开属于微电子制造及存储器技术领域，具体涉及一种1S1R存储器集成结构及其制备方法。
背景技术
存储器在半导体市场中占有重要的地位，一般可以分为挥发性存储器和非挥发性存储器。挥发性存储器是指存储器的信息必须在加电的时候才能保持，在不加电时存储的信息就会丢失；而不挥发性存储器的主要特点是在不加电的情况下也能够长期保持存储的信息。随着便携式电子设备的不断普及，非挥发性存储器在嵌入式应用中变得越来越重要。由于物联网、人工智能、智能车和虚拟现实等新兴市场的爆炸性膨胀，电子终端中存储和计算大数据需要高密度嵌入式存储器。阻变存储器或者相变存储器等两端器件因为其结构简单，易于集成，低功耗等特征，被认为是最有希望成为未来嵌入式应用的存储器。
阻变存储器和相变存储器同为一金属/介质层/金属(MIM)电容结构，通过电信号的作用，使器件在高电阻状态(High Resistance State，HRS)和低电阻状态(Low Resistance State，LRS)之间可逆转换，实现存储功能。由于其结构简单，非常利于实现高密度的交叉阵列结构。单R结构的交叉阵列由于存在低阻态的电流泄漏路径，有读串扰问题，解决此问题方法是必须在R上面串联一个选通管，如晶体管(1T1R结构)或二极管(1D1R结构)。1T1R结构，由于晶体管需要占用衬底硅的面积，不能用于三维集成。而在传统的1S1R架构中，选通管(1S)和两端存储器(1R)的器件面积同样大(如图1所示)，对选通管的开态电流密度提出了非常高的要求，尤其是针对相变存储器的高操作电流，要求选通管的开态电流密度要大于1MA/cm2甚至10MA/cm2。大部分选通管难以满足其高开态电流密度的要求，成为限制两端存储器大规模集成的主要问题。
发明内容
(一)要解决的技术问题
本公开提供了一种1S1R存储器集成结构及其制备方法，以至少部分解决以上所提出的技术问题。
(二)技术方案
根据本公开的一个方面，提供了一种1S1R存储器集成结构，包括：字线金属、阻变材料层、选通管下电极、选通管材料层、选通管上电极、互联线及位线金属；其中，所述选通管材料层呈凹槽形，所述选通管上电极形成于所述凹槽内。
在一些实施例中，所述字线金属为所述存储器下电极，所述选通管下电极同时为所述存储器上电极及互联线。
在一些实施例中，所述阻变材料层位于所述字线金属上或位于所述选通管上电极上。
在一些实施例中，所述选通管材料层的面积大于所述阻变材料层的面积。
在一些实施例中，所述字线、位线、互联线、阻变材料层及选通管材料层采用电子束蒸发、化学气相沉积、脉冲激光沉积、原子层沉积或溅射工艺形成；
所述字线、位线及互联线的材质为W或Cu；
所述阻变材料层的厚度介于5nm～60nm之间，材质包括ZrO 2、HfO 2、TiO 2、SiO 2、Ta 2O 5和Y 2O 3的其中一种或其组合；
所述选通管材料层的厚度介于5nm～60nm之间，材质为金属氧化物或离子电子混合导电(MIEC)材料；所述金属氧化物包括ZrO 2、HfO 2、TiO 2、SiO 2、Ta 2O 5、Y 2O 3、NbO x及VO 2的其中一种或其组合。
根据本公开的另一个方面，提供了一种1S1R存储器集成结构的制备方法，包括：
自下而上依次形成字线金属、阻变材料层及选通管下电极；
在所述选通管下电极上形成绝缘层，刻蚀该绝缘层，形成凹槽结构；
在所述凹槽结构内形成凹槽形的选通管材料层；
在所述选通管材料层的凹槽内形成选通管上电极；
在选通管上电极上依次形成互联线及位线金属。
根据本公开的再一个方面，提供了一种1S1R存储器集成结构的制备方法，包括：
自下而上依次形成字线金属及选通管下电极；
在所述选通管下电极上形成绝缘层，刻蚀该绝缘层，形成凹槽结构；
在所述凹槽结构内形成凹槽形的选通管材料层；
在所述选通管材料层的凹槽内形成选通管上电极；
在选通管上电极上依次形成阻变材料层、互联线及位线金属。
在一些实施例中，所述字线金属为所述存储器下电极，所述选通管下电极同时为所述存储器上电极及互联线；形成的所述选通管材料层的面积大于所述阻变材料层的面积。
在一些实施例中，在刻蚀该绝缘层的步骤中，刻蚀该绝缘层至所述互联线的上表面，由此形成的所述凹槽结构的底面与所述互联线上表面齐平。
在一些实施例中，采用电子束蒸发、化学气相沉积、脉冲激光沉积、原子层沉积或溅射工艺形成所述字线、位线、互联线、阻变材料层及选通管材料层；
所述字线、位线、互联线材质为W或Cu；
所述阻变材料层的厚度介于5nm～60nm之间，材质包括ZrO 2、HfO 2、TiO 2、SiO 2、Ta 2O 5和Y 2O 3的其中一种或其组合；
所述选通管材料层的厚度介于5nm～60nm之间，材质为金属氧化物或离子电子混合导电(MIEC)材料；所述金属氧化物包括ZrO 2、HfO 2、TiO 2、SiO 2、Ta 2O 5、Y 2O 3、NbO x及VO 2的其中一种或其组合；
所述绝缘层的材质为SiO 2。
(三)有益效果
从上述技术方案可以看出，本公开1S1R存储器集成结构及其制备方法至少具有以下有益效果其中之一：
(1)本公开1S1R存储器集成结构及制备方法，通过选通管集成位置的改变，使得选通管的器件面积远大于存储器的器件面积，显著降低了对选通管开态电流密度的要求。
(2)本公开1S1R存储器集成结构及制备方法可以有效的抑制交叉阵列中的漏电流，且不增加集成结构的整体尺寸。
(3)本公开1S1R存储器集成结构及制备方法，相比于传统1S1R集成结构，有效的增加了选通管的器件面积，使得选通管可以提供更大的电流。
附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1为现有1S1R存储器集成结构示意图。
图2为依据本公开一实施例1S1R存储器集成结构示意图。
图3-7为依据本公开实施例1S1R存储器集成结构制备过程示意图。
图8为依据本公开又一实施例1S1R存储器集成结构示意图。
<符号说明>
101-互联线(选通管上电极)、M0-选通管下电极；201-选通管材料层、301-互联线、401-阻变材料层；102-互联线、202-选通管材料层、302-互联线(选通管下电极、存储器上电极)、402-阻变材料层、502-绝缘层、602-深槽、M1-字线金属(存储器下电极)、M2-选通管上电极、M3-位线金属；103-互联线、203-选通管材料层、303-互联线(选通管下电极、存储器上电极)、403-阻变材料层。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本公开进一步详细说明。
本公开提供了一种1S1R存储器集成结构，包括：字线金属、阻变材料层、选通管下电极、选通管材料层、选通管上电极、互联线及位线金属；其中，所述选通管材料层呈凹槽形，所述选通管上电极形成于所述凹槽内。
另外，本公开还提供了一种1S1R存储器集成结构的制备方法，包括：
自下而上依次形成字线金属、阻变材料层及选通管下电极；
在所述选通管下电极上形成绝缘层，刻蚀该绝缘层，形成凹槽结构；
在所述凹槽结构内形成凹槽形的选通管材料层；
在所述选通管材料层的凹槽内形成选通管上电极；以及
在选通管上电极上依次形成互联线及位线金属。
此外，本公开还提供了另一种1S1R存储器集成结构的制备方法，包括：
自下而上依次形成字线金属及选通管下电极；
在所述选通管下电极上形成绝缘层，刻蚀该绝缘层，形成凹槽结构；
在所述凹槽结构内形成凹槽形的选通管材料层；
在所述选通管材料层的凹槽内形成选通管上电极；以及
在选通管上电极上依次形成阻变材料层、互联线及位线金属。
具体的，所述字线、位线、互联线、阻变材料层及选通管材料层可采用电子束蒸发、化学气相沉积、脉冲激光沉积、原子层沉积或溅射工艺形成。
在所述1S1R存储器集成结构中，所述字线金属为所述存储器下电极，所述选通管下电极同时为所述存储器上电极及互联线。所述阻变材料层可位于所述字线金属上，也可位于所述选通管上电极上。所述选通管材料层的面积大于所述阻变材料层的面积。
在一实施例中，如图2所示，所述1S1R存储器集成结构自下而上依次包括：存储器字线金属M1(为存储器下电极)、阻变材料层402、选通管下电极302(同时作为阻变存储器上电极及互联线)、选通管材料层202、选通管上电极M2、互联线102以及位线金属M3。
其中，如图2所示，所述选通管材料层202呈凹槽形，所述选通管上电极M2填充在所述选通管材料层202的凹槽内，所述选通管上电极M2的顶面与所述选通管材料层202的凹槽的两侧顶面齐平。
所述选通管材料层的底面尺寸大于所述各金属电极、互联线的底面尺寸。通过选通管集成位置的改变，使得选通管的器件面积远大于存储器的器件面积，显著降低了对选通管开态电流密度的要求。
具体的，所述金属电极M1、M2、位线金属M3以及互联线302和102的材质可以为金属单质，例如W、Cu等，可通过电子束蒸发，化学气相沉积、脉冲激光沉积、原子层沉积或溅射方法制备而成。
所述阻变材料层402形成于所述下电极M1之上，可通过电子束蒸发， 化学气相沉积、脉冲激光沉积、原子层沉积或溅射方法制备而成。所述阻变材料层的材质包括ZrO 2、HfO 2、TiO 2、SiO 2、Ta 2O 5、Y 2O 3等完全配比的金属氧化物中的一种或其组合，厚度介于5nm～60nm之间，优选的，厚度为36nm。
所述选通管材料层202形成于所述选通管下电极302之上，其材质为金属氧化物或离子电子混合导电(MIEC)的材料。具体的，所述选通管材料层202可以由ZrO 2、HfO 2、TiO 2、SiO 2、Ta 2O 5、Y 2O 3、NbO x、VO 2等金属氧化物中的一种或其组合形成，也可以由其他化合材料如离子电子混合导电(MIEC)的材料形成。所述选通管材料层可通过电子束蒸发，化学气相沉积、脉冲激光沉积、原子层沉积或溅射方法制备而成，厚度介于5nm～60nm之间，优选的，厚度为38nm。
请继续参照图2所示，在所述字线金属M1、阻变材料层402，选通管下电极302、选通管材料层202、选通管上电极M2、互联线102、以及位线金属M3的外侧壁上覆盖有绝缘层602，绝缘层的材质可以为SiO 2。所述绝缘层也可通过电子束蒸发，化学气相沉积、脉冲激光沉积、原子层沉积或溅射方法制备而成。
在另一实施例中，如图2-7所示，所述1S1R存储器集成结构的制备方法包括：
步骤1：采用标准CMOS工艺形成下电极M1、阻变材料层402及互联线302，如图3所示。
具体的，所述下电极M1、阻变材料层402及互联线302可通过电子束蒸发，化学气相沉积、脉冲激光沉积、原子层沉积、溅射方法中的一种方法制备而成。所述阻变材料层402的材质可以为ZrO 2、HfO 2、TiO 2、SiO 2、Ta 2O 5、Y 2O 3等完全配比的金属氧化物中的一种，材料厚度为5nm至60nm。
步骤2：在互联线302上生长绝缘层502，如图4所示。
所述绝缘层的材质可以为SiO 2。通过电子束蒸发，化学气相沉积、脉冲激光沉积、原子层沉积、溅射方法中的一种生长绝缘层502。
步骤3：刻蚀所述绝缘层，在所述绝缘层上形成一深槽602，如图5所示。
具体的，在刻蚀所述绝缘层的步骤中，刻蚀所述绝缘层至所述互联线的上表面，由此形成的所述深槽602的底面与所述互联线上表面齐平。
步骤4：通过电子束蒸发，化学气相沉积、脉冲激光沉积、原子层沉积、溅射方法中的一种制备选通管材料层202。然后通过磨平工艺得到如图6所示结构。
具体的，所述选通管材料层可以由ZrO 2、HfO 2、TiO 2、SiO 2、Ta 2O 5、Y 2O 3、NbO x、VO 2等金属氧化物中的一种形成，也可以由其他化合材料如离子电子混合导电(MIEC)的材料形成。
步骤5：在选通管材料层202上生长上电极M2，然后通过磨平工艺得到如图7所示结构。
步骤6：通过标准CMOS工艺手段实现互联线102及位线金属M3，得到所述1S1R存储器集成结构，如图2所示。
本实施例方法中，所述金属电极M1、M2、位线金属M3以及互联线303和103的材质可以为金属单质，例如W、Cu等，可通过电子束蒸发，化学气相沉积、脉冲激光沉积、原子层沉积或溅射方法制备而成。
在又一实施例中，如图8所示，所述1S1R存储器集成结构自下而上依次包括：存储器字线金属与下电极M1、选通管下电极303(同时作为存储器上电极及互联线)、选通管材料层203，选通管上电极M2，阻变材料层403、互联线103、位线金属M3。
与前一实施例1S1R存储器集成结构不同的是，本实施中阻变材料层形成于所述选通管上电极之上，前一实施例中阻变材料层形成于所述字线金属之上。关于本实施例1S1R存储器集成结构的其他组成与前述实施例相同，其相应的制备方法也与前述制备方法类似，此处不再赘述。
至此，已经结合附图对本公开实施例进行了详细描述。依据以上描述，本领域技术人员应当对本公开1S1R存储器集成结构及其制备方法有了清楚的认识。
需要说明的是，在附图或说明书正文中，未绘示或描述的实现方式，均为所属技术领域中普通技术人员所知的形式，并未进行详细说明。此外，上述对各元件的定义并不仅限于实施例中提到的各种具体结构、形状，本领域普通技术人员可对其进行简单地更改或替换；本文可提供包含特定值 的参数的示范，但这些参数无需确切等于相应的值，而是可在可接受的误差容限或设计约束内近似于相应值；实施例中提到的方向用语，例如“上”、“下”、“前”、“后”、“左”、“右”等，仅是参考附图的方向，并非用来限制本公开的保护范围；上述实施例可基于设计及可靠度的考虑，彼此混合搭配使用或与其他实施例混合搭配使用，即不同实施例中的技术特征可以自由组合形成更多的实施例。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本申请。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本申请的精神或范围的情况下，在其它实施例中实现。因此，本公开将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。
需要说明的是，在附图或说明书正文中，未绘示或描述的实现方式，均为所属技术领域中普通技术人员所知的形式，并未进行详细说明。此外，上述对各元件和方法的定义并不仅限于实施例中提到的各种具体结构、形状或方式，本领域普通技术人员可对其进行简单地更改或替换。
以上所述的具体实施例，对本公开的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本公开的具体实施例而已，并不用于限制本公开，凡在本公开的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (10)

  1. 一种1S1R存储器集成结构，包括：字线金属、阻变材料层、选通管下电极、选通管材料层、选通管上电极、互联线及位线金属；其中，所述选通管材料层呈凹槽形，所述选通管上电极形成于所述凹槽内。
  2. 根据权利要求1所述的1S1R存储器集成结构，其中，所述字线金属为所述存储器下电极，所述选通管下电极同时为所述存储器上电极及互联线。
  3. 根据权利要求1所述的1S1R存储器集成结构，其中，所述阻变材料层位于所述字线金属上或位于所述选通管上电极上。
  4. 根据权利要求1所述的1S1R存储器集成结构，其中，所述选通管材料层的面积大于所述阻变材料层的面积。
  5. 根据权利要求1所述的1S1R存储器集成结构，其中，
    所述字线、位线、互联线、阻变材料层及选通管材料层采用电子束蒸发、化学气相沉积、脉冲激光沉积、原子层沉积或溅射工艺形成；
    所述字线、位线及互联线的材质为W或Cu；
    所述阻变材料层的厚度介于5nm～60nm之间，材质包括ZrO 2、HfO 2、TiO 2、SiO 2、Ta 2O 5和Y 2O 3的其中一种或其组合；
    所述选通管材料层的厚度介于5nm～60nm之间，材质为金属氧化物或离子电子混合导电(MIEC)材料；所述金属氧化物包括ZrO 2、HfO 2、TiO 2、SiO 2、Ta 2O 5、Y 2O 3、NbO x及VO 2的其中一种或其组合。
  6. 一种1S1R存储器集成结构的制备方法，包括：
    自下而上依次形成字线金属、阻变材料层及选通管下电极；
    在所述选通管下电极上形成绝缘层，刻蚀该绝缘层，形成凹槽结构；
    在所述凹槽结构内形成凹槽形的选通管材料层；
    在所述选通管材料层的凹槽内形成选通管上电极；
    在选通管上电极上依次形成互联线及位线金属。
  7. 一种1S1R存储器集成结构的制备方法，包括：
    自下而上依次形成字线金属及选通管下电极；
    在所述选通管下电极上形成绝缘层，刻蚀该绝缘层，形成凹槽结构；
    在所述凹槽结构内形成凹槽形的选通管材料层；
    在所述选通管材料层的凹槽内形成选通管上电极；
    在选通管上电极上依次形成阻变材料层、互联线及位线金属。
  8. 根据权利要求6或7所述的1S1R存储器集成结构的制备方法，其中，所述字线金属为所述存储器下电极，所述选通管下电极同时为所述存储器上电极及互联线；形成的所述选通管材料层的面积大于所述阻变材料层的面积。
  9. 根据权利要求6或7所述的1S1R存储器集成结构的制备方法，其中，在刻蚀该绝缘层的步骤中，刻蚀该绝缘层至所述互联线的上表面，由此形成的所述凹槽结构的底面与所述互联线上表面齐平。
  10. 根据权利要求6或7所述的1S1R存储器集成结构的制备方法，其中，
    采用电子束蒸发、化学气相沉积、脉冲激光沉积、原子层沉积或溅射工艺形成所述字线、位线、互联线、阻变材料层及选通管材料层；
    所述字线、位线、互联线材质为W或Cu；
    所述阻变材料层的厚度介于5nm～60nm之间，材质包括ZrO 2、HfO 2、TiO 2、SiO 2、Ta 2O 5和Y 2O 3的其中一种或其组合；
    所述选通管材料层的厚度介于5nm～60nm之间，材质为金属氧化物或离子电子混合导电(MIEC)材料；所述金属氧化物包括ZrO 2、HfO 2、TiO 2、SiO 2、Ta 2O 5、Y 2O 3、NbO x及VO 2的其中一种或其组合；
    所述绝缘层的材质为SiO 2。
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