WO2022032550A1

WO2022032550A1 - Novel integration scheme to form vertical 3d x-point memory with lower cost

Info

Publication number: WO2022032550A1
Application number: PCT/CN2020/108782
Authority: WO
Inventors: Jun Liu
Original assignee: Yangtze Advanced Memory Industrial Innovation Center Co., Ltd
Priority date: 2020-08-13
Filing date: 2020-08-13
Publication date: 2022-02-17
Also published as: CN112106201B; CN112106201A

Abstract

A three dimensional cross point memory stack includes a plurality of longitudinally extending vertical pillars including metal layers vertically alternating with dielectric layers, the metal layers providing word lines. The architecture also includes bit lines extending vertically along lateral sides of the pillars. A longitudinal direction is perpendicular to a vertical direction, and a lateral direction is perpendicular to the vertical direction and the longitudinal direction.

Description

[Title established by the ISA under Rule 37.2] NOVEL INTEGRATION SCHEME TO FORM VERTICAL 3D X-POINT MEMORY WITH LOWER COST

TECHNICAL FIELD

The present disclosure generally relates to three-dimensional electronic memories, and more particularly, to increasing the density of memory cells in three-dimensional cross point memories.

BACKGROUND OF THE INVENTION

Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As such, memory density for planar memory cells approaches an upper limit. A three-dimensional (3D) memory architecture can address the density limitation in planar memory cells by layering multiple planes of memory cells in a single device.

BRIEF SUMMARY OF THE INVENTION

In accordance with an aspect, a three dimensional cross point memory stack includes a plurality of longitudinally extending vertical pillars including metal layers vertically alternating with dielectric layers, the metal layers providing word lines. The architecture also includes bit lines extending vertically along lateral sides of the pillars. A longitudinal direction is perpendicular to a vertical direction, and a lateral direction is perpendicular to the vertical direction and the longitudinal direction.

In some arrangements, longitudinally adjacent and laterally aligned bit lines are separated in the longitudinal direction by blocks of dielectric material.

In some arrangements, the metal layers in each stack are laterally narrower than vertically adjacent oxide layers.

In some arrangements, memory cells are provided on lateral sides of the metal layers in each stack, and the memory cells extend to be flush with lateral sides of the pillars and to contact the bit lines.

In some arrangements, each memory cell includes a phase change material element and an ovonic threshold switch element.

In some arrangements, dielectric blocks extend into each lateral sides of the pillars and separate vertically and laterally aligned, longitudinally adjacent memory cells in the longitudinal direction.

In some arrangements, planar oxide dividers extend vertically and longitudinally across a laterally central plane of each pillar.

In accordance with another aspect, a method for producing a three dimensional cross point memory stack includes depositing alternating layers of oxide and nitride to form a vertical stack, wherein a vertical direction is perpendicular to a lateral direction and a longitudinal direction is perpendicular to the vertical direction and the lateral direction. The method also includes cutting parallel longitudinal gaps out of the vertical stack to provide multiple longitudinally extending vertical pillars and providing empty spaces between the oxide layers by removing the nitride layers. The method further includes disposing longitudinally extending word lines in the empty spaces between the oxide layers, wherein the word lines are laterally narrower than the oxide layers, disposing memory cells on lateral sides of the word lines, the memory cells extending to be flush with lateral sides of the pillars, and disposing vertically extending word lines within the gaps on the lateral sides of the pillars.

In some arrangements, the method includes cutting vertical slots through the memory stack, the slots being laterally wider than the gaps laterally aligned with the gaps, and filling the slots with dielectric blocks before cutting the gaps.

In some arrangements, the step of disposing the word lines includes filling the empty spaces between the oxide layers with metal, etching the metal such that any of the metal on the lateral sides of the pillars is removed, thereby creating discrete layers of the metal vertically alternating with the oxide layers in the pillars, and etching the discrete layers of the metal such that the discrete layers of the metal are recessed laterally inward from the lateral sides of the pillars.

In some arrangements, the step of disposing the memory cells includes depositing a phase change material on the stack such that the phase change material extends between the oxide layers, then etching away any phase change material on the lateral sides of the pillars, and depositing an ovonic threshold switch material on the stack such that the ovonic threshold switch material extends between the oxide layers, then etching away any ovonic threshold switch material on the lateral sides of the pillars.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects, features and advantages of the present disclosure will be further appreciated when considered with reference to the following description of exemplary embodiments and accompanying drawings, wherein like reference numerals represent like elements. In describing the exemplary embodiments of the present disclosure illustrated in the drawings, specific terminology may be used for the sake of clarity. However, the aspects of the present disclosure are not intended to be limited to the specific terms used.

FIG. 1 illustrates a unit of a memory architecture.

FIG. 2 illustrates a stack of oxide and nitride layers according to an exemplary embodiment.

FIG. 3A illustrates a single layer of the stack during a stage in a method according to the embodiment wherein slots exist in the stack.

FIG. 3B is a cross-sectional view of the stack along the section line in FIG. 3A.

FIG. 4A illustrates a single layer of the stack during a stage in the method wherein dielectric blocks fill the slots.

FIG. 4B is a cross-sectional view of the stack along the section line in FIG. 4A.

FIG. 5A illustrates a single layer of the stack during a stage in the method wherein gaps extend through the stack.

FIG. 5B is a cross-sectional view of the stack along the section line in FIG. 5A.

FIG. 6 is a cross-sectional view of the stack on the plane of FIG. 5B during a stage in the method wherein empty spaces exist between the oxide layers.

FIG. 7 is a cross-sectional view of the stack on the plane of FIG. 6 during a stage in the method wherein a first metal coats the stack.

FIG. 8A illustrates a single layer of the stack during a stage in the method wherein the first metal extends to be flush with lateral sides of the oxide layers.

FIG. 8B is a cross-sectional view of the stack along the section line in FIG. 8A.

FIG. 9A illustrates a layer of first metal and an oxide layer of the stack during a stage of the method wherein the first metal is recessed laterally inward from the lateral sides of the oxide layers.

FIG. 9B is a cross-sectional view along the section line in FIG. 9A.

FIG. 10A illustrates a single layer of the stack during a stage in the method wherein a phase change material coats the stack.

FIG. 10B is a cross-sectional view along the section line in FIG. 10A.

FIG. 11A illustrates a layer of the first metal and an oxide layer of the stack during a stage of the method wherein the phase change material is recessed laterally inward from the lateral sides of the oxide layers.

FIG. 11B is a cross-sectional view along the section line in FIG. 11A.

FIG. 12A is a cross-sectional view of the stack on the plane of FIG. 11B during a stage of the method wherein an ovonic threshold switch material coats the stack.

FIG. 12B is a cross-sectional view of the stack on the plane of FIG. 12A during a stage of the method wherein ovonic threshold switch material has been removed from lateral sides of the oxide layers.

FIG. 13A illustrates a single layer of the stack during a stage of the method wherein a second metal extends along the lateral sides of the oxide layers.

FIG. 13B is a cross-sectional view along the section line in FIG. 13A.

FIG. 14A illustrates a single layer of the stack according to another embodiment.

FIG. 14B is a cross-sectional view along the section line in FIG. 14A.

FIG. 15A illustrates a single layer of the stack according to yet another embodiment.

FIG. 15B is a cross-sectional view along the section line in FIG. 15A.

DETAILED DESCRIPTION

FIG. 1 illustrates an exemplary unit 10 of memory architecture. The unit 10 includes a bit line 12 and a word line 14 extending perpendicular to the bit line 12 and spaced apart from the bit line 12. A memory cell 16 extends perpendicular to both the bit line 12 and the word line 14 at a point where the bit line 12 crosses the word line 14 to contact both the bit line and the word line. The memory cell 16 includes a stack 18 of multiple elements, which may include one of or some combination of ovonic threshold switches, phase change materials, and metal conductors.

In a typical planar memory architecture, several mutually parallel bit lines 12 extend perpendicular to several mutually parallel word lines 14 on a plane, and memory cells 16 are arranged wherever a bit line 12 crosses a word line 14 to provide a planar grid of units 10. 3D cross point memory architecture includes multiple of such planar grids of units 10 layered in a direction perpendicular to the plane. Such 3D memory architectures may be produced by manufacturing multiple planar grids separately and layering the multiple planar grids within a memory device. Production of 3D memory architectures by layering separate planar grids can result in diminishing returns in cost savings per unit 10 of memory in a device, as certain production steps will have to be repeated for every layer of memory.

FIG. 2 illustrates a step in a method of producing a 3D memory architecture that includes batch creation of multiple integrated and self-aligned layers of memory. In the step illustrated in FIG. 2, a precursor stack 20 is formed. The precursor structure includes a substrate 22 with a planar surface, and alternating planar layers of oxide 24 and nitride 26 stacked upon the planar surface of the substrate 22. The illustrated number of oxide 24 and nitride 26 is merely exemplary, and it should be understood that the precursor stack 20 may include more or fewer layers. Further, though an oxide 24 layer is illustrated as contacting the planar surface of the substrate 22, the precursor stack 20 may alternatively be constructed such that a nitride 26 layer contacts the planar surface of the substrate 22.

As illustrated in FIGS. 3A and 3B, slots 28 are cut through the layers of oxide 24 and nitride 26 perpendicular to the planar surface of the substrate 22. Four slots 28 are illustrated, but more or fewer slots 28 may be cut as appropriate for an application. Further, though FIG. 3A illustrates the slots in aligned parallel rows, other arrangements of slots are contemplated.

After being cut, the slots 28 are filled with dielectric blocks 30 as illustrated in FIGS. 4A and 4B. The blocks 30 may be of any suitable dielectric, such as, for example, silicon carbide. Gaps 32 are cut through the layers of oxide 24 and nitride 26 and the blocks 30 as illustrated in FIGS. 5A and 5B. The gaps 32 extend through every layer of oxide 24 and nitride 26 and have a lengthwise direction along the plane of the planar surface of the substrate 22. Forming the gaps separates the layers of oxide 22 and nitride 26 into pillars 34. Three pillars are illustrated, but FIGS. 5A and 5B illustrate only a representative portion of a memory architecture, and it should be understood that a greater number of pillars 34 may be provided.

The nitride 26 layers are removed by any suitable removal process. The removal process may involve application of a chemical removing agent, such as, for example, hot phosphoric acid. The removal of the nitride 26 layers leaves spaces between the oxide 24 layers as shown in FIG. 6, which remain suspended in a mutually parallel arrangement by attachment to the blocks 30.

First metal 36 is deposited in the stack 20 such that the spaces between the oxide 24 layers are filled with first metal 36 as shown in FIG. 7. The first metal 36 may be any suitably conductive metal, such as, for example, tungsten. Excess first metal 36 is then removed by, for example, dry or wet etching to remove first metal 36 from lateral sides of the pillars 34 while leaving first metal 36 between the oxide 24 layers as shown in FIGS. 8A and 8B. The first metal 36 is thereby separated into several strips or individual layers of first metal 36 in each stack, alternating vertically with the layers of oxide 24. Once separated, the first metal 36 strips in each pillar provide word lines or bit lines. The first metal 36 is etched enough to recess it inward from the lateral sides of the pillar as defined by the oxide 34 layers as shown in FIGS. 9A and 9B. The lines provided by the first metal 36 are therefore laterally narrower than the vertically adjacent oxide 24 layers in each pillar, and are laterally centered relative to the pillars 34.

As shown in FIGS. 10A-11C, phase change material (PCM) 38 is then deposited in the stack 20 according to a similar process as the first metal 36. The PCM 38 is first deposited over the stack 20 to coat the pillars 34 and flow into the spaces between the oxide 24 layers left after etching the first metal 36, as shown in FIGS. 10A and 10B. The PCM 38 is then dry or wet etched to remove the PCM from the top and the lateral sides of the pillars 34 and recess the PCM 38 remaining between the oxide 24 layers from the lateral sides of the pillars 34, resulting in the stack 20 as shown in FIGS. 11A and 11B.

An ovonic threshold switch (OTS) 40 material is also deposited on the stack 20 according to a similar process as the first metal 36 and the PCM 38, as shown in FIGS. 12A and 12B. Specifically, OTS 40 material is deposited over the stack 20 as shown in FIG. 12A. The OTS 40 material is then dry or wet etched from the top and lateral sides of the pillars 34 as shown in FIG. 12B. As illustrated, the OTS 40 is etched to leave OTS 40 between the oxide 24 layers extending to be flush with the lateral sides of the pillars 34. However, in other examples, the OTS 40 material could be recessed inward from the lateral sides of the pillars 34 to allow for additional materials to be deposited between the oxide 24 layers. Further, although FIGS. 10A-12B show the PCM 38 deposited before the OTS 40, the OTS 40 may be deposited before the PCM 38 in other examples. After both being deposited, the PCM 38 and the OTS 40 remaining between each oxide 24 layer and on each side of the lines provided by the first metal 36 act as a memory cell 16.

Aligned memory cells 16 on a same layer and side of a pillar 34 are separated by the blocks 30, as shown in FIG. 13A. The second metal 42 may be any suitably conductive metal, such as, for example, tungsten, and may be the same metal, or a different metal, than the first metal 36. As shown in FIGS. 13A and 13B, second metal 42 is deposited on the lateral sides of the pillars 34 and between the blocks 30 to provide lines extending perpendicular the lines provided by the first metal 36. The second metal 42 thereby provides word lines if the first metal 36 provides bit lines, or the second metal 42 provides bit lines if the first metal 36 provides word lines. Thus, a 3D memory architecture is provided by lines of first metal 36 extending in a longitudinal direction and separated by oxide 24, lines of second metal 42 extending in a vertical direction perpendicular to the longitudinal direction and separated by oxide 24 and dielectric blocks 30, and multiple planar grids of memory cells 16 provided by adjoining PCM 38 and OTS 40 elements extending in a lateral direction perpendicular to the longitudinal and vertical directions between adjacent perpendicular lines of first metal 36 and second metal 42 where those lines cross each other.

3D memory architectures according to other exemplary arrangements are also contemplated. According to an example shown in FIGS. 14B and 14C, the second metal 42 may be deposited so as to completely fill the gaps 32 such that memory cells 16 on facing lateral sides of adjacent pillars 34 share vertical lines provided by the second metal 42. According to another example shown in FIGS. 15B and 15C, an oxide divider 44 may extend longitudinally and vertically through a laterally central plane of each pillar 34 such that memory cells 16 on opposite lateral sides of a pillar 34 do not share longitudinal lines provided by the first metal 36. The oxide dividers 44 may be produced by providing longitudinally extending fins of oxide 24 extending vertically between the oxide 24 layers during deposition of vertically alternating layers of oxide 24 and nitride 26 on the substrate 22.

Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.

Claims

A three dimensional memory stack, comprising:

a plurality of longitudinally extending vertical pillars including metal layers vertically alternating with dielectric layers, the metal layers providing word lines; and

bit lines extending vertically along lateral sides of the pillars, wherein a longitudinal direction is perpendicular to a vertical direction, and a lateral direction is perpendicular to the vertical direction and the longitudinal direction.
The memory stack of claim 1, wherein longitudinally adjacent and laterally aligned bit lines are separated in the longitudinal direction by blocks of dielectric material.
The memory stack of claim 1, wherein the metal layers in each stack are laterally narrower than vertically adjacent oxide layers.
The memory stack of claim 3, wherein memory cells are provided on lateral sides of the metal layers in each stack, and the memory cells extend to be flush with lateral sides of the pillars and to contact the bit lines.
The memory stack of claim 4, wherein each memory cell includes a phase change material element and an ovonic threshold switch element.
The memory stack of claim 4, wherein dielectric blocks extend into each lateral sides of the pillars and separate vertically and laterally aligned, longitudinally adjacent memory cells in the longitudinal direction.
The memory stack of claim 1, wherein planar oxide dividers extend vertically and longitudinally across a laterally central plane of each pillar.
A method for forming a three dimensional memory stack, comprising:

depositing alternating layers of oxide and nitride to form a vertical stack, wherein a vertical direction is perpendicular to a lateral direction and a longitudinal direction is perpendicular to the vertical direction and the lateral direction;

cutting parallel longitudinal gaps out of the vertical stack to provide multiple longitudinally extending vertical pillars;

providing empty spaces between the oxide layers by removing the nitride layers;

disposing longitudinally extending word lines in the empty spaces between the oxide layers, wherein the word lines are laterally narrower than the oxide layers;

disposing memory cells on lateral sides of the word lines, the memory cells extending to be flush with lateral sides of the pillars;

disposing vertically extending word lines within the gaps on the lateral sides of the pillars.
The method of claim 8, including:

cutting vertical slots through the memory stack, the slots being laterally wider than the gaps laterally aligned with the gaps; and

filling the slots with dielectric blocks before cutting the gaps.
The method of claim 8, wherein the step of disposing the word lines includes:

filling the empty spaces between the oxide layers with metal;

etching the metal such that any of the metal on the lateral sides of the pillars is removed, thereby creating discrete layers of the metal vertically alternating with the oxide layers in the pillars; and

etching the discrete layers of the metal such that the discrete layers of the metal are recessed laterally inward from the lateral sides of the pillars.
The method of claim 8, wherein the step of disposing the memory cells includes:

depositing a phase change material on the stack such that the phase change material extends between the oxide layers, then etching away any phase change material on the lateral sides of the pillars; and

depositing an ovonic threshold switch material on the stack such that the ovonic threshold switch material extends between the oxide layers, then etching away any ovonic threshold switch material on the lateral sides of the pillars.