CN113594200A

CN113594200A - Phase change memory and manufacturing method thereof

Info

Publication number: CN113594200A
Application number: CN202110765596.4A
Authority: CN
Inventors: 刘峻
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2021-07-07
Filing date: 2021-07-07
Publication date: 2021-11-02
Anticipated expiration: 2041-07-07
Also published as: CN113594200B

Abstract

The embodiment of the disclosure discloses a phase change memory and a manufacturing method thereof, wherein the phase change memory comprises the following steps: sequentially forming a first conductive layer, a first electrode layer, a first functional layer, a second electrode layer and a first sacrificial layer from bottom to top; forming a first isolation structure penetrating through the first conductive layer, the first electrode layer, the first functional layer, the second electrode layer and the first sacrificial layer; wherein the first isolation structure extends along a first direction; forming a second isolation structure penetrating through the first sacrificial strips, the second electrode strips, the first functional strips and the first electrode strips, wherein the second isolation structure extends along a second direction perpendicular to the first direction; removing the first sacrificial block to form a first groove; forming a second functional layer in the first trench; a third electrode layer and a second conductive layer are formed in this order on the second functional layer.

Description

Phase change memory and manufacturing method thereof

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, and in particular relates to a phase change memory and a manufacturing method of the phase change memory.

Background

As a new nonvolatile memory device, the phase change memory has great advantages over the flash memory in many aspects such as read-write speed, read-write times, data retention time, cell area, and multi-value implementation.

However, with the development of phase change memories, there are many problems in forming the elements in the phase change memory cells.

Disclosure of Invention

The embodiment of the disclosure provides a phase change memory and a manufacturing method of the phase change memory.

According to a first aspect of the embodiments of the present disclosure, a method for manufacturing a phase change memory is provided, including:

sequentially forming a first conductive layer, a first electrode layer, a first functional layer, a second electrode layer and a first sacrificial layer from bottom to top;

forming a first isolation structure penetrating through the first conductive layer, the first electrode layer, the first functional layer, the second electrode layer and the first sacrificial layer; wherein the first isolation structure extends in a first direction; the first isolation structure divides the first conducting layer into a plurality of first address wires which are parallel to each other, and divides the first electrode layer, the first functional layer, the second electrode layer and the first sacrificial layer into a first electrode strip, a first functional strip, a second electrode strip and a first sacrificial strip respectively;

forming a second isolation structure penetrating through the first sacrificial strip, the second electrode strip, the first functional strip and the first electrode strip, wherein the second isolation structure extends along a second direction perpendicular to the first direction, and the second isolation structure divides the first sacrificial strip into first sacrificial blocks;

removing the first sacrificial block to form a first groove;

forming a second functional layer in the first trench;

and sequentially forming a third electrode layer and a second conductive layer which are stacked on the second functional layer.

In the above scheme, the method further comprises:

forming a third isolation structure through the first sacrificial strip before forming the second isolation structure; wherein the second isolation structure penetrates the third isolation structure.

In the above scheme, the method further comprises:

after forming the first isolation structure, forming a second sacrificial layer on the first sacrificial strip;

the forming a third isolation structure through the first sacrificial strip includes:

forming a third isolation structure penetrating through the first sacrificial strip and the second sacrificial layer;

forming a second isolation structure penetrating through the first sacrificial strip, the second electrode strip, the first functional strip and the first electrode strip, comprising:

forming a second isolation structure penetrating through the first sacrificial strip, the second sacrificial layer, the second electrode strip, the first functional strip and the first electrode strip, wherein the second isolation structure divides the second sacrificial layer into second sacrificial strips;

the removing the first sacrificial block forms a first trench, comprising:

removing the first sacrificial block to form a first groove, and simultaneously removing the second sacrificial strip to form a second groove;

the forming a second functional layer in the first trench includes:

forming a second functional layer in the first trench and the second trench.

In the foregoing solution, the forming a third isolation structure penetrating through the first sacrificial strip and the second sacrificial layer includes:

forming a third trench penetrating the first sacrificial strip and the second sacrificial layer;

and forming a first covering layer on at least the side wall of the third groove to form the third isolation structure.

In the above solution, the forming of the second isolation structure penetrating through the first sacrificial strip, the second sacrificial layer, the second electrode strip, the first functional strip, and the first electrode strip includes:

forming a fourth groove penetrating through the second electrode bar, the first functional bar and the first electrode bar at the bottom of the third groove; the width of the third groove along the first direction is larger than that of the fourth groove along the first direction;

and forming a second covering layer on at least the side wall of the fourth groove and the surface of the first covering layer to form the second isolation structure.

In the above scheme, the method further comprises:

forming a fourth isolation structure penetrating through the third electrode layer and the second conductive layer; wherein the fourth isolation structure extends along the second direction; the fourth isolation structure divides the second conductive layer into a plurality of second address lines which are parallel to each other; the first electrode layer, the first functional layer, the second electrode layer, the second functional layer and the third electrode layer are divided into a plurality of first electrodes, first functional elements, second electrodes, second functional elements and third electrodes by the first isolation structure, the second isolation structure, the third isolation structure and the fourth isolation structure.

In the above scheme, the method further comprises:

sequentially forming a third conducting layer, a fourth electrode layer, a third functional layer, a fifth electrode layer and a third sacrificial layer which are stacked from bottom to top on the second address line;

forming a fifth isolation structure penetrating through the third conductive layer, the fourth electrode layer, the third functional layer, the fifth electrode layer and the third sacrificial layer; wherein the fifth isolation structure extends along the second direction; the fifth isolation structure divides the third conducting layer into a plurality of third address wires which are parallel to each other, and divides the fourth electrode layer, the third functional layer, the fifth electrode layer and the third sacrificial layer into a fourth electrode strip, a third functional strip, a fifth electrode strip and a third sacrificial strip respectively;

forming a sixth isolation structure through the third sacrificial strip; wherein the sixth isolation structures extend along the first direction, the sixth isolation structures dividing the third sacrificial strip into third sacrificial blocks;

forming a seventh isolation structure penetrating through the sixth isolation structure, the fifth electrode strips, the third functional strips and the fourth electrode strips;

removing the third sacrificial block to form a fifth groove;

forming a fourth functional layer in the fifth trench;

sequentially forming a sixth electrode layer and a fourth conductive layer which are stacked on the fourth functional layer;

forming an eighth isolation structure penetrating through the sixth electrode layer and the fourth conductive layer; wherein the eighth isolation structure extends along the first direction; the eighth isolation structure divides the fourth conductive layer into a plurality of fourth address lines parallel to each other; the fifth isolation structure, the sixth isolation structure, the seventh isolation structure and the eighth isolation structure divide the fourth electrode layer, the third functional layer, the fifth electrode layer, the fourth functional layer and the sixth electrode layer into a plurality of fourth electrodes, third functional elements, fifth electrodes, fourth functional elements and sixth electrodes.

In the above scheme, the method further comprises:

a fourth electrode layer, a third functional layer, a fifth electrode layer and a third sacrificial layer which are stacked are sequentially formed on the second conductive layer from bottom to top;

forming a ninth isolation structure penetrating through the third electrode layer, the second conductive layer, the fourth electrode layer, the third functional layer, the fifth electrode layer and the third sacrificial layer; wherein the ninth isolation structure extends along the second direction; the ninth isolation structure divides the second conducting layer into a plurality of second address wires which are parallel to each other, and divides the fourth electrode layer, the third functional layer, the fifth electrode layer and the third sacrificial layer into a fourth electrode strip, a third functional strip, a fifth electrode strip and a third sacrificial strip respectively;

forming a tenth isolation structure through the third sacrificial strip; wherein the tenth isolation structure extends along the first direction, the tenth isolation structure dividing the third sacrificial strip into third sacrificial blocks;

forming an eleventh isolation structure penetrating through the tenth isolation structure, the fifth electrode strips, the third functional strips and the fourth electrode strips;

removing the third sacrificial block to form a fifth groove;

forming a fourth functional layer in the fifth trench;

and sequentially forming a sixth electrode layer and a fourth conductive layer which are stacked on the fourth functional layer.

In the above-mentioned scheme, the first step of the method,

the first functional layer comprises a first gating layer, and the first phase change storage element formed by the first phase change storage layer is heated or quenched by the electrode through the conduction of a first gating element formed by the first gating layer so as to realize the switching between the crystalline state and the amorphous state of the first phase change storage element; the second functional layer comprises a first phase change storage layer, and data storage is realized through switching between the crystalline state and the amorphous state of the first phase change storage element.

In the foregoing solution, the removing the first sacrificial block includes:

and removing the first sacrificial block by adopting a wet etching process.

According to a second aspect of the embodiments of the present disclosure, there is provided a phase change memory including:

the phase change memory comprises a first address line, a first phase change memory unit and a second address line which are sequentially stacked from bottom to top; wherein the first address line and the second address line are parallel to the same plane and perpendicular to each other; the first phase change memory unit comprises a first electrode, a first functional element, a second electrode, a second functional element and a third electrode which are sequentially stacked from bottom to top; the first electrode, the first functional element and the second electrode are all vertical to the first address line and the second address line; the second functional element is at least partially orthogonal to both the first address line and the second address line; the third electrode is perpendicular to the first address line and parallel to the second address line;

a first isolation structure; the first isolation structures extend along a first direction and are arranged in parallel with the first address lines, the first electrodes, the first functional elements and the second electrodes which are arranged in a stacked mode in an alternating mode;

a second isolation structure; the second isolation structure extends along a second direction perpendicular to the first direction, and is arranged in parallel with the second functional element, the second electrode, the first functional element and the first electrode which are stacked alternately.

In the above scheme, the phase change memory further includes:

a third isolation structure; the second isolation structures penetrate through the third isolation structures, and the third isolation structures and the second functional elements are arranged in parallel and alternately.

In the above scheme, the second functional element includes a first sub-functional element and a second sub-functional element which are stacked from bottom to top; wherein,

the first sub-function element is perpendicular to both the first address line and the second address line;

the second sub-function element is perpendicular to the first address line and parallel to the second address line.

In the above scheme, the phase change memory further includes:

a fourth isolation structure; the fourth isolation structures extend along the second direction and are arranged in parallel with the third electrodes and the second address lines in an alternating manner.

In the above scheme, the phase change memory further includes:

the third address line, the second phase change memory unit and the fourth address line are sequentially stacked from bottom to top on the second address line; wherein the third address line is parallel to the second address line, and the fourth address line and the third address line are parallel to the same plane and perpendicular to each other; the second phase change memory unit comprises a fourth electrode, a third functional element, a fifth electrode, a fourth functional element and a sixth electrode which are sequentially stacked from bottom to top; the fourth electrode, the third functional element and the fifth electrode are all vertical to the third address line and the fourth address line; the fourth functional element is at least partially orthogonal to both the third address line and the fourth address line; the sixth electrode is perpendicular to the third address line and parallel to the fourth address line;

a fifth isolation structure; the fifth isolation structures extend along the second direction and are arranged in parallel and alternately with the stacked third address lines, fourth electrodes, third functional elements and fifth electrodes;

a sixth isolation structure; the sixth isolation structures extend along the first direction and are arranged in parallel with the fourth functional elements in an alternating manner;

a seventh isolation structure; the seventh isolation structure penetrates through the sixth isolation structure and is alternately arranged in parallel with the fourth electrode, the third functional element and the fifth electrode which are arranged in a stacked mode;

an eighth isolation structure; wherein the eighth isolation structures extend along the first direction and are alternately arranged in parallel with the sixth electrodes and the fourth address lines.

In the above scheme, the phase change memory further includes:

the second phase change memory unit and the fourth address line are sequentially stacked on the second address line from bottom to top; wherein the fourth address line and the second address line are parallel to the same plane and perpendicular to each other; the second phase change memory unit comprises a fourth electrode, a third functional element, a fifth electrode, a fourth functional element and a sixth electrode which are sequentially stacked from bottom to top; the fourth electrode, third functional element, and fifth electrode are all perpendicular to the second address line and the fourth address line; the fourth functional element is at least partially orthogonal to both the second address line and a fourth address line; the sixth electrode is perpendicular to the second address line and parallel to the fourth address line;

a ninth isolation structure; the ninth isolation structure extends along the second direction and is arranged in parallel with the stacked third electrode, second address line, fourth electrode, third functional element and fifth electrode in an alternating manner;

a tenth isolation structure; the tenth isolation structure extends along the first direction and is arranged in parallel with the fourth functional element in an alternating manner;

an eleventh isolation structure; and the eleventh isolation structure penetrates through the tenth isolation structure and is arranged in parallel with the fourth electrode, the third functional element and the fifth electrode in an alternating manner.

In the above scheme, the first functional element includes a first gate element, and the electrode is heated or quenched by conduction of the first gate element to realize switching between the crystalline state and the amorphous state of the first phase change memory element; the second functional element includes the first phase change memory element, and data storage is realized by switching between a crystalline state and an amorphous state of the first phase change memory element.

The embodiment of the disclosure provides a phase change memory and a manufacturing method of the phase change memory. The manufacturing method of the phase change memory comprises the following steps: sequentially forming a first conductive layer, a first electrode layer, a first functional layer, a second electrode layer and a first sacrificial layer from bottom to top; forming a first isolation structure penetrating through the first conductive layer, the first electrode layer, the first functional layer, the second electrode layer and the first sacrificial layer; wherein the first isolation structure extends in a first direction; the first isolation structure divides the first conducting layer into a plurality of first address wires which are parallel to each other, and divides the first electrode layer, the first functional layer, the second electrode layer and the first sacrificial layer into a first electrode strip, a first functional strip, a second electrode strip and a first sacrificial strip respectively; forming a second isolation structure penetrating through the first sacrificial strip, the second electrode strip, the first functional strip and the first electrode strip, wherein the second isolation structure extends along a second direction perpendicular to the first direction, and the second isolation structure divides the first sacrificial strip into first sacrificial blocks; removing the first sacrificial block to form a first groove; forming a second functional layer in the first trench; and sequentially forming a third electrode layer and a second conductive layer which are stacked on the second functional layer. In the embodiment of the disclosure, a first sacrificial layer is deposited on a second electrode layer, and a first isolation structure extending along a first direction and a second isolation structure extending along a second direction are formed, wherein the first isolation structure and the second isolation structure divide the first sacrificial layer into first sacrificial blocks; and finally, removing the first sacrificial block, and filling the first groove with a material for forming a second functional layer after the first sacrificial block is removed. That is, part of the material of the first functional layer is removed in the process of forming the first isolation structure, and the material for forming the second functional layer is directly filled into the first trench after the first trench is formed, so that the situation that part of the material of the first functional layer and part of the material of the second functional layer are removed simultaneously in the same process does not exist, and thus, the problem of cross contamination existing in the process of processing the first functional layer and the second functional layer is solved.

Drawings

FIG. 1 is a partial three-dimensional schematic diagram of a phase change memory of the related art;

FIG. 2a is a schematic diagram of a phase change memory in a related art;

FIG. 2b is a schematic diagram of a phase change memory according to the related art;

FIG. 3 is a flow chart illustrating an implementation of a method for fabricating a phase change memory according to an embodiment of the disclosure;

FIGS. 4 a-4 u are schematic cross-sectional views illustrating an implementation process of a method for fabricating a phase change memory according to an embodiment of the disclosure;

FIG. 5a is a schematic partial cross-sectional view of a phase change memory in accordance with an embodiment of the present disclosure in the plane of the xoz axis;

FIG. 5b is a schematic partial cross-sectional view of a phase change memory according to an embodiment of the present disclosure in the yoz-axis plane;

FIG. 6a is a schematic partial cross-sectional view of another phase change memory of an embodiment of the present disclosure in the plane of the xoz axis;

FIG. 6b is a schematic partial cross-sectional view of another phase change memory of an embodiment of the present disclosure in the yoz-axis plane;

FIG. 7 is a schematic partial cross-sectional view of yet another phase change memory of an embodiment of the present disclosure in the yoz-axis plane;

fig. 8 is a partial cross-sectional view of a further phase change memory according to an embodiment of the present disclosure in the yoz-axis plane.

Detailed Description

The technical solutions of the present disclosure will be further explained in detail with reference to the drawings and examples. While exemplary implementations of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The present invention is more particularly described in the following paragraphs with reference to the accompanying drawings by way of example. Advantages and features of the present disclosure will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present disclosure.

It is to be understood that the meaning of "on … …," "over … …," and "over … …" in this disclosure should be read in the broadest manner such that "on … …" not only means that it is "on" something without intervening features or layers therebetween (i.e., directly on something), but also includes the meaning of being "on" something with intervening features or layers therebetween.

In the embodiments of the present disclosure, the terms "first", "second", and the like are used for distinguishing similar objects, and are not necessarily used for describing a particular order or sequence.

In embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure, or a layer may be between any horizontal pair at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along inclined surfaces. The layer may comprise a plurality of sub-layers. For example, the interconnect layer may include one or more conductors and contact sub-layers (in which interconnect lines and/or via contacts are formed), and one or more dielectric sub-layers.

The technical means described in the embodiments of the present disclosure may be arbitrarily combined without conflict.

Fig. 1 is a partial three-dimensional schematic diagram of a phase change memory in the related art. Referring to fig. 1, the phase change memory includes a first address line 1020, a first phase change memory cell 1100a, a second address line 1060, a second phase change memory cell 1100b, and a third address line 1090, which are stacked in sequence from bottom to top; the first phase change memory cell 1100a includes a first electrode 1030a, a first gate element 1040, a second electrode 1030b, a first phase change memory element 1050, and a third electrode 1030c, which are sequentially stacked from bottom to top; the second phase change memory cell 1100b includes a fourth electrode 1030d, a second gate element 1070, a fifth electrode 1030e, a second phase change memory element 1080, and a sixth electrode 1030f, which are stacked in this order from bottom to top. The phase change memory may be based on heating and quenching the first and second phase

change memory elements

1050 and 1080 such that the first and second phase

change memory elements

1050 and 1080 are switched between the amorphous and crystalline states, and further, data may be stored using a difference between the resistivity of the first and second phase

change memory elements

1050 and 1080 in the amorphous state and the resistivity of the crystalline state.

As can be seen from fig. 1: the first address line 1020 is parallel to the third address line 1090, and both the first address line 1020 and the third address line 1090 are perpendicular to the second address line 1060; meanwhile, the first phase change memory cell 1100a is perpendicular to both the first address line 1020 and the second address line 1060, and the second phase change memory cell 1100b is perpendicular to both the second address line 1060 and the third address line 1090. The first address Line 1020 and the third address Line 1090 can be used as Bit lines (expressed in english as Bit Line), and the second address Line 1060 can be used as Word lines (expressed in english as Word Line). Fig. 2a shows a schematic electron microscope diagram corresponding to the phase change memory in fig. 1, and fig. 2b shows a schematic electron microscope diagram corresponding to fig. 2a at a larger magnification.

In the related art, a method of forming the first gate element 1040 and the first phase change memory element 1050 of the first phase change memory cell 1100a includes: forming five layers of films; the five layers of films comprise a first electrode layer, a first gating layer, a second electrode layer, a first phase change storage layer and a third electrode layer; the five films are etched together in a first direction and the five films are etched together in a second direction perpendicular to the first direction to form a phase change memory cell including a gate element and a phase change memory element.

That is, in the related art, when the etching in the first direction or the etching in the second direction is performed, a part of the material of the phase change memory layer and a part of the material of the gate layer are removed together. And the problem of cross contamination can occur when part of the materials of the phase change storage layer and the gate layer are removed simultaneously during the etching in the first direction, or when part of the materials of the phase change storage layer and the gate layer are removed simultaneously during the etching in the second direction.

Based on the above problem, an implementation flow of the phase change memory manufacturing method shown in fig. 3 is provided, where the method includes the following steps:

step 3001: sequentially forming a first conductive layer, a first electrode layer, a first functional layer, a second electrode layer and a first sacrificial layer from bottom to top;

step 3002: forming a first isolation structure penetrating through the first conductive layer, the first electrode layer, the first functional layer, the second electrode layer and the first sacrificial layer; wherein the first isolation structure extends in a first direction; the first isolation structure divides the first conducting layer into a plurality of first address wires which are parallel to each other, and divides the first electrode layer, the first functional layer, the second electrode layer and the first sacrificial layer into a first electrode strip, a first functional strip, a second electrode strip and a first sacrificial strip respectively;

step 3003: forming a second isolation structure penetrating through the first sacrificial strip, the second electrode strip, the first functional strip and the first electrode strip, wherein the second isolation structure extends along a second direction perpendicular to the first direction, and the second isolation structure divides the first sacrificial strip into first sacrificial blocks;

step 3004: removing the first sacrificial block to form a first groove;

step 3005: forming a second functional layer in the first trench;

step 3006: and sequentially forming a third electrode layer and a second conductive layer which are stacked on the second functional layer.

Fig. 4a to 4u are schematic cross-sectional views illustrating an implementation process of a method for fabricating a phase change memory according to an embodiment of the disclosure. The following describes the fabrication process of the phase change memory according to the embodiment of the present disclosure in detail with reference to fig. 4a to 4 u.

Note that in the xoz-axis plane and the yoz-axis plane referred to in fig. 4 a-4 u, the x-axis and the y-axis are both parallel to substrate 4010, the z-axis is perpendicular to substrate 4010, and the x-axis, the y-axis, and the z-axis are perpendicular to each other.

In step 3001, referring to fig. 4a, a first conductive layer 4020, a first electrode layer 4030a, a first functional layer 4040, a second electrode layer 4030b, and a first sacrificial layer 4050a are sequentially formed on a surface of a substrate 4010 from bottom to top.

Here, a constituent material of the substrate 4010 may include a semiconductor material such as silicon, germanium, or gallium arsenide.

It should be noted that "from bottom to top" in the embodiment of the present disclosure means a direction from a direction close to the surface of the substrate 4010 to a direction away from the surface of the substrate 4010.

Here, a constituent material of the first conductive layer 4020 includes a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, or the like.

Here, the constituent material of the first electrode layer 4030a and the second electrode layer 4030b includes amorphous carbon, for example, α -phase carbon.

Here, the first sacrificial layer 4050a may include a photoresist mask or a hard mask patterned based on a photolithography mask. Such as silicon nitride, etc.

Here, the first conductive Layer 4020, the first electrode Layer 4030a, the first functional Layer 4040, the second electrode Layer 4030b, and the first sacrificial Layer 4050a may be sequentially formed on the surface of the substrate 4010 through a Deposition process including, but not limited to, a Chemical Vapor Deposition (CVD) process, an Atomic Layer Deposition (ALD) process, or a combination thereof.

In step 3002, referring to fig. 4b to 4d, a first isolation structure penetrating through the first conductive layer 4020, the first electrode layer 4030a, the first functional layer 4040, the second electrode layer 4030b and the first sacrificial layer 4050a is formed; wherein the first isolation structure extends in a first direction; the first isolation structure divides the first conductive layer 4020 into a plurality of first address lines 4020-2 parallel to each other, and divides the first electrode layer 4030a, the first functional layer 4040, the second electrode layer 4030b, and the first sacrificial layer 4050a into first electrode strips 4030a-1, first functional strips 4040-1, second electrode strips 4030b-1, and first sacrificial strips 4050a-1, respectively.

Here, the first direction is parallel to the surface of the substrate 4010, and in practical applications, the first direction may be understood as a y-axis direction shown in fig. 4a to 4u, and it is understood that the first direction is not limited to the y-axis direction.

In some embodiments, forming the first isolation structure comprises:

forming a sixth trench 4016 penetrating the first conductive layer 4020, the first electrode layer 4030a, the first functional layer 4040, the second electrode layer 4030b, and the first sacrificial layer 4050 a;

a third capping layer is formed on at least the sidewalls of the sixth trench 4016 to form the first isolation structure.

In practical applications, the above method for forming the first isolation structure is described with reference to fig. 4b to 4 d.

As shown in fig. 4b, first, etching is performed along a direction parallel to the z-axis to form a sixth trench 4016 penetrating the first conductive layer 4020, the first electrode layer 4030a, the first functional layer 4040, the second electrode layer 4030b, and the first sacrificial layer 4050a, wherein a bottom of the sixth trench 4016 exposes the substrate 4010.

Here, the method of forming the sixth trench 4016 may include, but is not limited to, dry plasma etching.

In practical applications, the sixth grooves 4016 may include one or more, and a plurality of the sixth grooves 4016 are illustrated in fig. 4b, wherein the plurality of the sixth grooves 4016 are arranged in parallel along a direction parallel to the x-axis.

After forming the sixth trench 4016, as shown in fig. 4c, said forming a third capping layer at least on the sidewalls of the sixth trench 4016 comprises: forming a first insulating layer 4100 covering sidewalls of the sixth trenches 4016 and an upper surface of the first sacrificial strip 4050 a-1; forming a second insulating layer 4200 covering the first insulating layer 4100; forming a third insulating layer 4300 covering the second insulating layer 4200 while covering the bottom of the sixth trench 4016; the third insulating layer 4300 is filled with a first insulating material to form a first insulating structure 4400. That is, the third cover layer includes the first insulating layer 4100, the second insulating layer 4200, the third insulating layer 4300, and the first thermal insulation structure 4400.

In practical applications, the first insulating layer 4100, the second insulating layer 4200, the third insulating layer 4300, and the first thermal isolation structure 4400 may be formed by CVD or ALD. The composition material of the first insulating layer 4100 may include, but is not limited to, nitride such as silicon nitride. The composition material of the second insulating layer 4200 may include an oxide such as silicon oxide, but is not limited thereto. The first insulating layer 4100 and the second insulating layer 4200 are used to encapsulate the covered first address lines 4020 to 2, the first electrode bars 4030a to 1, the first functional bars 4040 to 1, and the second electrode bars 4030b to 1. The composition material of the third insulating layer 4300 may include a nitride, such as silicon nitride, but is not limited thereto. The composition material of the first thermal isolation structure 4400 may include an oxide, such as silicon oxide, but is not limited thereto. The third insulating layer 4300 and the first thermal isolation structure 4400 overlying the second insulating layer 4200 serve to electrically isolate adjacent first address lines 4020-2, first electrode stripes 4030a-1, first functional stripes 4040-1 and second electrode stripes 4030b-1 in the x-direction.

In practical applications, after forming the third capping layer, the method further includes: first insulating layer 4100, second insulating layer 4200, third insulating layer 4300, and first thermal isolation structure 4400 covering the surface of first sacrificial strip 4050a-1 are removed, and first sacrificial strip 4050a-1 is exposed (as shown in fig. 4 d).

In practical applications, the first insulating layer 4100, the second insulating layer 4200, the third insulating layer 4300, and the first thermal insulation structure 4400 covering the surface of the first sacrificial strip 4050a-1 can be removed by Chemical Mechanical Polishing (CMP).

As shown in fig. 4d, the first insulating layer 4100, the second insulating layer 4200, the third insulating layer 4300 and the first thermal isolation structure 4400 together constitute a first isolation structure, which extends along a first direction; the first isolation structure divides the first conductive layer 4020 into a plurality of first address lines 4020 to 2 parallel to each other.

In some embodiments, the method for manufacturing a phase change memory further includes:

after the first isolation structures are formed, a second sacrificial layer 4050b is formed on the first sacrificial strip 4050 a-1.

In practical applications, referring to fig. 4e to fig. 4f, a first mask layer 4050c may be further formed on the second sacrificial layer 4050b, wherein the second sacrificial layer 4050b may be made of the same material as the first sacrificial layer 4050a, and the first mask layer 4050c may include carbon or the like.

It should be noted that the first mask layer 4050c is used to transfer a pattern when forming a third trench in a subsequent process, the first mask layer 4050c is removed when forming the third trench, and the second sacrificial layer is used to form a second trench in the subsequent process, so that a material for forming the second functional layer is directly filled into the second trench in the subsequent process.

It should be noted that fig. 4f shows a cross-sectional view at the AA' position of fig. 4e, in the plane zoy.

In step 3003, second isolation structures are formed through the first sacrificial strip 4050a-1, second electrode strip 4030b-1, first functional strip 4040-1, first electrode strip 4030a-1, the second isolation structures extending in a second direction perpendicular to the first direction, the second isolation structures dividing the first sacrificial strip 4050a-1 into first sacrificial blocks 4050 a-2.

In some embodiments, the method further comprises:

forming third isolation structures through the first sacrificial strip 4050a-1 prior to forming second isolation structures; wherein the second isolation structure penetrates the third isolation structure.

In some embodiments, forming the third isolation structure through the first sacrificial strip 4050a-1 comprises:

third isolation structures are formed through the first sacrificial strip 4050a-1 and second sacrificial layer 4050 b.

In some embodiments, forming a second isolation structure through the first sacrificial strip 4050a-1, second electrode strip 4030b-1, first functional strip 4040-1, first electrode strip 4030a-1 comprises:

a second isolation structure is formed through the first sacrificial strip 4050a-1, second sacrificial layer 4050b, second electrode strip 4030b-1, first functional strip 4040-1, first electrode strip 4030a-1, which second isolation structure divides the second sacrificial layer 4050b into second sacrificial strips 4050 b-1.

That is, when second sacrificial layer 4050b is not formed on first sacrificial strip 4050a-1, the second isolation structure extends through first sacrificial strip 4050a-1 in the second direction; and when second sacrificial layer 4050b is formed over first sacrificial strip 4050a-1, the second isolation structures extend through first sacrificial strip 4050a-1 and second sacrificial layer 4050b in a second direction. It is to be understood that illustrated in FIG. 4i is the case where the second isolation structure extends through first sacrificial strip 4050a-1 and second sacrificial layer 4050b in the second direction. The second isolation structures divide first sacrificial strip 4050a-1 and second sacrificial layer 4050b into first sacrificial block 4050a-2 and second sacrificial strip 4050b-1, respectively. Here, the second direction is parallel to the surface of the substrate 4010, and in practical applications, the second direction may be understood as an x-axis direction shown in fig. 4a to 4u, and it is understood that the second direction is not limited to the x-axis direction.

In some embodiments, the forming a third isolation structure through the first sacrificial strip 4050a-1 and the second sacrificial layer 4050b comprises:

forming a third trench 4013 through said first sacrificial strip 4050a-1 and said second sacrificial layer 4050 b;

a first capping layer is formed on at least the sidewalls of the third trench 4013 to form the third isolation structure.

In practical applications, the above method for forming the third isolation structure is described with reference to fig. 4g to 4 i.

It should be noted that fig. 4h shows a cross-sectional view at the AA' position of fig. 4g, in the plane zoy.

As shown in fig. 4 g-4 h, a plurality of third trenches 4013 are formed through first sacrificial strip 4050a-1 and second sacrificial layer 4050b in a direction parallel to the z-axis; wherein the bottom of the third trench 4013 exposes the second electrode strip 4030 b-1. A plurality of third grooves 4013 are arranged side by side in a direction parallel to the y-axis, each third groove 4013 extending in a direction parallel to the x-axis.

In practice, the first mask layer 4050c is removed during the process of forming the third trench.

As shown in fig. 4i, a fourth insulating layer 4500 covering sidewalls of the third trench 4013 is formed, and a fifth insulating layer 4600 covering the fourth insulating layer 4500 is formed; the fourth insulating layer 4500 and the fifth insulating layer 4600 collectively form a first cover layer. It is understood that when the fourth insulating layer 4500 is formed on the sidewalls of the third trench 4013, the fourth insulating layer 4500 is also formed on the upper surface of the second sacrificial strip 4050b-1, and when the fifth insulating layer 4600 is formed on the sidewalls of the fourth insulating layer 4500, the fifth insulating layer 4600 is also formed on the upper surface of the fourth insulating layer 4500.

Here, the second isolation structure extends in the same direction as the third isolation structure, i.e., a second direction.

In some embodiments, forming a second isolation structure through the first sacrificial strip 4050a-1, second sacrificial layer 4050b, second electrode strip 4030b-1, first functional strip 4040-1, first electrode strip 4030a-1 includes:

forming a fourth trench 4014 through the second electrode strip 4030b-1, the first functional strip 4040-1 and the first electrode strip 4030a-1 at the bottom of the third trench 4013; a width of the third groove 4013 in the first direction is greater than a width of the fourth groove 4014 in the first direction;

a second capping layer is formed on at least the sidewalls of the fourth trench 4014 and the surface of the first capping layer to form the second isolation structure.

In practical applications, the above method for forming the second isolation structure is described with reference to fig. 4j to 4 l.

As shown in fig. 4j, a fourth trench 4014 is formed by etching the second electrode strip 4030b-1, the first functional strip 4040-1 and the first electrode strip 4030a-1 from the bottom of the third trench 4013 in a direction parallel to the z-axis; wherein the fourth trench 4014 extends through the second sacrificial strip 4050b-1, the first sacrificial block 4050a-2, the second electrode strip 4030b-1, the first functional strip 4040-1 and the first electrode strip 4030a-1, and the bottom of the fourth trench 4014 exposes the first address line 4020-2. A plurality of fourth grooves 4014 are arranged side by side in a direction parallel to the y-axis, and each fourth groove 4014 extends in a direction parallel to the x-axis.

As shown in fig. 4k, a sixth insulating layer 4700 covering the fifth insulating layer 4600, the sidewalls of the fourth trench 4014 and the bottom of the fourth trench 4014 is formed; the fourth trench 4014 where the sixth insulating layer 4700 is formed is filled with a filler, so that a second thermal isolation structure 4800 is formed. The fourth insulating layer 4500 and the fifth insulating layer 4600 in the third trench 4013 collectively form a third isolation structure; the sixth insulating layer 4700 and the second heat insulating structure 4800 in the fourth trench 4014 collectively constitute a second isolation structure, and the sixth insulating layer 4700 and the second heat insulating structure 4800 covering the side wall of the fourth trench 4014 serve to electrically isolate the adjacent second electrode 4030b-2, first functional element 4040-2, and first electrode 4030a-2 in the y direction. The second capping layer includes a sixth insulating layer 4700 and a second thermal insulation structure 4800.

Here, as shown in fig. 4j, the third groove 4013 is formed to have a width in the y-axis direction larger than that of the fourth groove 4014; it is to be understood that, after the third trench 4013 is formed, the sidewalls of the third trench 4013 are covered with the fourth insulating layer 4500 and the fifth insulating layer 4600, and when the fourth trench 4014 is formed by etching the second electrode strip 4030b-1, the first functional strip 4040-1 and the first electrode strip 4030a-1 from the bottom of the third trench 4013, the opening size of the fourth trench 4014 is smaller than the opening size of the third trench 4013 after the sidewalls of the third trench 4013 are covered with the fourth insulating layer 4500 and the fifth insulating layer 4600.

As shown in fig. 4l to 4m, the method of removing the fourth insulating layer 4500, the fifth insulating layer 4600, the sixth insulating layer 4700 and the second thermal isolation structure 4800 on the second sacrificial strip 4050b-1 to expose the second sacrificial strip 4050b-1 includes CMP. As shown in fig. 4l and 4m, the first and second isolation structures sequentially divide the first electrode layer 4030a, the first functional layer 4040, and the second electrode layer 4030b into a plurality of first electrodes 4030a-2, a plurality of first functional elements 4040-2, and a plurality of second electrodes 4030 b-2.

It should be noted that fig. 4m shows a cross-sectional view at the AA' position of fig. 4l, in the plane zoy.

In step 3004, referring to FIGS. 4 n-4 o, the first sacrificial block 4050a-2 is removed, forming a first trench 4011.

It should be noted that fig. 4o shows a cross-sectional view at the AA' position of fig. 4n in the plane zoy.

In some embodiments, the removing the first sacrificial block 4050a-2 comprises:

and removing the first sacrificial block 4050a-2 by using a wet etching process.

In some embodiments, the removing the first sacrificial block 4050a-2 to form a first trench 4011 comprises:

the first sacrificial block 4050a-2 is removed to form a first trench 4011 and the second sacrificial strip 4050b is simultaneously removed to form a second trench 4012.

That is, when the second sacrificial layer 4050b is not formed on the first sacrificial strip 4050a-1, the first trench 4011 is formed; and when the second sacrificial layer 4050b is formed on the first sacrificial strip 4050a-1, the first trench 4011 and the second trench 4012 are formed in communication. It is to be understood that illustrated in fig. 4n to 4o are the case where the first trench 4011 and the second trench 4012 which communicate are formed.

It will be appreciated that the method of removing first sacrificial block 4050a-2 and second sacrificial strip 4050b-1 comprises a wet etch. The wet etch is highly selective, where only the first sacrificial block 4050a-2 and the second sacrificial strip 4050b-1 need be removed, and is therefore preferred. Illustratively, when the constituent material of first sacrificial block 4050a-2 and second sacrificial strip 4050b-1 is silicon nitride, first sacrificial block 4050a-2 and second sacrificial strip 4050b-1 can be removed by a phosphoric acid solution. The method of removing first sacrificial block 4050a-2 and second sacrificial strip 4050b-1 may also comprise a dry etch.

In step 3005, referring to fig. 4 p-4 q, a second functional layer 4060 is formed in said first trench 4011.

Fig. 4q shows a cross-sectional view at the AA' position of fig. 4p, in the plane zoy.

In some embodiments, the forming of the second functional layer 4060 in the first trench 4011 includes:

a second functional layer 4060 is formed in the first trench 4011 and the second trench 4012.

That is, when the second sacrificial layer 4050b is not formed on the first sacrificial strip 4050a-1, the second functional layer 4060 is formed in the first trench 4011; and when the second sacrificial layer 4050b is formed on the first sacrificial strip 4050a-1, the second functional layer 4060 is formed in the first trench 4011 and the second trench 4012. It is to be understood that illustrated in fig. 4p to 4q is a case where the second functional layer 4060 is formed in the first trench 4011 and the second trench 4012.

In practice, the second functional layer 4060 is formed by a Deposition process, including but not limited to CVD and ALD, wherein CVD includes Metal-Organic Chemical Vapor Deposition (MOCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), and the like.

In practice, as shown in fig. 4 p-4 q, after depositing the second functional layer 4060 into the first trench 4011 and the second trench, a second functional component 4060-2 is formed. Wherein the second functional component 4060-2 comprises a first sub-functional component 4060a-2 and a second sub-functional component 4060b-2, and the first sub-functional component 4060a-2 is formed from the material of the second functional layer deposited in the first trench 4011, the second sub-functional component 4060b-2 is formed from the material of the second functional layer deposited in the second trench 4012, the first sub-functional component 4060a-2 is juxtaposed alternately with the first isolation structures in the x-axis direction and is juxtaposed alternately with the third isolation structures in the y-axis direction, the second sub-functional component 4060b-2 is juxtaposed alternately with the third isolation structures in the y-axis direction, and the second sub-functional component 4060b-2 extends in the x-axis direction and is perpendicular to the first 4020-2 address lines.

It can be understood that, in the related art, after the first functional layer and the second functional layer are deposited, the first functional layer and the second functional layer are etched in the first direction to form a first isolation structure penetrating through the first functional layer and the second functional layer, the first isolation structure divides the first functional layer and the second functional layer into a first functional strip and a second functional strip respectively, and then the first functional layer and the second functional layer are etched in the second direction perpendicular to the first direction to form a third isolation structure penetrating through the first functional strip and the second functional strip, so that the first functional layer and the second functional layer both have a cross contamination problem when the first functional layer and the second functional layer are etched in the first direction and the second direction.

In some embodiments of the present disclosure, the first sacrificial layer 4050a is first deposited on the second electrode layer 4030b, and a first isolation structure extending along the first direction is formed, after the first isolation structure divides the first sacrificial layer 4050a into first sacrificial strips 4050a-1, the first sacrificial strips 4050a-1 are removed, and the first trench 4011 after the first sacrificial strip 4050a-1 is removed is filled with a material for forming the second functional layer 4060, that is, when the first direction etching is performed to form the first isolation structure, a part of the material of the first functional layer 4040 is removed, while the material used to form the second functional layer 4060 is filled directly into the first trench 4011, this is so that part of the material of the first functional layer 4040 and part of the material of the second functional layer 4060 are not removed simultaneously in the same process when forming the first separation structure, which improves the problem of cross-contamination at least in the first direction.

In other embodiments of the present disclosure, a first sacrificial layer 4050a is deposited on the second electrode layer 4030b, a first isolation structure extending along the first direction and a third isolation structure extending along the second direction are formed, the first isolation structure and the third isolation structure divide the first sacrificial layer 4050a into first sacrificial blocks 4050a-2, then the first sacrificial blocks 4050a-2 are removed, and the first trenches 4011 formed after the first sacrificial blocks 4050a-2 are removed are directly filled with a material for forming the second functional layer 4060. That is, when the first isolation structure is formed by performing the etching in the first direction, part of the material of the first functional layer 4040 is removed, and after the third isolation structure is formed by performing the etching in the second direction, the material for forming the second functional layer 4060 is directly filled in the first trench 4011, so that part of the material of the first functional layer 4040 and part of the material of the second functional layer 4060 are not removed simultaneously in the same process when the first isolation structure is formed, and part of the material of the first functional layer 4040 and part of the material of the second functional layer 4060 are not removed simultaneously in the same process when the third isolation structure is formed, which improves the problem of cross contamination in both the first direction and the second direction.

In some embodiments, the first functional layer 4040 includes a first gate layer, and the first phase change memory element formed by the first gate layer is heated or quenched by the electrode through conduction of the first gate element to switch between the crystalline state and the amorphous state of the first phase change memory element; the second functional layer 4060 includes the first phase change memory layer, and data storage is realized by switching between a crystalline state and an amorphous state of the first phase change memory element.

It is understood that the second functional layer 4060 may include a phase change memory layer, and may also include a pass layer; the first functional layer 4040 may include a phase change memory layer and may also include a gate layer. However, the first functional layer 4040 and the second functional layer 4060 cannot be the same layer, e.g., when the first functional layer 4040 is a phase change memory layer, the second functional layer 4060 is a gate layer; alternatively, when the first functional layer 4040 is a pass layer, the second functional layer 4060 is a phase change memory layer.

Here, the constituent materials of the gate layer may include: threshold selection switch (OTS) materials, such as zinc telluride (ZnaTeb), germanium telluride (GeaTeb), niobium oxide (NbaOb), or silicon arsenic telluride (SiaAsbTec).

Here, the composition materials of the phase-change memory layer may include: chalcogenide-based alloys, such as, but not limited to, GST (Ge-Sb-Te) alloys. The constituent material of the phase-change memory layer may also include any other suitable phase-change material. Note that when the phase change memory element undergoes a phase change, the resistance of the phase change memory element changes. Phase change memories store data according to changes in the resistance state of a phase change memory element.

It can be understood that, when the second functional layer 4060 is a phase change memory layer, the manner of forming the phase change memory layer includes directly depositing a material for forming the phase change memory layer in the closed unit structure (the first trench 4011 and the second trench 4012), and as the case that the phase change memory layer of the whole plane is formed first and then the phase change memory layer having a shape similar to that of the first trench 4011 and the second trench 4012 is obtained by dry etching is avoided, the damage to the phase change memory device caused by the dry etching is also avoided.

In step 3006, referring to fig. 4r, a third electrode layer 4030c and a second conductive layer 4070 are sequentially formed on the second functional layer 4060.

In some embodiments, the method for manufacturing a phase change memory further includes: forming a fourth isolation structure penetrating the third electrode layer 4030c and the second conductive layer 4070; wherein the fourth isolation structure extends along the second direction; the fourth isolation structure divides the second conductive layer 4070 into a plurality of second address lines 4070-2 that are parallel to each other; the first, second, third and fourth isolation structures divide the first electrode layer 4030a, the first functional layer 4040, the second electrode layer 4030b, the second functional layer 4060 and the third electrode layer 4030c into a plurality of first electrodes 4030a-2, first functional elements 4040-2, second electrodes 4030b-2, second functional elements 4060-2 and third electrodes 4030 c-2.

In practical applications, the method for forming the fourth isolation structure is described with reference to fig. 4s to 4 u.

As shown in fig. 4s, a plurality of seventh trenches 4017 are formed that penetrate the third electrode layer 4030c and the second conductive layer 4070 in a direction parallel to the z-axis; wherein the bottom of the seventh trench 4017 exposes the third isolation structure. A plurality of seventh grooves 4017 are juxtaposed in a direction parallel to the y-axis, each seventh groove 4017 extending in a direction parallel to the x-axis.

As shown in fig. 4 t-4 u, the seventh trench 4017 is filled with a first dielectric layer 4090 to form a fourth isolation structure, and a bottom of the fourth isolation structure is aligned with an upper surface of the third isolation structure.

Fig. 4u shows a cross-sectional view in plane zoy at position AA' of fig. 4 t.

Here, the first dielectric layer 4090 includes silicon oxide, but is not limited thereto.

The first electrode 4030a-2, the first functional element 4040-2, the second electrode 4030b-2, the second functional element 4060-2, and the third electrode 4030c-2 described above collectively constitute a memory cell of a phase-change memory. The number of phase change memory cells formed in the z-axis direction may include one or more, and in the above method, a case of forming one phase change memory cell and an address line in the z-axis direction is described, and a method of forming a second phase change memory cell and an address line in a first phase change memory cell in the z-axis direction will be described below.

removing the third sacrificial block to form a fifth groove;

forming a fourth functional layer in the fifth trench;

Here, a cross-sectional view of a phase change memory cell layer having a two-layer stack formed in this embodiment can be referred to fig. 7.

removing the third sacrificial block to form a fifth groove;

forming a fourth functional layer in the fifth trench;

Here, a cross-sectional view of a phase change memory cell layer having a two-layer stack formed in this embodiment can be referred to fig. 8. It should be noted that fig. 8 and fig. 7 illustrate corresponding manufacturing schemes for forming a phase change memory cell layer with two stacked layers. It will be appreciated that in comparison with the corresponding manufacturing scheme of fig. 7, in one aspect, the corresponding manufacturing scheme of fig. 8 does not require the formation of the third address line 4080-2, which may save material for forming the address lines; on the other hand, the corresponding manufacturing scheme in fig. 8 is to form a ninth isolation structure and a tenth isolation structure, and to divide the third electrode layer and the second conductive layer into a plurality of third electrodes 4030c-2 and second address lines 4070-2 through the ninth isolation structure and the tenth isolation structure, that is, the third electrodes 4030c-2 and the second address lines 4070-2 of the corresponding manufacturing scheme in fig. 8 are formed in synchronization with the fourth electrodes 4030d-2, the third functional elements 4091-2 and the fifth electrodes 4030e-2 in the second layer stack, while the corresponding manufacturing scheme in fig. 7 is to form a fourth isolation structure penetrating through the third electrode layer and the second conductive layer, and to divide the third electrode layer and the second conductive layer into a plurality of third electrodes 4030c-2 and second address lines 4070-2 by using the fourth isolation structure, and then to form a fifth isolation structure and a seventh isolation structure, the fourth electrode layer, the third functional layer and the fifth electrode layer are divided into a plurality of fourth electrodes 4030d-2, third functional elements 4091-2 and fifth electrodes 4030e-2 by using the fifth isolation structure and the seventh isolation structure, so that compared with the corresponding manufacturing scheme in fig. 7, the process flow of the corresponding manufacturing scheme in fig. 8 is simpler.

In the corresponding embodiments shown in fig. 8 and 7, it is conceivable that the formation of the fourth functional layer is performed such that the two sub-functional layers are formed when the second functional layer is formed as described above.

In practical applications, the method for forming the second phase change memory cell and the address line is similar to the specific method for forming the first phase change memory cell and the address line, and is not described herein again.

It should be noted that the first address line, the second address line, the third address line, and the fourth address line may be used as word lines of the three-dimensional phase change memory, or may also be used as bit lines of the three-dimensional phase change memory, but it needs to be satisfied that when the first address line and the fourth address line are used as word lines of the three-dimensional phase change memory, the second address line and the third address line can only be used as bit lines of the three-dimensional phase change memory; when the first address line and the fourth address line are used as bit lines of the three-dimensional phase change memory, the second address line and the third address line can only be used as word lines of the three-dimensional phase change memory.

It can be understood that the phase change memory cell of the phase change memory provided by the embodiment of the disclosure is formed by self-aligned patterning and etching at the intersection of the word line and the bit line, and the phase change memory element in the phase change memory cell is formed by directly depositing a material for forming the phase change memory element in a closed cell structure by an ALD or CVD method. Thus, cross-contamination between the material forming the phase change memory element and the material forming the gate element is mitigated.

The embodiment of the disclosure provides a manufacturing method of a phase change memory, which includes: sequentially forming a first conductive layer, a first electrode layer, a first functional layer, a second electrode layer and a first sacrificial layer from bottom to top; forming a first isolation structure penetrating through the first conductive layer, the first electrode layer, the first functional layer, the second electrode layer and the first sacrificial layer; wherein the first isolation structure extends in a first direction; the first isolation structure divides the first conducting layer into a plurality of first address wires which are parallel to each other, and divides the first electrode layer, the first functional layer, the second electrode layer and the first sacrificial layer into a first electrode strip, a first functional strip, a second electrode strip and a first sacrificial strip respectively; forming a second isolation structure penetrating through the first sacrificial strip, the second electrode strip, the first functional strip and the first electrode strip, wherein the second isolation structure extends along a second direction perpendicular to the first direction, and the second isolation structure divides the first sacrificial strip into first sacrificial blocks; removing the first sacrificial block to form a first groove; forming a second functional layer in the first trench; and sequentially forming a third electrode layer and a second conductive layer which are stacked on the second functional layer. In the embodiment of the disclosure, a first sacrificial layer is deposited on a second electrode layer, and a first isolation structure extending along a first direction and a second isolation structure extending along a second direction are formed, wherein the first isolation structure and the second isolation structure divide the first sacrificial layer into first sacrificial blocks; and finally, removing the first sacrificial block, and filling the first groove with a material for forming a second functional layer after the first sacrificial block is removed. That is, part of the material of the first functional layer is removed in the process of forming the first isolation structure, and the material for forming the second functional layer is directly filled into the first trench after the first trench is formed, so that the situation that part of the material of the first functional layer and part of the material of the second functional layer are removed simultaneously in the same process does not exist, and thus, the problem of cross contamination existing in the process of processing the first functional layer and the second functional layer is solved.

Based on the above method for manufacturing a phase change memory, an embodiment of the present disclosure further provides a phase change memory, with reference to fig. 5a to 5b, including:

the phase change memory comprises a first address line 4020-2, a first phase change memory unit 4000a and a second address line 4070-2 which are sequentially stacked from bottom to top; wherein the first address line 4020-2 and the second address line 4070-2 are parallel to the same plane and perpendicular to each other; the first phase-change memory cell 4000a includes a first electrode 4030a-2, a first functional element 4040-2, a second electrode 4030b-2, a second functional element 4060-2, and a third electrode 4030c-2 which are stacked in this order from bottom to top; the first electrode 4030a-2, first functional element 4040-2, second electrode 4030b-2 are each perpendicular to the first address line 4020-2 and second address line 4070-2; the second functional element 4060-2 is at least partially orthogonal to both the first address line 4020-2 and the second address line 4070-2; the third electrode 4030c-2 is perpendicular to the first address line 4020-2 and parallel to the second address line 4070-2;

a first isolation structure; the first isolation structures extend along a first direction and are arranged in parallel with the first address lines 4020-2, the first electrodes 4030a-2, the first functional elements 4040-2 and the second electrodes 4030b-2 which are arranged in a stacked manner in an alternating manner;

a second isolation structure; the second isolation structures extend along a second direction perpendicular to the first direction, and are arranged in parallel with the second functional components 4060-2, the second electrodes 4030b-2, the first functional components 4040-2 and the first electrodes 4030a-2 which are arranged in a stacked manner in an alternating manner.

In some embodiments, the phase change memory further comprises:

a third isolation structure; the second isolation structure penetrates through the third isolation structure, and the third isolation structure and the second functional element 4060-2 are arranged in parallel and alternately.

In some embodiments, the phase change memory further comprises:

a fourth isolation structure; wherein the fourth isolation structures extend along the second direction and are arranged alternately in parallel with the third electrodes 4030c-2 and the second address lines 4070-2.

It should be noted that fig. 5b shows a cross-sectional view at the AA' position of fig. 5a, in the plane zoy.

In some embodiments, referring to figures 6 a-6 b, the second functional component 4060-2 comprises a first sub-functional component 4060a-2 and a second sub-functional component 4060b-2 arranged in a bottom-to-top stack; wherein,

the first sub-functional element 4060a-2 is perpendicular to both the first address line 4020-2 and the second address line 4070-2;

the second sub-functional element 4060b-2 is perpendicular to the first address line 4020-2 and parallel to the second address line 4070-2;

the first isolation structures extend in a first direction, and are alternately arranged in parallel with the first address lines 4020 to 2, the first electrodes 4030a to 2, the first functional elements 4040 to 2, the second electrodes 4030b to 2, and the first sub-functional elements 4060a to 2 which are stacked.

Fig. 6b shows a cross-sectional view at the AA' position of fig. 6a, in the plane zoy.

In some embodiments, referring to fig. 7, the phase change memory further includes:

a third address line 4080-2, a second phase change memory unit 4000b and a fourth address line 4095-2 which are sequentially stacked from bottom to top on the second address line 4070-2; wherein the third address line 4080-2 is parallel to the second address line 4070-2, and the fourth address line 4095-2 and the third address line 4080-2 are parallel to the same plane and perpendicular to each other; the second phase change memory cell 4000b comprises a fourth electrode 4030d-2, a third functional element 4091-2, a fifth electrode 4030e-2, a fourth functional element 4093-2 and a sixth electrode 4030f-2 which are sequentially stacked from bottom to top; the fourth electrode 4030d-2, the third functional element 4091-2 and the fifth electrode 4030e-2 are all perpendicular to the third address line 4080-2 and the fourth address line 4095-2; the fourth functional element 4093-2 is at least partially orthogonal to both the third address line 4080-2 and the fourth address line 4095-2; the sixth electrode 4030f-2 is perpendicular to the third address line 4080-2 and parallel to the fourth address line 4095-2;

a fifth isolation structure; the fifth isolation structures extend along the second direction, and are arranged in parallel and alternately with the stacked third address lines 4080-2, fourth electrodes 4030d-2, third functional elements 4091-2 and fifth electrodes 4030 e-2;

a sixth isolation structure; the sixth isolation structures extend along the first direction and are arranged in parallel with the fourth functional elements 4093-2 in an alternating manner;

a seventh isolation structure; the seventh isolation structure penetrates through the sixth isolation structure and is arranged in parallel with the stacked fourth electrode 4030d-2, the stacked third functional element 4091-2 and the stacked fifth electrode 4030e-2 in an alternating manner;

an eighth isolation structure; wherein the eighth isolation structures extend along the first direction and are arranged alternately in parallel with the sixth electrodes 4030f-2 and the fourth address lines 4095-2.

It should be noted that only the case where the fourth functional component includes two sub-functional components is shown in fig. 7, that is, the fourth functional component 4093-2 includes a third sub-functional component 4093a-2 and a fourth sub-functional component 4093b-2, and it is understood that the third sub-functional component 4093a-2 and the fourth sub-functional component 4093b-2 can be understood by referring to the aforementioned first sub-functional component 4060a-2 and second sub-functional component 4060 b-2. In a not shown example, said fourth functional element 4093-2 may also comprise the case of an integral functional element, in which case reference may be made to fig. 5a and 5 b.

In some embodiments, referring to fig. 8, the phase change memory further includes:

the second address line 4070-2 is sequentially stacked from bottom to top with a second phase change memory unit 4000b and a fourth address line 4095-2; wherein the fourth address line 4095-2 and the second address line 4070-2 are parallel to the same plane and perpendicular to each other; the second phase change memory cell 4000b comprises a fourth electrode 4030d-2, a third functional element 4091-2, a fifth electrode 4030e-2, a fourth functional element 4093-2 and a sixth electrode 4030f-2 which are sequentially stacked from bottom to top; the fourth electrode 4030d-2, the third functional element 4091-2 and the fifth electrode 4030e-2 are all perpendicular to the second address line 4070-2 and the fourth address line 4095-2; the fourth functional element 4093-2 is at least partially orthogonal to both the second address line 4070-2 and the fourth address line 4095-2; the sixth electrode 4030f-2 is perpendicular to the second address line 4070-2 and parallel to the fourth address line 4095-2;

a ninth isolation structure; the ninth isolation structures extend along the second direction, and are arranged in parallel with the stacked third electrodes 4030c-2, second address lines 4070-2, fourth electrodes 4030d-2, third functional elements 4091-2 and fifth electrodes 4030e-2 in an alternating manner;

a tenth isolation structure; the tenth isolation structure extends along the first direction and is arranged in parallel with the fourth functional element 4093-2 in an alternating manner;

an eleventh isolation structure; the eleventh isolation structures penetrate through the tenth isolation structures and are arranged in parallel with the fourth electrodes 4030d-2, the third functional elements 4091-2 and the fifth electrodes 4030e-2 in an alternating manner.

It should be noted that only the case where the fourth functional component includes two sub-functional components is shown in fig. 8, that is, the fourth functional component 4093-2 includes a third sub-functional component 4093a-2 and a fourth sub-functional component 4093b-2, and it is understood that the third sub-functional component 4093a-2 and the fourth sub-functional component 4093b-2 can be understood by referring to the aforementioned first sub-functional component 4060a-2 and second sub-functional component 4060 b-2. In a not shown example, said fourth functional element 4093-2 may also comprise the case of an integral functional element, in which case reference may be made to fig. 5a and 5 b.

In some embodiments, the first functional element 4040-2 comprises a first gating element, and the heating or quenching of the first phase change memory element by the electrode is achieved by conduction of the first gating element to achieve switching between the crystalline and amorphous states of the first phase change memory element; the second functional element 4060-2 comprises the first phase change memory element, and the storage of data is achieved by switching between the crystalline and amorphous states of the first phase change memory element.

Here, the width of the first gating element in the first direction is greater than the width of the first sub-functional element 4040a-2 in the first phase change memory element in the first direction.

In practice, the second functional component 4060-2 comprises the first sub-functional component 4060a-2 and the second sub-functional component 4060b-2, and it is the first sub-functional component 4060a-2 that functions to switch between the crystalline state and the amorphous state.

The details of the phase change memory described above are described in detail in the corresponding method, and are not described herein again.

In the embodiments provided in the present disclosure, it should be understood that the disclosed products and methods may be implemented in other ways. The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A method for manufacturing a phase change memory is characterized by comprising the following steps:

removing the first sacrificial block to form a first groove;

forming a second functional layer in the first trench;

2. The method of claim 1, further comprising:

3. The method of claim 2, further comprising:

the removing the first sacrificial block forms a first trench, comprising:

the forming a second functional layer in the first trench includes:

forming a second functional layer in the first trench and the second trench.

4. The method of claim 3, wherein forming a third isolation structure through the first sacrificial strip and the second sacrificial layer comprises:

5. The method of claim 4, wherein forming a second isolation structure through the first sacrificial strip, the second sacrificial layer, the second electrode strip, the first functional strip, and the first electrode strip comprises:

6. A method according to claim 2 or 3, characterized in that the method further comprises:

7. The method of claim 6, further comprising:

removing the third sacrificial block to form a fifth groove;

forming a fourth functional layer in the fifth trench;

8. A method according to claim 2 or 3, characterized in that the method further comprises:

removing the third sacrificial block to form a fifth groove;

forming a fourth functional layer in the fifth trench;

9. The method according to claim 1 or 3,

10. The method of claim 1 or 3, wherein the removing the first sacrificial block comprises:

and removing the first sacrificial block by adopting a wet etching process.

11. A phase change memory, comprising:

12. The phase change memory of claim 11, further comprising:

13. The phase change memory according to claim 11, wherein the second functional element includes a first sub-functional element and a second sub-functional element which are stacked from bottom to top; wherein,

14. The phase change memory according to claim 12 or 13, further comprising:

15. The phase change memory of claim 14, further comprising:

16. The phase change memory according to claim 12 or 13, further comprising:

an eleventh isolation structure; the eleventh isolation structure penetrates through the tenth isolation structure and is arranged in parallel with the fourth electrode layer, the third functional element and the fifth electrode in an alternating mode.

17. The phase change memory according to claim 11, wherein the first functional element comprises a first gate element, and the heating or quenching of the first phase change memory element by the electrode is realized by the conduction of the first gate element to realize the switching between the crystalline state and the amorphous state of the first phase change memory element; the second functional element includes the first phase change memory element, and data storage is realized by switching between a crystalline state and an amorphous state of the first phase change memory element.