CN112018239A - Phase change memory and manufacturing method thereof - Google Patents

Phase change memory and manufacturing method thereof Download PDF

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CN112018239A
CN112018239A CN202011159709.8A CN202011159709A CN112018239A CN 112018239 A CN112018239 A CN 112018239A CN 202011159709 A CN202011159709 A CN 202011159709A CN 112018239 A CN112018239 A CN 112018239A
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layer
phase change
change memory
conductive
electrode layer
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CN112018239B (en
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刘峻
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Yangtze River Advanced Storage Industry Innovation Center Co Ltd
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Yangtze River Advanced Storage Industry Innovation Center Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices

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  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

The embodiment of the disclosure discloses a phase change memory and a manufacturing method of the phase change memory, wherein the phase change memory comprises: the phase change memory array comprises a first conductive line, a phase change memory array and a second conductive line which are sequentially stacked from bottom to top; wherein the first and second conductive lines are parallel to the same plane and perpendicular to each other; the phase change memory array includes: a plurality of phase change memory cells arranged in parallel; the phase change memory cell includes: the phase change memory comprises a first electrode layer, a gating layer, a second electrode layer, a phase change memory layer, a third electrode layer and a conductive stop layer which are sequentially stacked from bottom to top; wherein the phase change memory cell is perpendicular to the first and second conductive lines, and the hardness of the stop layer is greater than the hardness of the third electrode layer.

Description

Phase change memory and manufacturing method thereof
Technical Field
The embodiment of the disclosure relates to the technical field of semiconductors, and in particular relates to a phase change memory and a manufacturing method of the phase change memory.
Background
The basic principle of the phase change memory is that an electric pulse signal acts on a memory cell of a device to enable the phase change material to generate reversible phase change between an amorphous state and a crystalline state, and the writing, erasing and reading operations of information can be realized by distinguishing high resistance in the amorphous state from low resistance in the crystalline state. As a new non-volatile memory device, the phase change memory has great advantages in many aspects such as read-write speed, read-write times, data retention time, cell area, multi-value implementation, and the like. Therefore, how to increase the manufacturing yield of the phase change memory is a problem to be solved.
Disclosure of Invention
In view of the above, the present disclosure provides a phase change memory and a method for manufacturing the same.
According to a first aspect of embodiments of the present disclosure, there is provided a phase change memory, including:
the phase change memory array comprises a first conductive line, a phase change memory array and a second conductive line which are sequentially stacked from bottom to top; wherein the first and second conductive lines are parallel to the same plane and perpendicular to each other;
the phase change memory array includes: a plurality of phase change memory cells arranged in parallel; the phase change memory cell includes: the phase change memory comprises a first electrode layer, a gating layer, a second electrode layer, a phase change memory layer, a third electrode layer and a conductive stop layer which are sequentially stacked from bottom to top;
wherein the phase change memory cell is perpendicular to the first and second conductive lines, and the hardness of the stop layer is greater than the hardness of the third electrode layer.
In some embodiments, a constituent material of the stop layer is the same as a constituent material of the second conductive line.
In some embodiments, the phase change memory further comprises:
the first isolation structure is extended along a first direction and used for electrically isolating two adjacent phase change memory units which are arranged in parallel along a second direction in the phase change memory array; wherein the second direction is perpendicular to the first direction.
In some embodiments, the phase change memory further comprises:
a plurality of second isolation structures extending along the second direction, for electrically isolating two adjacent phase change memory cells arranged in parallel along the first direction in the phase change memory array; wherein the second isolation structure perpendicularly intersects the first isolation structure.
In some embodiments, the phase change memory includes:
at least two phase change memory arrays arranged in a stacked manner in a direction perpendicular to the substrate; wherein two adjacent phase change memory arrays share the first conductive line or the second conductive line.
In some embodiments, when the two adjacent phase change memory arrays share the first conductive line, the phase change memory array located below the first conductive line includes:
a second third electrode layer and a second conductive stop layer; wherein the second conductive stop layer is located between the first conductive line and the second third electrode layer, and the second conductive stop layer is made of the same material as the first conductive line.
According to a second aspect of the embodiments of the present disclosure, there is provided a method for manufacturing a phase change memory, including:
forming a first electrode layer, a gating layer, a second electrode layer, a phase change storage layer, a third electrode layer, a conductive stop layer and a first mask layer which are sequentially stacked from bottom to top on the surface of the first conductive layer; wherein the hardness of the stop layer is greater than the hardness of the third electrode layer;
forming a first preset pattern in the first mask layer to expose a partial area of the stop layer;
forming a first isolation structure penetrating through the stop layer, the third electrode layer, the phase change memory layer, the second electrode layer, the gate layer, the first electrode layer and the first conductive layer based on the first preset pattern;
after the first isolation structure is formed, removing the first mask layer until the stop layer is exposed;
after removing the first mask layer, forming a second conducting layer covering the first isolation structure and the stop layer; wherein the second conductive layer and the first conductive layer are parallel to the same plane and perpendicular to each other.
In some embodiments, the first isolation structure extends in a first direction, the method further comprising:
forming a second mask layer covering the second conductive layer;
forming a second preset pattern in the second mask layer to expose a partial area of the second conductive layer;
forming a second isolation structure penetrating through the second conductive layer, the stop layer, the third electrode layer, the phase change memory layer, the second electrode layer, the pass layer and the first electrode layer based on the second preset pattern;
wherein the second isolation structure extends along a second direction perpendicular to the first direction, the second isolation structure perpendicularly intersecting the first isolation structure.
In some embodiments, the method further comprises:
after forming the second isolation structure, the second conductive layer is formed as a second conductive line;
removing the second mask layer and exposing the second conductive line;
forming a second first electrode layer, a second gating layer, a second electrode layer, a second phase change storage layer, a second third electrode layer, a second conductive stop layer and a third mask layer which are sequentially stacked from bottom to top on the surface of the second conductive wire;
forming the first preset pattern in the third mask layer to expose a partial area of the second conductive stop layer;
forming a second first isolation structure penetrating through the second conductive stop layer, the second third electrode layer, the second phase change memory layer, the second electrode layer, the second gate layer, and the second first electrode layer based on the first preset pattern in the third mask layer;
after the second first isolation structure is formed, removing the third mask layer until the second conductive stop layer is exposed;
and after removing the third mask layer, forming a second first conductive layer covering the second first isolation structure and the second conductive stop layer.
In some embodiments, the second first isolation structure extends along the first direction, the method further comprising:
forming a fourth mask layer covering the second first conductive layer;
forming a second preset pattern in the fourth mask layer to expose a partial area of the second first conductive layer;
forming a second isolation structure through the second first conductive layer, the second conductive stop layer, the second third electrode layer, the second phase change memory layer, the second electrode layer, the second pass layer, and the second first electrode layer; wherein the second isolation structure extends along the second direction, and the second isolation structure perpendicularly intersects the second first isolation structure.
According to the phase change memory, the conductive stop layer is arranged between the third electrode layer and the first mask layer, and the hardness of the stop layer is greater than that of the third electrode layer, so that the stop layer can play a role in protecting the third electrode layer in the process of removing the first mask layer, the quality of the third electrode layer cannot be affected, the quality of the formed phase change memory is guaranteed to be good, and the yield of the phase change memory is improved.
In addition, compared with the arrangement of an insulating stop layer, the stop layer arranged in the method is conductive, so that the stop layer does not need to be removed after the first mask layer is removed, the process steps are simplified, the third electrode layer can be electrically contacted with the second conductive wire through the conductive stop layer, and the normal execution of the function of the phase change memory is ensured.
Drawings
FIG. 1a to FIG. 1c are schematic views illustrating a manufacturing process of a phase change memory;
FIG. 2 is a flow chart illustrating a method of fabricating a phase change memory according to an exemplary embodiment;
FIGS. 3 a-3 k are schematic diagrams illustrating a method of fabricating a phase change memory according to an exemplary embodiment;
FIG. 4 is a schematic diagram illustrating a phase change memory in accordance with an exemplary embodiment;
FIG. 5 is a schematic diagram illustrating a phase change memory in accordance with an exemplary embodiment.
Detailed Description
The technical solutions of the present disclosure will be further explained in detail with reference to the drawings and examples. While exemplary implementations of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The present invention is more particularly described in the following paragraphs with reference to the accompanying drawings by way of example. Advantages and features of the present disclosure will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present disclosure.
It is to be understood that the meaning of "on … …," "over … …," and "over … …" in this disclosure should be read in the broadest manner such that "on … …" not only means that it is "on" something without intervening features or layers therebetween (i.e., directly on something), but also includes the meaning of being "on" something with intervening features or layers therebetween.
In the disclosed embodiment, the term "a is connected to B" includes A, B where a is connected to B in contact with each other, or A, B where a is connected to B in a non-contact manner with other components interposed between the two.
In the embodiments of the present disclosure, the terms "first", "second", and the like are used for distinguishing similar objects, and are not necessarily used for describing a particular order or sequence.
In embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure, or a layer may be between any horizontal pair at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along inclined surfaces. The layer may comprise a plurality of sub-layers. For example, the interconnect layer may include one or more conductors and contact sub-layers (in which interconnect lines and/or via contacts are formed), and one or more dielectric sub-layers.
The technical means described in the embodiments of the present invention may be arbitrarily combined without conflict.
Fig. 1a to 1c are schematic views illustrating a manufacturing process of a Phase Change Memory (PCM). As shown in fig. 1a to 1c, the manufacturing process includes the following steps:
the method comprises the following steps: as shown in fig. 1a, a first conductive layer 2100, an electrode layer 2210, a gate layer 2220, an electrode layer 2230, a phase-change memory layer 2240, an electrode layer 2250, and an etching mask layer (hard mask) 2300 are formed on a surface of a substrate 2001 in this order;
step two: as shown in fig. 1b, an insulating isolation structure 2400 is formed through the etch mask layer 2300, the electrode layer 2250, the phase change memory layer 2240, the electrode layer 2230, the gate layer 2220, the electrode layer 2210 and the first conductive layer 2100. The insulating isolation structure 2400 includes a blocking layer 2410 and a filling layer 2420, the composition material of the blocking layer 2410 may include an insulating nitride, and the filling layer 2420 may include an oxide.
During the formation of the isolation structure 2400, the composition material of the blocking layer 2410 and the composition material of the filling layer 2420 may cover the upper surface of the etching mask layer 2300.
Step three: with reference to fig. 1b and fig. 1c, the structure shown in fig. 1b is planarized by a Chemical Mechanical Polishing (CMP) process to remove the composition material of the blocking layer 2410 and the composition material of the filling layer 2420 covering the upper surface of the etching mask layer 2300 and to etch the mask layer 2300 until the electrode layer 2250 is exposed.
It should be noted that, in general, the electrode layer 2250 is made of a relatively soft material with relatively low hardness, so that during the chemical mechanical polishing of the etching mask layer 2300, defects such as scratches (scratch) may be generated on the electrode layer 2250 or particles (particles) may be introduced into the electrode layer 2250, which may damage the quality of the electrode layer 2250, thereby reducing the yield of the phase change memory.
Fig. 2 illustrates a method for manufacturing a phase change memory according to an exemplary embodiment, and fig. 3a to 3e illustrate a manufacturing process of a phase change memory according to an exemplary embodiment. As shown in fig. 2 and fig. 3a to 3e, the method includes the following steps:
s110: referring to fig. 3a, a first electrode layer 1210, a gate layer 1220, a second electrode layer 1230, a phase change memory layer 1240, a third electrode layer 1250, a conductive stop layer 1260 and a first mask layer 1400 are sequentially stacked from bottom to top on the surface of a first conductive layer 1100; wherein the hardness of the stop layer 1260 is greater than the hardness of the third electrode layer 1250;
s120: forming a first predetermined pattern in the first mask layer 1400 to expose a partial region of the stop layer 1260;
s130: referring to fig. 3b to 3d, a first isolation structure 1010 penetrating through the stop layer 1260, the third electrode layer 1250, the phase-change memory layer 1240, the second electrode layer 1230, the gate layer 1220, the first electrode layer 1210, and the first conductive layer 1100 is formed based on the first predetermined pattern;
s140: after the first isolation structure 1010 is formed, the first mask layer 1400 is removed until the stop layer 1260 is exposed, thereby forming the structure shown in fig. 3 e;
s150: after removing the first mask layer 1400, a second conductive layer 1500 covering the first isolation structure 1010 and the stop layer 1260 is formed, as shown in fig. 3 f; the second conductive layer 1500 and the first conductive layer 1100 are parallel to the same plane and perpendicular to each other.
Illustratively, the constituent material of the stop layer 1260 may include a conductive material, such as metallic tungsten.
For example, as shown in fig. 3b and 3e, in S120 and S130, a double patterning process may be performed on the first mask layer 1400, the stop layer 1260, the third electrode layer 1250, the phase change memory layer 1240, the second electrode layer 1230, the gate layer 1220, and the first electrode layer 1210 to form a trench, and then the trench is filled with a dielectric material to form the first isolation structure 1010.
Specifically, referring to fig. 3b, a plurality of first trenches 1011 are formed to penetrate the first mask layer 1400, the stop layer 1260, the third electrode layer 1250 and the phase change memory layer 1240 in a direction parallel to the z-axis; wherein the bottom of the first trench 1011 exposes the second electrode layer 1230.
Referring to fig. 3c, a first insulating layer 1012 covering the first trench 1011 is formed by Chemical Vapor Deposition (CVD) and a second insulating layer 1013 covering the first insulating layer 1012 is formed based on the profile of the first trench 1011; the structure shown in fig. 3c is planarized to remove the constituent material of the second insulating layer 1013 covering the top of the first mask layer 1400.
It is understood that while the constituent material of the first insulating layer is deposited into the first trench 1011, a portion of the constituent material of the first insulating layer is deposited on top of the first mask layer 1400, thereby covering the first mask layer 1400. Similarly, when forming the second insulating layer 1013, a portion of the constituent material of the second insulating layer 1013 is deposited on top of the first mask layer 1400. Thus, by planarizing the structure shown in fig. 3c, the constituent material of the second insulating layer 1013 covering the top of the first mask layer 1400 is removed.
After removing the constituent material of the second insulating layer 1013 covering the top of the first mask layer 1400 until the constituent material of the first insulating layer 1012 covering the top of the first mask layer 1400 is exposed, the constituent material of the first insulating layer 1012 covering the top of the first mask layer 1400 may also be removed by a planarization process until the first mask layer 1400 is exposed.
The constituent material of the first insulating layer 1012 may include a nitride, such as a nitride. The constituent material of the second insulating layer 1013 may include an oxide such as silicon oxide or the like. The first and second insulating layers 1012 and 1013 encapsulate the covered third electrode layer 1250 and the phase change memory layer 1240.
Referring to fig. 3d, a second trench penetrating the first and second insulating layers 1012 and 1013 covering the bottom of the first trench 1011, and the second electrode layer 1230, the gate layer 1220, and the first electrode layer 1210 at the bottom of the first trench 1011 is formed along a direction parallel to the z-axis based on the opening of the first trench 1011 after the first and second insulating layers 1012 and 1013 are formed; forming a third insulating layer 1014 covering the second insulating layer 1013, the second trench sidewalls, and the second trench bottom; the first trench and the second trench in which the third insulating layer 1014 is formed are filled with a first filling material to form a first thermal insulation structure 1015.
Illustratively, the constituent material of the third insulating layer 1014 may include a nitride, such as silicon nitride. The composition material of the first thermal isolation structure 1015 may include an oxide, such as silicon oxide. I.e., the first filler material may comprise an oxide.
The first trench and the second trench in which the third insulating layer 1014 is formed may be filled by atomic layer vapor deposition (ALD), spin-on dielectric (SOD), or chemical vapor deposition to form the first thermal isolation structure 1015.
The thermal conductivity of the first filling material is low, that is, the thermal conductivity of the first thermal insulation structure 1015 is low, so that the heat transfer between adjacent memory cells can be reduced, further, the crosstalk caused by the heat transfer is reduced, and the reliability of the phase change memory is ensured to be good.
It will be appreciated that the top of the second groove communicates with the bottom of the first groove 1011.
A third insulating layer 1014 covering the sidewalls of the second trench, and a first thermal isolation structure 1015 for electrically isolating the stop layer 1260, the third electrode layer 1250, the phase change memory layer 1240, the second electrode layer 1230, the gate layer 1220, the first electrode layer 1210, and the first conductive line 1100 in the adjacent phase change memory cell in the x direction.
It is to be understood that the first isolation structure is formed to divide the first conductive layer into the first conductive lines, and therefore, the same reference numerals are used to designate the first conductive layer and the first conductive lines in the present disclosure.
Note that the first isolation structure 1010 includes: a first insulating layer 1012, a second insulating layer 1013, a third insulating layer 1014, and a first insulating structure 1015.
Generally, a phase change memory includes a plurality of first isolation structures. Each first isolation structure extends in a direction parallel to the y-axis. And, in the direction parallel to the x-axis, the first isolation structures are alternately arranged in parallel with the memory cells of the phase change memory.
In S140, a planarization process may be performed by a chemical mechanical polishing process to remove the first mask layer 1400 and expose the stop layer 1260.
It is understood that, referring to fig. 3d, during the formation of the third insulating layer 1014, a portion of the composition material of the third insulating layer 1014 may cover the first mask layer 1400. Also, when the first and second trenches in which the third insulating layer 1014 is formed are filled with a filling material, a portion of the filling material covers over the first mask layer 1400. Accordingly, in the planarization process, the constituent material of the third insulating layer 1014 covering the first mask layer 1400 and the constituent material of the first thermal isolation structure 1015 are removed.
It is noted that, referring to fig. 3f, since the stop layer 1260 located between the second conductive layer 1500 and the third electrode layer 1250 is conductive, the second conductive layer 1500 can be electrically connected to the third electrode layer 1250 through the stop layer 126.
In the embodiment of the disclosure, the conductive stop layer 1260 is disposed between the third electrode layer 1250 and the first mask layer 1400, and since the hardness of the stop layer 1260 is greater than that of the third electrode layer 1250, the stop layer 1260 can play a role in protecting the third electrode layer 1250 in the process of removing the first mask layer 1400, so that the quality of the third electrode layer 1250 is not affected, which is beneficial to ensuring that the quality of the formed phase change memory is good, and the yield of the phase change memory is improved.
Moreover, since the stop layer 1260 conducts electricity, after the first mask layer 1400 is removed, the second conductive layer 1500 covering the stop layer 1260 can be directly formed without removing the stop layer 1260, and it can still be ensured that the second conductive layer 1500 can form an electrical connection with the third electrode layer 1250 through the conductive stop layer 1260, so that the function of the phase change memory can be normally executed, and the process is simple.
In some embodiments, the first isolation structure extends in a first direction, the method further comprising:
referring to fig. 3f, a second mask layer 1410 is formed to cover the second conductive layer 1500;
forming a second preset pattern in the second mask layer to expose a partial region of the second conductive layer 1500;
referring to fig. 3g to 3i, a second isolation structure penetrating through the second conductive layer 1500, the stop layer 1260, the third electrode layer 1250, the phase-change memory layer 1240, the second electrode layer 1230, the gate layer 1220 and the first electrode layer 1210 is formed based on a second predetermined pattern;
referring to fig. 3i, the second isolation structure extends along a second direction perpendicular to the first direction, and the second isolation structure perpendicularly intersects the first isolation structure.
The first direction may be parallel to the y-axis direction and the second direction may be parallel to the x-axis direction. The first direction is perpendicular to the plane zox.
The second mask layer 1410 may be formed of the same material as the first mask layer 1400. For example, the second mask layer 1410 may include silicon nitride or the like.
Figure 3g shows a cross-sectional view of the AA' position in the yoz plane in figure 3 f. It will be appreciated that the yoz plane is parallel to the y-axis and z-axis, and perpendicular to the x-axis.
Referring to fig. 3h, a plurality of third trenches 1016 are formed through the second mask layer 1410, the second conductive line 1500, the stop layer 1260, the third electrode layer 1250, and the phase-change memory layer 1240 in a direction parallel to the z-axis; wherein the bottom of the third trench 1016 exposes the second electrode layer 1230.
As shown in fig. 3h, a plurality of third trenches 1016 are arranged side by side in a direction parallel to the y-axis, each third trench 1016 extending in a direction parallel to the x-axis.
Referring to fig. 3i, a fourth insulating layer 1022 is formed to cover the third trench 1016, and a fifth insulating layer 1023 is formed to cover the fourth insulating layer 1022; forming a fourth trench penetrating the fifth and fourth insulating layers 1023 and 1022 covering the bottom of the third trench 1012, and the second electrode layer 1230, the gate layer 1220, and the first electrode layer 1210 at the bottom of the third trench 1016 based on the opening of the third trench 1016 forming the fourth and fifth insulating layers 1022 and 1023 in the direction parallel to the z-axis; wherein the top of the fourth trench is in communication with the bottom of the third trench 1016, the bottom of the fourth trench exposing the first conductive line 1100; forming a sixth insulating layer 1024 covering the fifth insulating layer 1023, the sidewalls of the fourth trench, and the bottom of the fourth trench; the third trench 1016 and the fourth trench, in which the sixth insulating layer 1024 is formed, are filled with a second filling material, forming a second thermal insulation structure 1025.
A sixth insulating layer 1024 covering the sidewalls of the fourth trench, and a second thermal isolation structure 1025 for electrically isolating the second electrode layer 1230, the gate layer 1220, and the first electrode layer 1210 in the adjacent memory cell in the y-direction.
The composition materials of the fourth insulating layer 1022 and the sixth insulating layer 1024 may be the same as those of the first insulating layer 1012 and the third insulating layer 1014. For example, the constituent material of the fourth insulating layer 1022 and the sixth insulating layer 1024 may include silicon nitride.
For example, the second thermal isolation structure 1025 may be formed in the same manner as the first thermal isolation structure 1015. Further, the composition material of the second thermal insulation structure 1025 may be the same as the composition material of the first thermal insulation structure 1015, for example, the composition material of the second thermal insulation structure 1025 may include silicon oxide or the like. I.e., the second filler material may comprise silicon oxide or the like.
It can be understood that the thermal conductivity of the second filling material is low, that is, the thermal conductivity of the second thermal isolation structure 1025 is low, so that the heat transfer between adjacent memory cells can be reduced, further, the crosstalk caused by the heat transfer is reduced, and the reliability of the phase change memory is ensured to be good.
It should be noted that the second isolation structure includes: a fourth insulating layer 1022, a fifth insulating layer 1023, a sixth insulating layer 1024, and a second thermal isolation structure 1025. The second isolation structures extend in a direction parallel to the x-axis, and are alternately arranged in parallel with the memory cells in a direction parallel to the y-axis.
The second isolation structure is formed to divide the second conductive layer into second conductive lines, and therefore, the same reference numerals are used in the present disclosure to denote the second conductive layer and the second conductive lines.
It will be appreciated that the first and second isolation structures, which are perpendicular to each other, serve to electrically isolate adjacent memory cells.
In some embodiments, the phase change memory includes at least two phase change memory arrays stacked in a direction perpendicular to the substrate, each phase change memory array including a plurality of memory cells arranged in parallel in the direction parallel to the substrate, and the method further includes:
referring to fig. 3j, after forming the second isolation structure, the second conductive layer forms a second conductive line; removing the second mask layer to expose the second conductive line 1500;
referring to fig. 3k, a second first electrode layer 1210b, a second gate layer 1220b, a second electrode layer 1230b, a second phase-change memory layer 1240b, a second third electrode layer 1250b, a second conductive stop layer 1260b, and a third mask layer are sequentially stacked from bottom to top on the surface of the second conductive line 1500;
forming a first predetermined pattern in the third mask layer to expose a partial region of the second conductive stop layer 1260 b;
forming a second first isolation structure penetrating the second conductive stop layer 1260b, the second third electrode layer 1250b, the second phase change memory layer 1240b, the second electrode layer 1230b, the second gate layer 1220b, and the second first electrode layer 1210b based on the first predetermined pattern in the third mask layer;
after the second first isolation structure is formed, removing the third mask layer until the second conductive stop layer 1260b is exposed;
after removing the third mask layer, a second first conductive layer 1100b is formed covering the second first isolation structure and the second conductive stop layer 1260 b.
It is understood that the first memory array includes memory cell 1200a and the second memory array includes memory cell 1200b, and the first memory array and the second memory array are stacked in a z-axis direction perpendicular to substrate 1001.
In forming the memory cell 1200b, the second conductive line 1500 is in direct contact with the memory cell 1200b of the upper memory array, and the memory cell 1200a and the memory cell 1200b share the same second conductive line 1500.
It is understood that the first conductive line 1100b of the upper memory array is located above the memory cell 1200b, and the first conductive line 1100a of the lower memory array is located below the memory cell 1200 a.
Illustratively, the memory 1000 may include a three-dimensional phase change memory. The first and second conductive lines 1100a and 1100b may be word lines (word lines) of a three-dimensional phase change memory, and the second conductive line 1500 may be bit lines (bit lines) of the three-dimensional phase change memory. Alternatively, the first and second conductive lines 1100a and 1100b may be bit lines and 1500 may be word lines of a three-dimensional phase change memory.
In some embodiments, the second first isolation structure extends in a first direction, the method further comprising:
forming a fourth mask layer covering the second first conductive layer;
forming a second preset pattern in the fourth mask layer to expose a partial area of the second first conductive layer;
forming a second isolation structure through the second first conductive layer, the second conductive stop layer 1260b, the second third electrode layer, the second phase change memory layer, the second electrode layer, the second gate layer, and the second first electrode layer; and the second isolation structure extends along the second direction, and the second isolation structure is vertically intersected with the second first isolation structure.
Fig. 4 is a schematic diagram illustrating a phase change memory 1000 in accordance with an exemplary embodiment. The phase change memory 1000 may be fabricated using the methods provided by the embodiments of the present disclosure. Referring to fig. 4, the phase change memory 1000 includes:
a first conductive line 1100, a phase change memory array and a second conductive line 1500 sequentially stacked from bottom to top; wherein the first conductive line 1100 and the second conductive line 1500 are parallel to the same plane and perpendicular to each other;
the phase change memory array includes: a plurality of phase change memory cells 1200 arranged in parallel; phase change memory cell 1200 includes: a first electrode layer 1210, a gate layer 1220, a second electrode layer 1230, a phase change memory layer 1240, a third electrode layer 1250 and a conductive stop layer 1260 which are sequentially stacked from bottom to top;
the phase-change memory cell 1200 is perpendicular to the first conductive line 1100 and the second conductive line 1500, and the hardness of the stop layer 1260 is greater than the hardness of the third electrode layer 1250.
The constituent material of the first conductive line 1100 includes a conductive material. The conductive material includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), or polysilicon, etc.
The constituent materials of the first electrode layer 1210, the second electrode layer 1230, and the third electrode layer 1250 may include: amorphous carbon, such as alpha phase carbon. The first electrode layer 1210, the second electrode layer 1230, and the third electrode layer 1250 are the same in composition material. A first electrode layer 1210, a second electrode layer 1230 and a third electrode layer 1250 for conducting electrical signals.
It is emphasized that the first plane in which the first conductive line 1100 is disposed and the second plane in which the second conductive line 1500 is disposed are parallel, and the first plane and the second plane do not overlap. The phase change memory cell 1200 is located between a first plane and a second plane, and the phase change memory cell 1200 is perpendicular to both the first plane and the second plane.
The material of the gate layer 1220 may include: threshold selection switch (OTS) material, e.g. ZnaTeb、GeaTeb、NbaObOr SiaAsbTecAnd the like.
The composition materials of the phase change memory layer 1240 may include: chalcogenide-based alloys. For example, a GST (Ge-Sb-Te) alloy. The constituent material of the phase change memory layer 1240 may also include any other suitable phase change material.
By manufacturing the phase change memory 1000 by using the method provided by the embodiment of the disclosure, since the hardness of the stop layer 1260 is greater than that of the third electrode layer 1250, the stop layer 1260 can play a role in protecting the third electrode layer 1250 in the process of removing the first mask layer 1400, so that the quality of the third electrode layer 1250 is not affected, which is beneficial to ensuring that the quality of the formed phase change memory is good, and the yield of the phase change memory is improved.
In addition, the embodiment of the disclosure forms the conductive stop layer 1260, so that the second conductive line 1500 can still be electrically connected to the third electrode layer 1250 through the conductive stop layer 1260, the function of the phase change memory can be normally performed, and the process is simple.
In some embodiments, as shown with reference to fig. 3d, the phase change memory 1000 further includes:
a first isolation structure extending along a first direction for electrically isolating two adjacent phase change memory cells 1200 arranged in parallel along a second direction in the phase change memory array; wherein the second direction is perpendicular to the first direction.
In some embodiments, the stop layer 1260 is the same as the second conductive line.
Illustratively, the constituent materials of the stop layer 1260 may include: a metal, such as metallic tungsten.
In the embodiment of the disclosure, since the stop layer and the second conductive line are made of the same material, when the stop layer is in contact with the second conductive line, the contact resistance between the stop layer and the second conductive line can be reduced, thereby improving the electrical performance of the phase change memory 1000.
In some embodiments, referring to fig. 4, the phase change memory further includes:
a plurality of second isolation structures extending along the second direction, configured to electrically isolate two adjacent phase change memory cells 1200 in the phase change memory array, which are juxtaposed on the surface of the substrate 1001 along the first direction; wherein the second isolation structure is vertically intersected with the first isolation structure.
Illustratively, a substrate 1001 for carrying a first conductive line 1100, a phase change memory array, and a second conductive line 1500; wherein the first and second directions are parallel to the substrate 1001.
The substrate represents the material onto which subsequent layers of material are added. The substrate may comprise a semiconductor material such as silicon, germanium, or gallium arsenide, among others.
And a second isolation structure for electrically isolating the memory cells 1200 adjacently arranged in a direction parallel to the y-axis. And a second isolation structure for electrically isolating the second conductive lines 1500 arranged adjacently in a direction parallel to the y-axis.
It is noted that a larger amount of heat is generated during the phase change of the phase change memory layer 1240, and therefore, the second isolation structure is also used to thermally isolate two memory cells adjacently arranged in a direction parallel to the y-axis, so as to reduce the thermal crosstalk between the adjacent memory cells 1200.
The second isolation structure has a cross-contact position with the first isolation structure. The second isolation structure and the first isolation structure may include the same constituent material. The constituent materials of the second isolation structure and the first isolation structure may include a material having a relatively low thermal conductivity.
In some embodiments, referring to fig. 3j, the phase change memory layer 1240 has a first width and the second electrode layer 1230 has a second width along a direction parallel to the extension direction of the first conductive line 1100; wherein the second width is greater than the first width;
and/or the presence of a gas in the gas,
referring to fig. 3f, the phase change memory layer 1240 has a third width and the second electrode layer 1230 has a fourth width along the extending direction parallel to the second conductive line 1500; wherein the fourth width is greater than the third width.
Illustratively, the extending direction of the first conductive line 1100 is parallel to the first direction, and the extending direction of the second conductive line 1500 is parallel to the second direction.
The bottom of the phase change memory layer 1240 is in contact with the top of the second electrode layer 1230. It is understood that, for each phase change memory cell 1200, the bottom area of the phase change memory layer 1240 is smaller than the top area of the second electrode layer 1230 in a direction parallel to the substrate surface.
For the phase change memory layer 1240 with the same thickness, compared with the bottom area of the phase change memory layer 1240 being greater than or equal to the top area of the second electrode layer 1230, the phase change memory unit 1200 provided in the embodiment of the disclosure reduces the bottom area of the phase change memory layer 1240, so that the volume of the phase change memory layer 1240 is reduced, and further, the energy required for causing the phase change memory layer 1240 to undergo a phase change is reduced, which is beneficial to reducing the power consumption of the phase change memory.
In some embodiments, a phase change memory includes:
at least two phase change memory arrays stacked in a direction perpendicular to the substrate 1001; wherein two adjacent phase change memory arrays share the first conductive line or the second conductive line.
In a direction parallel to the substrate surface, each phase change memory array includes: a plurality of phase change memory cells 1200 arranged side-by-side in a direction parallel to the x-axis, and a plurality of phase change memory cells 1200 arranged side-by-side in a direction parallel to the y-axis.
Illustratively, when the phase change memory 1000 includes M phase change memory arrays arranged in a stack, where M is an integer greater than 2, the first conductive line 1100 is located between the 2N-th phase change memory array and the 2N + 1-th phase change memory array, and the second conductive line 1500 is located between the 2N-1-th phase change memory array and the 2N-th phase change memory array, where N is a positive integer, and 2N +1 is less than or equal to M.
Referring to fig. 5, the phase change memory 1000 includes, in order from bottom to top: a substrate 1001, a first conductive line 1100a, a first phase change memory array, a second conductive line 1500, a second phase change memory array, and a second first conductive line 1100 b. The first phase change memory array includes a plurality of phase change memory cells 1200a juxtaposed parallel to substrate 1001 and the second phase change memory array includes a plurality of phase change memory cells 1200b juxtaposed parallel to substrate 1001.
It is understood that phase change memory cell 1200a and phase change memory cell 1200b are identical in structure.
Referring to fig. 5, phase change memory cell 1200a and phase change memory cell 1200b each include: the memory cell comprises a first electrode layer 1210, a gate layer 1220, a second electrode layer 1230, a phase change memory layer 1240, a third electrode layer 1250 and a conductive stop layer 1260 which are sequentially stacked from bottom to top. The second conductive line 1500 is electrically connected to the third electrode layer 1250 through the stop layer 1260.
It is to be noted that the first electrode layer 1210a, the gate layer 1220a, the second electrode layer 1230a, the phase change memory layer 1240a, the third electrode layer 1250a and the conductive stop layer 1260a included in the phase change memory cell 1200a respectively correspond to the first electrode layer 1210b, the gate layer 1220b, the second electrode layer 1230b, the phase change memory layer 1240b, the third electrode layer 1250b and the conductive stop layer 1260b included in the phase change memory cell 1200b, and have the same structure.
In some embodiments, referring to fig. 5, when two adjacent memory arrays disposed in a stacked configuration share the first conductive line 1100b, the phase change memory array located under the first conductive line 1100b includes: a second third electrode layer 1250b and a second conductive stop layer 1260 b;
wherein the second conductive stop layer 1260b is located between the first conductive line 1100b and the second third electrode layer 1250b, and the second conductive stop layer 1260b has the same composition material as the first conductive line 1100 b.
Since the second conductive stop layer 1260b is formed of the same material as the first conductive line 1100b, the contact resistance between the second conductive stop layer 1260b and the first conductive line 1100b can be reduced for the second conductive stop layer 1260b and the first conductive line 1100b, which are in contact with each other, thereby improving the electrical performance of the phase change memory 1000.
In the embodiments provided in the present disclosure, it should be understood that the disclosed apparatus, system, and method may be implemented in other ways. The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (10)

1. A phase change memory, comprising:
the phase change memory array comprises a first conductive line, a phase change memory array and a second conductive line which are sequentially stacked from bottom to top; wherein the first and second conductive lines are parallel to the same plane and perpendicular to each other;
the phase change memory array includes: a plurality of phase change memory cells arranged in parallel; the phase change memory cell includes: the phase change memory comprises a first electrode layer, a gating layer, a second electrode layer, a phase change memory layer, a third electrode layer and a conductive stop layer which are sequentially stacked from bottom to top;
wherein the phase change memory cell is perpendicular to the first and second conductive lines, and the hardness of the stop layer is greater than the hardness of the third electrode layer.
2. The phase change memory of claim 1, wherein a constituent material of the stop layer is the same as a constituent material of the second conductive line.
3. The phase change memory according to claim 1, further comprising:
the first isolation structure is extended along a first direction and used for electrically isolating two adjacent phase change memory units which are arranged in parallel along a second direction in the phase change memory array; wherein the second direction is perpendicular to the first direction.
4. The phase change memory according to claim 3, further comprising:
a plurality of second isolation structures extending along the second direction, for electrically isolating two adjacent phase change memory cells arranged in parallel along the first direction in the phase change memory array; wherein the second isolation structure perpendicularly intersects the first isolation structure.
5. The phase change memory according to claim 4, comprising:
at least two phase change memory arrays arranged in a stacked manner in a direction perpendicular to the substrate; wherein two adjacent phase change memory arrays share the first conductive line or the second conductive line.
6. The phase-change memory of claim 5, wherein when the first conductive line is shared by the two adjacent phase-change memory arrays, the phase-change memory array located below the first conductive line comprises:
a second third electrode layer and a second conductive stop layer; wherein the second conductive stop layer is located between the first conductive line and the second third electrode layer, and the second conductive stop layer is made of the same material as the first conductive line.
7. A method for manufacturing a phase change memory is characterized by comprising the following steps:
forming a first electrode layer, a gating layer, a second electrode layer, a phase change storage layer, a third electrode layer, a conductive stop layer and a first mask layer which are sequentially stacked from bottom to top on the surface of the first conductive layer; wherein the hardness of the stop layer is greater than the hardness of the third electrode layer;
forming a first preset pattern in the first mask layer to expose a partial area of the stop layer;
forming a first isolation structure penetrating through the stop layer, the third electrode layer, the phase change memory layer, the second electrode layer, the gate layer, the first electrode layer and the first conductive layer based on the first preset pattern;
after the first isolation structure is formed, removing the first mask layer until the stop layer is exposed;
after removing the first mask layer, forming a second conducting layer covering the first isolation structure and the stop layer; wherein the second conductive layer and the first conductive layer are parallel to the same plane and perpendicular to each other.
8. The method of claim 7, wherein the first isolation structure extends in a first direction, the method further comprising:
forming a second mask layer covering the second conductive layer;
forming a second preset pattern in the second mask layer to expose a partial area of the second conductive layer;
forming a second isolation structure penetrating through the second conductive layer, the stop layer, the third electrode layer, the phase change memory layer, the second electrode layer, the pass layer and the first electrode layer based on the second preset pattern;
wherein the second isolation structure extends along a second direction perpendicular to the first direction, the second isolation structure perpendicularly intersecting the first isolation structure.
9. The method of claim 8, further comprising:
after forming the second isolation structure, the second conductive layer is formed as a second conductive line;
removing the second mask layer and exposing the second conductive line;
forming a second first electrode layer, a second gating layer, a second electrode layer, a second phase change storage layer, a second third electrode layer, a second conductive stop layer and a third mask layer which are sequentially stacked from bottom to top on the surface of the second conductive wire;
forming the first preset pattern in the third mask layer to expose a partial area of the second conductive stop layer;
forming a second first isolation structure penetrating through the second conductive stop layer, the second third electrode layer, the second phase change memory layer, the second electrode layer, the second gate layer, and the second first electrode layer based on the first preset pattern in the third mask layer;
after the second first isolation structure is formed, removing the third mask layer until the second conductive stop layer is exposed;
and after removing the third mask layer, forming a second first conductive layer covering the second first isolation structure and the second conductive stop layer.
10. The method of claim 9, wherein the second first isolation structure extends along the first direction, the method further comprising:
forming a fourth mask layer covering the second first conductive layer;
forming a second preset pattern in the fourth mask layer to expose a partial area of the second first conductive layer;
forming a second isolation structure through the second first conductive layer, the second conductive stop layer, the second third electrode layer, the second phase change memory layer, the second electrode layer, the second pass layer, and the second first electrode layer; wherein the second isolation structure extends along the second direction, and the second isolation structure perpendicularly intersects the second first isolation structure.
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CN112234141A (en) * 2020-12-11 2021-01-15 长江先进存储产业创新中心有限责任公司 Phase change memory and manufacturing method thereof
CN112768488A (en) * 2021-02-04 2021-05-07 长江先进存储产业创新中心有限责任公司 Phase change memory and manufacturing method thereof
CN112968037A (en) * 2021-03-19 2021-06-15 长江先进存储产业创新中心有限责任公司 Phase change memory and manufacturing method thereof
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112234141A (en) * 2020-12-11 2021-01-15 长江先进存储产业创新中心有限责任公司 Phase change memory and manufacturing method thereof
CN112768488A (en) * 2021-02-04 2021-05-07 长江先进存储产业创新中心有限责任公司 Phase change memory and manufacturing method thereof
CN112768488B (en) * 2021-02-04 2021-11-09 长江先进存储产业创新中心有限责任公司 Phase change memory and manufacturing method thereof
CN112968037A (en) * 2021-03-19 2021-06-15 长江先进存储产业创新中心有限责任公司 Phase change memory and manufacturing method thereof
CN113594201A (en) * 2021-07-07 2021-11-02 长江先进存储产业创新中心有限责任公司 Phase change memory and manufacturing method thereof
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WO2024067048A1 (en) * 2022-09-30 2024-04-04 华为技术有限公司 Three-dimensional memory array, memory and electronic device

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