CN113451357B - Phase change memory - Google Patents
Phase change memory Download PDFInfo
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- CN113451357B CN113451357B CN202110729313.0A CN202110729313A CN113451357B CN 113451357 B CN113451357 B CN 113451357B CN 202110729313 A CN202110729313 A CN 202110729313A CN 113451357 B CN113451357 B CN 113451357B
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
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Abstract
The embodiment of the disclosure discloses a phase change memory. The phase change memory includes: a phase change memory cell on a substrate, comprising: the phase change memory layer and the transistor are arranged in parallel along a first direction; wherein the first direction is parallel to the plane of the substrate; the transistor, comprising: a source electrode, a channel layer and a drain electrode arranged in parallel along the first direction; the grid layer extends along the second direction and wraps the channel layer; the second direction is different from the first direction, and the second direction is parallel to the plane of the substrate; along the first direction, the phase change storage layer and the source electrode are arranged in parallel and electrically connected; or the phase change storage layer and the drain electrode are arranged in parallel and electrically connected.
Description
Technical Field
The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a phase change memory.
Background
Phase Change Memory (PCM) is the mainstream non-volatile Memory of the next generation, and has the advantages of high speed and long service life of Dynamic Random Access Memory (DRAM) and low cost and non-volatility of Flash Memory (Flash Memory). In addition, the method can be used in mobile equipment due to the advantages of low power consumption, high integration and the like.
In the related art, a single planar Transistor and a single phase change memory cell are connected in series, so that a phase change memory having a 1T1R (One Transistor One Resistance) structure can be formed. However, as phase change memory integration and bit density increase, the feature size of phase change memory cells decreases. The planar transistor is difficult to continue shrinking along with the reduction of the characteristic size of the phase change memory unit, and is difficult to provide enough current to drive the phase change material to generate phase change, so that the improvement of the performance of the phase change memory is limited. Therefore, how to improve the performance of the phase change memory while improving the integration level and the bit density of the phase change memory becomes a problem to be solved urgently.
Disclosure of Invention
In view of this, the disclosed embodiments provide a phase change memory, including:
a phase change memory cell on a substrate, comprising: the phase change memory layer and the transistor are arranged in parallel along a first direction; wherein the first direction is parallel to the plane of the substrate;
the transistor, comprising:
a source electrode, a channel layer and a drain electrode arranged in parallel along the first direction;
the grid layer extends along the second direction and wraps the channel layer; the second direction is different from the first direction and is parallel to the plane of the substrate;
in the direction of the said first direction,
the phase change storage layer and the source electrode are arranged in parallel and electrically connected;
or the like, or a combination thereof,
the phase change storage layer and the drain electrode are arranged in parallel and electrically connected.
In some embodiments, the phase change memory further comprises:
a first conductive line juxtaposed with the substrate and the phase change memory cell in a third direction and extending in the first direction; wherein the first conductive line is electrically connected with the gate layer; the third direction is vertical to the plane of the substrate;
a second conductive line juxtaposed with the phase change memory layer and the transistor along the first direction and extending along the second direction; wherein the second conductive line is electrically connected with the phase change memory layer; the second electrically conductive line is electrically insulated from the first electrically conductive line.
In some embodiments, the phase change memory further comprises:
a phase change memory array comprising:
a plurality of the phase change memory cells arranged in parallel along the first direction;
and/or;
a plurality of the phase change memory cells arranged in parallel along the second direction;
and/or;
and the phase change memory cells are arranged in parallel along the third direction.
In some embodiments, when a plurality of the phase change memory cells are juxtaposed in the first direction, the phase change memory further includes a plurality of the second conductive lines juxtaposed in the first direction;
and/or;
when a plurality of the phase change memory cells are juxtaposed along the second direction, the phase change memory further includes a plurality of the first conductive lines juxtaposed along the second direction;
and/or;
when the plurality of phase change memory cells are arranged in parallel along the third direction, the phase change memory further comprises a plurality of second conductive lines arranged in parallel along the third direction.
In some embodiments, the channel layer includes: a plurality of sub-channel layers arranged in parallel along the third direction;
the source electrode includes: a plurality of sub-source electrodes arranged in parallel along the third direction; wherein the sub-source is located at one side of the sub-channel layer;
the drain electrode includes: a plurality of sub-drains arranged in parallel along the third direction; wherein the sub-drain is located at the other side of the sub-channel layer;
the phase change memory layer includes: a plurality of sub phase change memory layers juxtaposed in the third direction; wherein each sub phase change memory layer is electrically connected to each sub source electrode or each sub drain electrode;
the phase change memory further includes: and the gate dielectric layer is positioned between the sub-channel layer and the gate electrode layer.
In some embodiments, the sub-channel layer comprises:
nanoplatelets extending along the first direction; wherein the nanosheets are located between the sub-source and the sub-drain;
or the like, or, alternatively,
a nanowire extending along the first direction; wherein the nanowire is located between the sub-source and the sub-drain.
In some embodiments, the phase change memory further comprises:
the active region is positioned between the substrate and the phase change memory cell and used for providing an electric signal to the phase change memory cell; wherein a top width of the active region is less than a bottom width of the active region.
In some embodiments, the active region, along a cross-sectional shape perpendicular to a plane of the substrate, includes: trapezoidal or trapezoid-like.
In some embodiments, the top width of the active region ranges from: 3nm to 7nm.
In some embodiments, the phase change memory further comprises:
a plurality of the active regions juxtaposed in the second direction;
the insulating isolation structure is positioned between two adjacent active regions; wherein a top width of the isolation structure is greater than a bottom width of the isolation structure.
In the embodiment of the disclosure, the integration of the phase change memory layer and the transistor can be realized by electrically connecting the phase change memory layer to the source electrode or the drain electrode of the transistor. The transistor has the advantages that the contact area of the gate layer and the channel layer can be increased due to the fact that the gate layer is wrapped by the channel layer, the control capacity of the gate layer in the transistor on current can be improved, the transistor can provide enough current to drive the phase change storage layer (namely, the phase change material) to carry out phase change in the phase change memory in the process of storing data based on the phase state of the phase change material, and the performance of the phase change memory is improved.
Furthermore, as the control capability of the grid layer on the current is increased, the phase change storage layer can be driven to generate phase change by a small current, so that the power consumption of the phase change storage is reduced, and the operation speed of the phase change memory is improved.
Drawings
FIG. 1 is a partial schematic diagram illustrating a phase change memory in accordance with an exemplary embodiment;
FIG. 2 is a schematic diagram illustrating the structure of another phase change memory according to an exemplary embodiment;
fig. 3 is a schematic diagram illustrating a structure of yet another phase change memory according to an example embodiment.
Detailed Description
The technical solutions of the present disclosure will be further elaborated below with reference to the drawings and embodiments. While exemplary implementations of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The present disclosure is more particularly described in the following paragraphs with reference to the accompanying drawings by way of example. Advantages and features of the present disclosure will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, and are provided solely for the purpose of facilitating and distinctly claiming the embodiments of the present disclosure.
It is understood that the meaning of "on 8230; \8230on," \8230, on, "\8230, 8230on," \8230, on top of the \8230shouldbe read in the broadest manner so that "on 8230;" \8230, on "not only means that it is" on "something without intervening features or layers therebetween (i.e., directly on something), but also includes the meaning of" on "something with intervening features or layers therebetween.
In the embodiments of the present disclosure, the term "a is connected to B" includes a case where a and B are connected to each other in contact with each other, or a case where a is connected to B in a non-contact manner with other components interposed therebetween.
In the embodiments of the present disclosure, the terms "first", "second", and the like are used for distinguishing similar objects, and are not necessarily used for describing a particular order or sequence.
In embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure, or a layer may be between any horizontal pair at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along inclined surfaces. The layer may comprise a plurality of sub-layers.
The technical means described in the embodiments of the present disclosure may be arbitrarily combined without conflict.
FIG. 1 is a partial schematic diagram illustrating a phase change memory 1000 in accordance with an exemplary embodiment. Referring to fig. 1, a phase change memory 1000 includes:
a first conductive line 1100, a phase change memory cell 1200 and a second conductive line 1300 which are sequentially stacked from bottom to top; wherein the first and second conductive lines 1100 and 1300 are parallel to the same plane and perpendicular to each other, and the phase change memory cell 1200 is perpendicular to both the first and second conductive lines 1100 and 1300;
the phase change memory cell 1200 includes: the first electrode layer 1210a, the gate layer 1220, the second electrode layer 1210b, the phase change memory layer 1230, and the third electrode layer 1210c are sequentially stacked from bottom to top.
In order to improve the integration level and bit density of the phase change memory, in the related art, a phase change memory having a 1S1R (One Selector One Resistance) structure may be formed by embedding the gate layer 1220 in the phase change memory cell 1200, so as to solve the problem of insufficient current driving capability of the planar transistor.
However, when the phase change memory with the 1S1R structure is subjected to a read/write operation, the gate layer 1220 needs to be opened to perform the read/write operation on the phase change memory layer 1230, and the gate layer 1220 connected in series with the phase change memory layer 1230 has a possibility of generating heat and locally crystallizing, which affects the resistance distribution of the phase change memory layer 1230 and reduces the reliability of the phase change memory.
In view of the above, the embodiments of the present disclosure provide a phase change memory.
Fig. 2 is a schematic diagram illustrating the structure of another phase change memory 2000 according to an example embodiment. Referring to fig. 2, the phase change memory 2000 includes:
a phase change memory cell 2300, located on a substrate 2110, comprising: a phase change memory layer 2310 and a transistor 2320 arranged in parallel in a first direction; wherein the first direction is parallel to the plane of the substrate 2110;
a transistor 2320, comprising:
a source 2321, a channel layer 2322, and a drain 2323 arranged in parallel along a first direction;
a gate layer 2324 extending in the second direction and disposed to wrap the channel layer 2322; the second direction is different from the first direction, and is parallel to the plane of the substrate 2110;
in the first direction, the first and second direction,
the phase change memory layer 2310 is arranged in parallel with and electrically connected to the source electrode;
or the like, or, alternatively,
the phase change memory layer 2310 is disposed in parallel with and electrically connected to the drain electrode.
Illustratively, referring to fig. 2, the phase change memory cell 2300 may include a phase change memory layer 2310, a drain 2323, a channel layer 2322, and a source 2321, which are sequentially juxtaposed in a forward direction along an x-axis. At this time, the phase change memory layer 2310 is electrically connected to the drain 2323.
In other embodiments, the phase change memory cell 2300 may also include a phase change memory layer, a source, a channel layer, and a drain juxtaposed in order along the x-axis forward direction. At this time, the phase change memory layer is electrically connected to the source.
Illustratively, referring to fig. 2, the gate layer 2324 extends in the y-direction and wraps around the channel layer 2322. It is understood that the channel layer 2322 includes left and right surfaces oppositely disposed in the y-direction and upper and lower surfaces oppositely disposed in the z-direction, and the gate layer 2324 is disposed to wrap the left, right, upper and lower surfaces of the channel layer 2322. In the present disclosure, the channel layer 2322 further includes a front surface and a rear surface that are oppositely disposed in the x-direction, the drain 2323 is electrically connected to the front surface of the channel layer 2322, and the source 2321 is electrically connected to the rear surface of the channel layer 2322.
In some embodiments, the angle between the first direction and the second direction comprises: acute, right, or obtuse angle. As shown in fig. 2, here, the x direction represents a first direction, the y direction represents a second direction, the x direction is different from the y direction, and the xoy plane is parallel to the plane of the substrate.
The constituent materials of the substrate 2110 include: a semiconductor material. Such as elemental semiconductor materials (silicon, germanium), group iii-v compound semiconductor materials, group ii-vi compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art.
The composition material of the phase change memory layer 2310 includes: chalcogenide-based alloys. For example, a GST (Ge-Sb-Te) alloy. The constituent material of phase change memory layer 2310 may also include any other suitable phase change material.
Note that when the phase-change memory layer 2310 is phase-changed, the resistance of the phase-change memory layer 2310 is changed. The phase change memory 2000 may store data according to a change in resistance state of the phase change memory layer 2310.
The source 2321, the channel layer 2322 and the drain 2323 comprise the following constituent materials: a semiconductor material. Such as silicon, polysilicon, doped silicon, doped polysilicon, or the like.
The gate layer 2324 is composed of the following materials: a conductive material. For example, tungsten (W), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), or the like.
In the embodiment of the disclosure, the integration of the phase change memory layer and the transistor can be realized by electrically connecting the phase change memory layer to the source electrode or the drain electrode of the transistor. The transistor has the advantages that the contact area of the gate layer and the channel layer can be increased due to the fact that the gate layer is wrapped by the channel layer, the control capacity of the gate layer in the transistor on current can be improved, the transistor can provide enough current to drive the phase change storage layer (namely, the phase change material) to carry out phase change in the phase change memory in the process of storing data based on the phase state of the phase change material, and the performance of the phase change memory is improved.
Furthermore, as the control capability of the grid layer on the current is increased, the phase change storage layer can be driven to generate phase change by a small current, so that the power consumption of the phase change storage is reduced, and the operation speed of the phase change memory is improved.
Compared with the phase change memory unit provided with the gating layer, the phase change memory unit is turned on/off by utilizing the bidirectional threshold characteristic of the gating material.
In some embodiments, referring to fig. 3, the phase change memory 2000 further includes:
a first conductive line 2400 juxtaposed with the substrate 2110 and the phase change memory cell 2300 along a third direction and extending along the first direction; wherein the first conductive line 2400 is electrically connected to the gate layer 2324; the third direction is vertical to the plane of the substrate;
a second conductive line 2500 juxtaposed to the phase change memory layer 2310 and the transistor 2320 in a first direction and extending in a second direction; wherein the second conductive line 2500 is electrically connected to the phase change memory layer 2310; second conductive line 2500 is electrically insulated from first conductive line 2400.
Illustratively, referring to fig. 3, a substrate 2110, a phase-change memory cell 2300 and a first conductive line 2400 are sequentially stacked along a z-direction, and the first conductive line 2400 is located on a gate layer 2324 and electrically connected to the gate layer 2324. The first conductive lines 2400 extend in the x-direction. Here, the z direction denotes a third direction, and the z direction is perpendicular to the xoy plane.
Illustratively, referring to fig. 3, a second conductive line 2500, a phase-change memory layer 2310, and a transistor 2320 are sequentially disposed along the x-direction, the second conductive line 2500 being located on a side of the phase-change memory layer 2310 opposite to the transistor 2320 and electrically connected to the phase-change memory layer 2310. The second conductive lines 2500 extend in the y-direction.
It is emphasized that the first plane in which the first conductive line 2400 is disposed and the second plane in which the second conductive line 2500 is disposed are parallel, and the first plane and the second plane do not overlap.
Illustratively, the first conductive line 2400 may be a word line (word line) of a phase change memory, and the second conductive line 2500 may be a bit line (bit line) of the phase change memory. Alternatively, the first conductive line 2400 may be a bit line of the phase change memory 2000 and the second conductive line 2500 may be a word line of the phase change memory.
The constituent materials of the first conductive line 2400 and the second conductive line 2500 include: a conductive material. The conductive material includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, or any combination thereof. The constituent materials of the first conductive line 2400 and the second conductive line 2500 may be the same or different.
In the embodiment of the disclosure, by providing the first conductive line electrically connected to the gate layer and the second conductive line electrically connected to the phase-change memory layer, the operations of reading/writing/erasing and the like of the phase-change memory cell can be realized by using the first conductive line and the second conductive line.
In some embodiments, the phase change memory 2000 further comprises:
a phase change memory array comprising:
a plurality of phase change memory cells arranged in parallel along a first direction;
and/or;
a plurality of phase change memory cells arranged in parallel along a second direction;
and/or;
and a plurality of phase change memory cells arranged in parallel along a third direction.
Illustratively, referring to FIG. 3, a phase change memory array may include 4 phase change memory cells juxtaposed along the y-direction, and 2 phase change memory cells juxtaposed along the z-direction. It is understood that the phase change memory shown in fig. 3 includes 8 phase change memory cells.
It is emphasized that the 8 are merely illustrative, and the number of phase change memory cells in the phase change memory is not limited to the 8 shown in fig. 3, but may be other numbers, such as 16, 32, 64, 128 or more.
In some embodiments, a phase change memory array includes: n phase change memory cells are arranged in parallel along a first direction, wherein N is a natural number. It is understood that, in the embodiments of the present disclosure, the phase change memory includes N phase change memory cells.
In some embodiments, a phase change memory array includes: m phase change memory cells arranged in parallel along the second direction, wherein M is a natural number. It is understood that, in the embodiments of the present disclosure, the phase change memory includes M phase change memory cells.
In some embodiments, a phase change memory array includes: l phase change memory cells arranged in parallel along a third direction, wherein L is a natural number. It is understood that, in the embodiments of the present disclosure, the phase change memory includes L phase change memory cells.
In some embodiments, a phase change memory array includes: n phase change memory cells arranged in parallel along a first direction, and M phase change memory cells arranged in parallel along a second direction, wherein N and M are natural numbers. It is understood that in the embodiments of the present disclosure, the phase change memory includes (N × M) phase change memory cells.
In some embodiments, a phase change memory array includes: n phase change memory cells arranged in parallel along a first direction, and L phase change memory cells arranged in parallel along a third direction, wherein N and L are natural numbers. It is understood that in the embodiments of the present disclosure, the phase change memory includes (N × L) phase change memory cells.
In some embodiments, a phase change memory array includes: m phase change memory cells arranged in parallel along the second direction, and L phase change memory cells arranged in parallel along the third direction, wherein M and L are natural numbers. It is understood that, in the embodiments of the present disclosure, the phase change memory includes (M × L) phase change memory cells.
In some embodiments, a phase change memory includes: n phase change memory cells arranged in parallel along a first direction, M phase change memory cells arranged in parallel along a second direction, and L phase change memory cells arranged in parallel along a third direction, wherein N, M and L are natural numbers. It is understood that in the embodiments of the present disclosure, the phase change memory includes (N × M × L) phase change memory cells.
In the embodiment of the disclosure, by arranging the phase change memory array, since the phase change memory array may respectively include a plurality of phase change memory cells arranged in parallel along the first direction, the second direction and the third direction, three-dimensional (3D) integration of the phase change memory may be achieved, the integration level and the bit density of the phase change memory may be improved, and the bit cost of the memory may be reduced.
In some embodiments, when a plurality of phase change memory cells are juxtaposed in a first direction, the phase change memory further includes a plurality of second conductive lines juxtaposed in the first direction;
and/or;
when the phase change memory unit is arranged in parallel along the second direction, the phase change memory further comprises a plurality of first conductive wires arranged in parallel along the second direction;
and/or;
when the plurality of phase change memory cells are arranged in parallel along the third direction, the phase change memory further includes a plurality of second conductive lines arranged in parallel along the third direction.
Exemplarily, referring to fig. 3, when 4 phase change memory cells are juxtaposed in the y-direction, the phase change memory further includes 4 first conductive lines juxtaposed in the y-th direction, and when 2 phase change memory cells are juxtaposed in the z-direction, the phase change memory further includes 2 second conductive lines juxtaposed in the z-th direction.
For example, a first conductive line 2400-1, a second first conductive line 2400-2, a third first conductive line 2400-3, and a fourth first conductive line 2400-4 are juxtaposed in the y-direction. The first second conductive line 2500-1 and the second conductive line 2500-2 are juxtaposed along the z-th direction.
It is emphasized that here the first conductive line 2400-1, the second first conductive line 2400-2, the third first conductive line 2400-3, and the fourth first conductive line 2400-4 all represent the first conductive line 2400. The first second electrically conductive line 2500-1 and the second electrically conductive line 2500-2 each represent a second electrically conductive line 2500. The different reference numerals are only used to distinguish the difference in position of the first conductive line and the second conductive line and are not necessarily used to describe a specific order or sequence.
In some embodiments, when N phase change memory cells are juxtaposed in the first direction, the phase change memory further includes N second conductive lines juxtaposed in the first direction, where N is a natural number. It is understood that, in the embodiments of the present disclosure, each of the second conductive lines is electrically connected to the phase change memory layer of each of the phase change memory cells juxtaposed in the first direction, respectively.
In some embodiments, when M phase change memory cells are juxtaposed in the second direction, the phase change memory further includes M first conductive lines juxtaposed in the second direction, M being a natural number. It is understood that, in the embodiments of the present disclosure, each of the first conductive lines is electrically connected to the gate layer of each of the phase change memory cells, respectively.
In some embodiments, when the L phase change memory cells are juxtaposed in the third direction, the phase change memory further includes L second conductive lines juxtaposed in the third direction, where L is a natural number. It is understood that, in the embodiments of the present disclosure, each of the second conductive lines is electrically connected to the phase change memory layer of each of the phase change memory cells juxtaposed in the third direction, respectively.
In some embodiments, the phase change memory further includes N second conductive lines juxtaposed in the first direction when N phase change memory cells are juxtaposed in the first direction, and M first conductive lines juxtaposed in the second direction when M phase change memory cells are juxtaposed in the second direction, N and M being natural numbers.
In some embodiments, when N phase change memory cells are juxtaposed in the first direction, the phase change memory further includes N second conductive lines juxtaposed in the first direction, and when L phase change memory cells are juxtaposed in the third direction, the phase change memory further includes L second conductive lines juxtaposed in the third direction, N and L being natural numbers.
In some embodiments, when M phase change memory cells are juxtaposed in the second direction, the phase change memory further includes M first conductive lines juxtaposed in the second direction, and when L phase change memory cells are juxtaposed in the third direction, the phase change memory further includes L second conductive lines juxtaposed in the third direction, M and L being natural numbers.
In some embodiments, when N phase change memory cells are juxtaposed in a first direction, the phase change memory further includes N second conductive lines juxtaposed in the first direction, and, when M phase change memory cells are juxtaposed in a second direction, the phase change memory further includes M first conductive lines juxtaposed in the second direction, and, when L phase change memory cells are juxtaposed in a third direction, the phase change memory further includes L second conductive lines juxtaposed in the third direction, N, M, and L being natural numbers.
In the embodiments of the present disclosure, when the phase change memory array is arranged in three dimensions, since the wirings (e.g., the first conductive lines and/or the second conductive lines) in the phase change memory are arranged in three dimensions, the three-dimensional phase change memory array and the peripheral circuit can be electrically connected.
In some embodiments, a channel layer, comprises: a plurality of sub-channel layers arranged in parallel in a third direction;
a source electrode, comprising: a plurality of sub-source electrodes arranged in parallel along a third direction; wherein, the sub-source pole is positioned at one side of the sub-channel layer;
a drain electrode, comprising: a plurality of sub-drains arranged in parallel along a third direction; the sub-drain electrode is positioned on the other side of the sub-channel layer;
a phase change memory layer comprising: a plurality of sub phase change memory layers arranged in parallel in a third direction; each sub-phase change storage layer is electrically connected with each sub-source electrode or each sub-drain electrode respectively;
the phase change memory 2000 further includes: and the gate dielectric layer is positioned between the sub-channel layer and the gate electrode layer.
Illustratively, referring to fig. 2, the channel layer 2322 includes 2 sub-channel layers juxtaposed in the z-direction, the source 2321 includes 2 sub-sources juxtaposed in the z-direction, and the drain 2323 includes 2 sub-drains juxtaposed in the z-direction. The sub-source electrode is positioned at one side of the sub-channel layer which is oppositely arranged along the x direction, and the sub-drain electrode is positioned at the other side of the sub-channel layer which is oppositely arranged along the x direction. Accordingly, the phase change memory layer 2310 includes 2 sub phase change memory layers juxtaposed in the z direction, each sub phase change memory layer being electrically connected to each sub drain electrode, respectively. At this time, the sub-drain is positioned between the sub-phase change memory layer and the sub-channel layer.
In other embodiments, the phase change storage layer comprises a plurality of sub phase change storage layers juxtaposed in the z-direction, each sub phase change storage layer being electrically connected to each of the electron sources, respectively. It is understood that, at this time, the sub-source pole is located between the sub-phase change memory layer and the sub-channel layer.
It should be noted that a gate dielectric layer (not shown in the figure) is further included between the sub-channel layer and the gate electrode layer, the gate dielectric layer is disposed to wrap the left surface, the right surface, the upper surface and the lower surface of the sub-channel layer, and the gate electrode layer is disposed to wrap the left surface, the right surface, the upper surface and the lower surface of the gate dielectric layer.
The gate dielectric layer comprises the following components: an insulating material. Such as silicon oxide, silicon dioxide, or silicon nitride.
In some embodiments, a sub-channel layer, comprising:
nanoplatelets extending in a first direction; wherein, the nano sheet is positioned between the sub source electrode and the sub drain electrode;
or the like, or, alternatively,
a nanowire extending in a first direction; wherein the nanowire is positioned between the sub-source and the sub-drain.
Illustratively, referring to fig. 2, the sub-channel layer may include a nanowire extending in the x-direction, the nanowire being located between the sub-source and the sub-drain.
In other embodiments, the sub-channel layer may include nanosheets extending along the x-direction, the nanosheets being located between the sub-source and the sub-drain.
In the embodiments of the disclosure, by disposing the sub-channel layer to include the nano-sheet or the nano-wire extending along the first direction, the integration level and the bit density of the phase change memory can be further improved due to the generally small size of the nano-sheet or the nano-wire.
In some embodiments, referring to fig. 2, the phase change memory 2000 further includes:
an active region 2120 between the substrate 2110 and the phase-change memory cell 2300 for providing an electrical signal to the phase-change memory cell 2300; wherein the top width W of the active region 2120 1 Is smaller than the bottom width W of the active region 2120 2 。
The composition material of the active region includes: a semiconductor material. Such as silicon, polysilicon, doped silicon, doped polysilicon, or the like.
In the embodiment of the present disclosure, since the top width of the active region is smaller than the bottom width of the active region, before the sub-channel layer of the nano-sheet or nano-wire is not formed, the active region can provide support to prevent the structure on the upper portion from bending deformation or maintain the upright degree thereof.
In some embodiments, the active region 2120, along a cross-sectional shape perpendicular to a plane of the substrate, includes: trapezoidal or trapezoid-like.
Illustratively, referring to FIG. 2, the projection of active area 2120 onto the yoz plane is trapezoidal. It is understood that in embodiments of the present disclosure, the projection of the top surface of the active region 2120 and the bottom surface of the active region 2120 onto the yoz plane is in a straight line.
In other embodiments, the projection of active area 2120 in the yoz plane is trapezoid-like. It is understood that in embodiments of the present disclosure, the projection of the top surface of active region 2120 and the bottom surface of active region 2120 onto the yoz plane is an arc.
In some embodiments, the top width W of the active region 1 The range of (A) is as follows: 3nm to 7nm.
In the embodiment of the disclosure, since the width of the top of the active region ranges from 3nm to 7nm, the active region is compatible with the most advanced node process of the current memory, which is beneficial to reducing the feature size of the memory and further improving the integration level and the bit density of the memory.
In some embodiments, referring to fig. 3, the phase change memory 2000 further includes:
a plurality of active regions 2120 juxtaposed in a second direction;
an insulating isolation structure 2200 between two adjacent active regions 2120; wherein the top width of the isolation structure 2200 is greater than the bottom width of the isolation structure 2200.
The isolation structure 2200 is composed of materials including: an insulating material. Such as silicon oxide, silicon dioxide, or silicon nitride.
In the embodiments of the present disclosure, by providing the isolation structure between two adjacent active regions, electrical insulation between two adjacent phase change memory cells can be achieved, and meanwhile, thermal crosstalk between two adjacent phase change memory cells is reduced.
In the embodiments provided in the present disclosure, it should be understood that the disclosed apparatus, system, and method may be implemented in other ways. The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present disclosure, and shall cover the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (9)
1. A phase change memory, comprising:
a phase change memory cell on a substrate, comprising: the phase change memory layer and the transistor are arranged in parallel along a first direction; wherein the first direction is parallel to the plane of the substrate;
the transistor, comprising:
a source electrode, a channel layer and a drain electrode arranged in parallel along the first direction;
the grid layer extends along the second direction and wraps the channel layer; the second direction is different from the first direction and is parallel to the plane of the substrate;
in the direction of the said first direction,
the phase change storage layer and the source electrode are arranged in parallel and electrically connected; or the phase change storage layer and the drain electrode are arranged in parallel and electrically connected;
the phase change memory further includes:
a first conductive line juxtaposed with the substrate and the phase change memory cell in a third direction and extending in the first direction; wherein the first conductive line is electrically connected with the gate layer; the third direction is vertical to the plane of the substrate;
a second conductive line juxtaposed with the phase change memory layer and the transistor along the first direction and extending along the second direction; wherein the second conductive line is electrically connected to the phase change storage layer; the second electrically conductive line is electrically insulated from the first electrically conductive line.
2. The phase change memory according to claim 1, further comprising:
a phase change memory array comprising:
a plurality of the phase change memory cells arranged in parallel along the first direction;
and/or;
a plurality of the phase change memory cells arranged in parallel along the second direction;
and/or;
and the phase change memory units are arranged in parallel along the third direction.
3. The phase change memory according to claim 2,
when a plurality of the phase change memory cells are arranged in parallel along the first direction, the phase change memory further comprises a plurality of the second conductive lines arranged in parallel along the first direction;
and/or;
when a plurality of the phase change memory cells are juxtaposed along the second direction, the phase change memory further includes a plurality of the first conductive lines juxtaposed along the second direction;
and/or;
when the plurality of phase change memory cells are arranged in parallel along the third direction, the phase change memory further comprises a plurality of second conductive lines arranged in parallel along the third direction.
4. The phase change memory according to claim 1, wherein the channel layer comprises: a plurality of sub-channel layers arranged in parallel along the third direction;
the source electrode includes: a plurality of sub-source electrodes arranged in parallel along the third direction; wherein the sub-source is located at one side of the sub-channel layer;
the drain electrode includes: a plurality of sub-drains arranged in parallel along the third direction; wherein the sub-drain is located at the other side of the sub-channel layer;
the phase change memory layer includes: a plurality of sub phase change memory layers arranged in parallel in the third direction; wherein each of the sub phase change memory layers is electrically connected to each of the sub source electrodes or each of the sub drain electrodes, respectively;
the phase change memory further includes: and the gate dielectric layer is positioned between the sub-channel layer and the gate electrode layer.
5. The phase change memory of claim 4, wherein the sub-channel layer comprises:
nanoplatelets extending along the first direction; wherein the nanosheets are located between the sub-source and the sub-drain;
or the like, or, alternatively,
a nanowire extending along the first direction; wherein the nanowire is located between the sub-source and the sub-drain.
6. The phase change memory according to claim 1, further comprising:
the active region is positioned between the substrate and the phase change memory cell and used for providing an electric signal to the phase change memory cell; wherein a top width of the active region is less than a bottom width of the active region.
7. The phase change memory of claim 6, wherein the active region comprises, in cross-section perpendicular to a plane of the substrate: trapezoidal or trapezoid-like.
8. The phase change memory of claim 6, wherein the top width of the active region ranges from: 3nm to 7nm.
9. The phase change memory according to claim 6, further comprising:
a plurality of the active regions arranged in parallel along the second direction;
the insulating isolation structure is positioned between two adjacent active regions; wherein a top width of the isolation structure is greater than a bottom width of the isolation structure.
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