KR20190065980A - Next Generation Non-Volatile Mott Memory Device using Characteristic of Transition Metal Oxides - Google Patents

Abstract

The present invention relates to a resistive switching memory device and a method of manufacturing the same. According to an embodiment of the present invention, the resistive switching memory device comprises: an oxidizable first electrode; a resistive switching material layer disposed on the first electrode and generating a metal insulator transition having a perovskite crystal structure represented by chemical formula 1, AMO_3; and a second electrode disposed on the resistive switching material layer. A resistance value of the resistive switching material layer is adjusted according to the oxygen concentration in the resistive switching material layer, and an energy barrier is created or extinguished by the oxygen movement at an interface between the first electrode and the resistive switching material layer. In the chemical formula 1, A is a lanthanide element, M is a transition metal element, and O is an oxygen element.

Description

TECHNICAL FIELD [0001] The present invention relates to a next generation nonvolatile memory device using characteristics of a transition metal oxide material,

The present invention relates to semiconductor technology, and more particularly, to a resistance-change memory element and a method of manufacturing the same.

In order to replace the flash memory technology, which is a resistance change memory device, as the integration of the memory reaches a limit, a resistance random access memory (ReRAM), a phase change memory (PcRAM, Phase-change Random Access Memory) and Spin Transfer Torque Magnetic Random Access Memory (STTRAM). Among them, a resistance-change memory (ReRAM) is a next-generation nonvolatile memory having a simple metal-insulator-metal (MIM) structure and excellent operation characteristics, and has been extensively studied and actively studied.

In a conventional resistance change memory device, a forming process is essentially performed to form a filament to form a conducting path or to have a different electrical resistance depending on a switching state. The forming process is a process of activating a device so that a resistance voltage can be applied by applying a predetermined voltage (hereinafter referred to as a forming voltage) to the resistance variable material. The conductive filament formed through the foaming process can electrically connect the upper electrode and the lower electrode. The conductive filament, which electrically connects the upper electrode and the lower electrode, may be at least partially cut off by a reset voltage. Conversely, the conductive filament, which is cut off by the reset voltage, ). ≪ / RTI >

In general, in a conventional resistance-change memory element, the forming voltage is larger than the reset voltage and the set voltage, and consequently power consumption may be increased. In addition, the resistance-change memory device that operates based on oxidation-reduction may have a limitation in minimizing leakage current because a current of a certain level or more is required as a driving current.

In particular, when the memory device has a cross-point array structure for memory integration, an operation error may occur due to inter-cell crosstalk due to sneak current from adjacent memory cells. To overcome this, a selection device that acts as a switch, such as a diode, may be needed. In order to form the selection device, a process of sequentially stacking a switch element and a resistance change memory is required. When different kinds of thin films are deposited at a high temperature, an undesired characteristic change may occur at the interface between thin films having different properties have. Particularly, when defects are concentrated at the interface, a problem that a reliable current-voltage characteristic can not be obtained may occur.

It is an object of the present invention to provide a resistance change memory device which eliminates or reduces the inter-cell interference without requiring a forming process using a high voltage, low power consumption, and without using a selection device at the same time.

It is another object of the present invention to provide a method of manufacturing a resistance change memory element having the above-described advantages.

According to an embodiment of the present invention, there is provided a plasma display panel comprising: an oxidizable first electrode; A resistance change material layer disposed on the first electrode and generating a metal insulator transition having a perovskite crystal structure represented by Chemical Formula 1; And a second electrode disposed on the resistance change material layer, wherein a resistance value of the resistance change material layer is adjusted according to an oxygen concentration in the resistance change material layer, A resistance change memory element in which an energy barrier is generated or eliminated by oxygen transfer at the interface of the resistance change memory element can be provided.

[Chemical Formula 1]

AMO ₃ (where A is a lanthanide element, M is a transition metal element, and O is an oxygen element).

In one embodiment, the resistance change material layer may comprise any one of LaTiO ₃ , LaNiO ₃ , LaCuO ₃ , LaScO ₃ , LaVO ₃ , LaMnO ₃ , LaCrO ₃ , LaCoO ₃ , and LaCO ₃ . Wherein the first electrode includes titanium (Ti), tungsten (W), aluminum (Al), or an alloy thereof as an oxidizable reactive metal and the second electrode is a non-reactive noble metal, Iridium (Ir), palladium (Pd), gold (Au), ruthenium (Ru), or alloys thereof. The adjustment of the resistance value can be performed by adjusting the bandgap of the resistance change material layer. When the oxygen concentration is increased, the resistance value is increased, and when the oxygen concentration is decreased, the resistance value can be decreased. The low resistance state of the resistance change material layer is assigned in a program state, and the high resistance state of the resistance change material layer can be assigned to an erase state. The metal insulator transition may include a mott transition. An energy barrier is formed at an interface between the first electrode and the resistance change material layer when a positive voltage is applied to the first electrode. When a negative voltage is applied to the first electrode, The energy barrier is extinguished at the interface between the anode and the cathode, so that the diode characteristics can be determined. A Schottky barrier layer may be disposed at an interface between at least one of the first electrode and the second electrode and the resistance change material layer.

According to another embodiment of the present invention, a semiconductor memory device having a cross point structure of memory cells including the resistance change memory element described in the first aspect as an information storage element may be provided.

According to another embodiment of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming an oxidizable first electrode; Forming a resistance change material layer on the first electrode to generate a metal insulator transition having a perovskite crystal structure represented by Formula 2 below; And a resistance change memory layer in which the resistance value of the resistance change material layer is adjusted in accordance with the oxygen concentration in the resistance change material layer and an energy barrier is generated or destroyed by oxygen movement at an interface between the first electrode and the resistance change material layer, A method of manufacturing a device can be provided.

(2)

AMO ₃ (where A is a lanthanide element, M is a transition metal element, and O is an oxygen element).

In one embodiment, the resistance change material layer may comprise any one of LaTiO ₃ , LaNiO ₃ , LaCuO ₃ , LaScO ₃ , LaVO ₃ , LaMnO ₃ , LaCrO ₃ , LaCoO ₃ , and LaCO ₃ . Wherein the second electrode comprises a non-reactive noble metal including platinum (Pt), iridium (Ir), palladium (Pd), gold (Au), ruthenium (Ru) As the possible reactive metal, it may include titanium (Ti), tungsten (W), aluminum (Al), molybdenum (Mo), tantalum (Ta) The bandgap of the resistance change material layer may range from 0.01 eV to 0.5 eV.

According to an embodiment of the present invention, there is provided a plasma display panel comprising: an oxidizable first electrode; A resistance change material layer disposed on the first electrode and generating a metal insulator transition having a perovskite crystal structure represented by Chemical Formula 1; And a second electrode disposed on the resistance-change material layer and forming a Schottky barrier layer at an interface with the resistance-change material layer, whereby a forming process using a high voltage is unnecessary, a power consumption is low It is possible to implement a resistance change memory element capable of eliminating or reducing inter-cell interference without using a selection element. In addition, by replacing the forming process of the resistance-variable memory element, the reset process can be performed immediately without performing the forming process, thereby making it possible to improve the damage of the device due to the high voltage required for the forming process, And can realize a low power, high performance memory device which is a requirement of the next generation memory.

Further, according to another embodiment of the present invention, a method of manufacturing a resistance-change memory element having the above-described advantages can be provided.

1A is a perspective view of a semiconductor memory device having a cross-point array according to an embodiment of the present invention, and FIG. 1B is a cross-sectional view of a resistance-change memory device according to an embodiment of the present invention.
2A to 2D are diagrams for explaining a mott transition according to an embodiment of the present invention.
3 is a flowchart illustrating a method of manufacturing a resistance-variable memory device according to an embodiment of the present invention.
4 is a block diagram illustrating a storage device including a solid state disk according to one embodiment of the present invention.
5 is a block diagram illustrating a memory system in accordance with another embodiment of the present invention.
6 is a block diagram illustrating a data storage device in accordance with another embodiment of the present invention.
7 is a block diagram illustrating a resistance change memory device and a computing system including the same, according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The embodiments of the present invention are described in order to more fully explain the present invention to those skilled in the art, and the following embodiments may be modified into various other forms, It is not limited to the embodiment. Rather, these embodiments are provided so that this disclosure will be more faithful and complete, and will fully convey the scope of the invention to those skilled in the art.

Like numbers refer to like elements in the drawings. Also, as used herein, the term "and / or" includes any and all combinations of any of the listed items.

The terms used herein are used to illustrate the embodiments and are not intended to limit the scope of the invention. Also, although described in the singular, unless the context clearly indicates a singular form, the singular forms may include plural forms. Also, the terms "comprise" and / or "comprising" used herein should be interpreted as referring to the presence of stated shapes, numbers, steps, operations, elements, elements and / And does not exclude the presence or addition of other features, numbers, operations, elements, elements, and / or groups.

Reference herein to a layer formed "on" a substrate or other layer refers to a layer formed directly on top of the substrate or other layer, or may be formed on intermediate or intermediate layers formed on the substrate or other layer Layer. ≪ / RTI > It will also be appreciated by those skilled in the art that structures or shapes that are "adjacent" to other features may have portions that overlap or are disposed below the adjacent features.

As used herein, the terms "below," "above," "upper," "lower," "horizontal," or " May be used to describe the relationship of one constituent member, layer or regions with other constituent members, layers or regions, as shown in the Figures. It is to be understood that these terms encompass not only the directions indicated in the Figures but also the other directions of the devices.

In the following, embodiments of the present invention will be described with reference to cross-sectional views schematically illustrating ideal embodiments (and intermediate structures) of the present invention. In these figures, for example, the size and shape of the members may be exaggerated for convenience and clarity of explanation, and in actual implementation, variations of the illustrated shape may be expected. Accordingly, embodiments of the present invention should not be construed as limited to any particular shape of the regions shown herein. In addition, reference numerals of members in the drawings refer to the same members throughout the drawings.

1A is a perspective view of a semiconductor memory device 100 having a crosspoint array according to one embodiment of the present invention, and FIG. 1B is a cross-sectional view of a resistance change memory device MC according to an embodiment of the present invention.

Referring to FIG. 1A, semiconductor memory device 100 may include an array of resistance-change memory elements MC arranged in a plurality of rows and columns. A set of conductive electrodes (here word lines; WL1-WL4) extend onto one end of the array of memory cells MC. Each word line may be electrically connected to the memory cells MC of the corresponding row. A different set of conductive electrodes (here, bit lines BL1-BL5) may extend onto the other end of the array of memory cells MC. Each bit line may be electrically connected to the memory cells MC in the corresponding column.

In the semiconductor memory device 100, each resistance-change memory element MC is disposed at the intersection of one word line and one bit line. A read and a write operation of a specific memory cell (referred to as a selected memory cell) can be performed by activating a word line and a bit line combined with the selected memory cell.

The semiconductor memory device 100 may further include a word line control circuit (not shown) coupled to the memory cells MC via each word line and activating a selected word line for reading or writing of the selected memory cell . In one embodiment, the word line control circuit may include a multiplexer (not shown) for selecting a particular word line among the word lines.

Semiconductor memory device 100 may further include a bit line control circuit (not shown) coupled to memory cells MC via respective bit lines BL1 - BL5.

In one embodiment, the bit line control circuit may include a demultiplexer, a sense circuit, and an input / output (I / O) pad. The demultiplexer may be configured to selectively couple to the sense circuit of a bit line of a selected memory cell.

The word line control circuit and the bit line control circuit can access the memory cells individually by activating corresponding word lines and bit lines coupled to the selected memory cells. During the write operation, the word line control circuit writes information to the selected memory cell by applying a predetermined voltage to the selected word line. The demultiplexer can activate the selected memory cell, for example, by grounding the selected memory cell. In this case, a logic value is written to the selected memory cell as the current that influences the characteristics of the memory cell flows.

Each of the memory cells includes a resistance change memory element (RE of FIG. 1B), and these logic values can be stored by a change in the resistance value of the resistance change memory element MC, Can be stored. The change in the resistance value is detected through a subsequent read operation.

During a read operation, the word line control circuit applies a predetermined voltage to the selected word line and the demultiplexer couples the selected bit line to the sense circuit. The logic value of the selected memory cell is detected as the magnitude of the current detected by the sense circuit, and the result can be transferred to the I / O pad.

The width and / or the magnitude of the voltage pulse across the memory cell for programming or reading of the selected memory cell is adjusted such that a particular logic state can be written or read by adjusting the resistance value of the selected memory cell. In one embodiment, each memory cell may further include a reverse diode connected in series to the resistance-change memory element, because the read operation may be affected by the leakage current caused by the memory cells adjacent to the selected other memory cell have. The reverse diode may be coupled between the memory cell and the word line or between the memory cell and the bit line. Such a reverse diode may serve as a selection device for isolating selected memory cells and adjacent non-selected memory cells.

The reverse diode may be a Zener diode. The threshold voltage Vth of the reverse diode may have a value smaller than the write voltage. In this case, the current flows through the reverse diode and the memory cell while writing to the selected memory cell, and the current flowing in the reverse direction is blocked by the voltage applied to the adjacent memory cells. The magnitude of the read voltage may be less than the threshold voltage Vth of the reverse diode. For example, the magnitude of the read voltage may be half of the threshold voltage Vth of the reverse diode. However, the selection of the memory cell in the cross point structure can be performed by a half selection method, and the present invention is not limited to this example.

In one embodiment, the rectifying characteristic of such a reverse diode can be implemented in the resistance-change memory element itself when the resistance-change memory element has a self-rectifying characteristic, in which case the reverse diode is omitted, Manufacturing can be further simplified. The resistance-variable memory device according to the above-described embodiment has a single-layer memory cell array, but the present invention is not limited thereto. For example, two or more memory cell arrays may be stacked and integrated. Although the memory cell array horizontally extended with respect to the semiconductor substrate is illustrated in Fig. 1A, it may have a three-dimensional memory cell array extended in the vertical direction with respect to the semiconductor substrate.

Referring to FIG. 1B, the resistance change memory element may include a first electrode EL1 and a second electrode EL2. The first electrode EL1 may be an oxidizable reactive metal.

For example, the first electrode EL1 may be an oxidizable reactive metal electrode. The second electrode EL2 is a metal having a work function of 5 eV or more to form a Schottky barrier layer, and may preferably be a non-reactive noble metal. For example, the first electrode EL1 includes titanium (Ti), tungsten (W), aluminum (Al), or an alloy thereof and the second electrode EL2 includes a platinum Pt ), Iridium (Ir), palladium (Pd), gold (Au), ruthenium (Ru), or alloys thereof. However, the electrode material of the present invention is not limited thereto. In one embodiment, the first electrode EL1 may be an upper electrode and the second electrode EL2 may be a lower electrode. The first electrode EL1 and the second electrode EL2 may be electrically coupled to the word line WL or the bit line BL respectively and the first electrode EL1 and the second electrode EL2 may be electrically coupled to the word line WL or the bit line BL, May be integrated with a word line or a bit line.

The resistance change memory element MC may include a resistance change material layer RE disposed between the first electrode EL1 and the second electrode EL2. The resistance change material layer RE has a perovskite crystal structure represented by the following chemical formula 1 and can generate metal insulator transition by external energy.

[Chemical Formula 1]

AMO ₃ (where A is a lanthanide element, M is a transition metal element, and O is an oxygen element).

Wherein the lanthanide element includes any one selected from La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Lu, Ni, Cu, Sc, V, Cr, Mn, Fe, Co, Zn, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, Hf, Ta, W, Pt, Au, Hg, Rf, Db, Sg, Bh, and Hs.

In an embodiment of the present invention, the resistance change material layer RE may include any one of LaTiO ₃ , LaNiO ₃ , LaCuO ₃ , LaScO ₃ , LaVO ₃ , LaMnO ₃ , LaCrO ₃ , LaCoO ₃ , and LaCO ₃ . Also, the metal insulator transition of the resistance change material layer RE includes a mott transition, and the external energy may be any one of voltage, current, power, light, and heat, The energy may be a voltage for writing or reading data in the resistance-change memory element MC.

According to the driving operation of the resistance change memory element MC according to one embodiment, the resistance value of the resistance change material layer can be adjusted according to the oxygen concentration in the resistance change material layer RE. In addition, the adjustment of the resistance value can be performed by adjusting the bandgap of the resistance change material layer RE. Specifically, by reducing oxygen to the resistance change material layer RE when a negative voltage is applied to the first electrode EL1, the oxygen concentration inside the resistance change material layer RE increases, and the oxygen concentration increases The resistance value of the resistance change material layer RE can be reduced. On the other hand, by oxidizing oxygen in the resistance change material layer RE when positive voltage is applied to the first electrode EL1, the oxygen concentration inside the resistance change material layer RE decreases, and the oxygen concentration decreases The resistance value of the resistance change material layer RE can be increased. In one embodiment, the low resistance state of the resistance change material layer RE is assigned in a program state, and the high resistance state of the resistance change material layer can be assigned to the erase state.

In addition, due to the movement of oxygen in the resistance change material layer RE, polarization occurs in the resistance change material layer RE, and the generated polarization may cause a change in the energy barrier, The device MC may have rectifying characteristics of the diode.

In one embodiment, when a positive voltage is applied to the first electrode EL1, oxygen ions move from the resistance change material layer RE to the first electrode EL1, and the movement of the oxygen ions having a negative charge property changes So that oxygen holes are formed on the surface of the material layer RE. This allows the surface of the resist-charge material to have a characteristic of positive charge. This positive charge characteristic of the surface of the resistance change material layer RE prevents the oxygen ions from moving from the resistance change material layer RE to the first electrode EL1. In addition, before the negative voltage is applied to the first electrode EL1, oxygen ion movement from the resistance-charge material to the first electrode EL1 increases as the positive voltage value and the time at the first electrode EL1 increase The blocking energy barrier can be increased. Thereafter, when a negative voltage is applied to the first electrode EL1, the oxygen ions move from the first electrode EL1 to the resistance change material layer RE, and the positive charge characteristic of the surface of the resistance- It is possible to promote the movement of oxygen ions into the resistance-change material layer RE in the region EL1.

In one embodiment, when a positive voltage is applied to the first electrode EL1, an energy barrier is generated at the interface between the first electrode EL1 and the resistance change material layer RE, and a negative voltage At the time of application, the energy barrier is eliminated at the interface between the first electrode EL1 and the resistance change material layer RE, so that the diode characteristics can be determined.

In another embodiment, when negative voltage is applied to the first electrode EL1, an energy barrier is generated at the interface between the first electrode EL1 and the resistance change material layer RE, and a positive voltage is applied to the first electrode EL1. At the time of application, the energy barrier is eliminated at the interface between the first electrode EL1 and the resistance change material layer RE, so that the diode characteristics can be determined.

As described above, the resistance change memory element MC has a property of changing the resistance value according to the change characteristic of the energy barrier according to the polarization direction caused by the oxygen movement in the transition metal oxide and the oxygen concentration in the transition metal oxide, In the mott transition without the cell selection transistor, the interference phenomenon occurring during the reading process and the voltage drop occurring during the writing process can be solved. At the same time, low power operation is possible without the conventional forming process of the ReRAM.

In the embodiment of the present invention, a mott transition may occur in the resistance change material layer RE through a voltage applied through the first electrode EL1 and the second electrode EL2. The Mott transition refers to a phenomenon in which the Mott insulator changes into a metallic material through which electrons flow, or the Mott insulator of the metallic material changes into an insulation characteristic that does not conduct electricity. The above-mentioned Mott insulator is a kind of a material which becomes an insulator at low temperature although it should be a conductor that conducts electricity according to the existing band theory, and is a phenomenon by electron-electron interactions not considered in the band theory.

According to the band theory, electrons belonging to a partially filled band can move relatively freely to neighboring atoms and become conduction electrons. However, energy barriers due to coulomb repulsion between two electrons already exist in the target atoms to be moved, If it is larger than the kinetic energy of electrons, it may be difficult for electrons to move to adjacent atoms. In the case of a material in which half of the conduction band is full and there is one conduction electron in all the atoms and the electron repulsion energy is sufficiently large, any electrons can not move and become an insulated state. The band gap of such a Mott insulator can exist between two strips having the same characteristic, for example, a strip having a characteristic of a 3d orbit. However, the present invention is not limited to a Mott insulator, and may be a charge-transfer insulator having a band gap between positive and negative ions such as a gap between the 3d band of nickel and the 2p band of oxygen in nickel oxide (II) (NiO) insulators are also applicable.

2A to 2D are diagrams for explaining a mott transition according to an embodiment of the present invention.

2A is a view showing an electronic structure showing an insulation state of a resistance change material layer RE that generates a metal insulator transition, and Figs. 2B and 2D are diagrams showing an electronic structure showing a metal state of the resistance change material layer RE ≪ / RTI >

Referring to Figures 2a and 2b, the Mott insulator, in the band theory, has a partially filled Fermi level (E _F ) that is either half-filled or has only one electron in a band capable of accepting two electrons of opposite spins Quot;) < / RTI > in the sense of a material comprising a band having a width (W) In band theory, a material with half filled bands can have metal properties. However, when the electrostatic repulsive energy (or coulomb repulsion) between electrons located in the same band is considered (referred to as Hubbard energy (U)), the half filled band is divided into one occupied subband Band: LHB) and one empty subband (Upper Hubbard Band: UHB). This can result in the opening of the energy bandgap of the energy width (E _g ) at the Fermi level (E _F ). Thus, as shown in Fig. 2A, opening of the bandgap E _g at the Fermi level EF provides an electrical insulating behavior to the Mott insulator, and as shown in Fig. 2B, a half-filled LHB Can provide metal properties to the Mott insulator. In another embodiment, as shown in FIG. 2C, half-filled UHBs may provide metal properties to the Mott insulator. This may be doped by a suitable chemical modification to add electrons in the UHB subband or to remove electrons from the LHB subband. In this case, the Mott insulator is referred to as n-doped or p-doped, respectively. For such n-doped or p-doped materials, the Fermi level (E _F ) may be placed in the UHB subband or the LHB subband, respectively. In another embodiment, as shown in Figure 2D, the LHB and UHB subbands are superimposed to provide metal properties to the Mott insulator.

In one embodiment, the transition metal oxide such as LaTiO ₃ , LaNiO ₃ , and LaCuO ₃ has a characteristic that the resistance value changes according to the oxygen concentration therein, and the voltage of the oxygen ion to the electrode according to the application of the electric field By adjusting the oxygen concentration according to the reversible movement according to the direction, it is possible to control the resistance change and apply it to the Mott transfer.

According to one embodiment, LaTiO ₃ can transition from an insulator to a metal through a hole doping of about 3.5%, which is a small doping amount, and the amount of doping is small, Do. In addition, the increase in optical conductivity in the region of 0 eV photon energy means that the bandgap in LaTiO ₃ is reduced, which means that it is possible to control the transport of oxygen ions through the electric field. This shows that it is easy to control the band gap for applying LaTiO ₃ as a mott memory device.

In the case of LaTiO _{3 + x} , the resistance value decreases when x (x? 0) increases (or the oxygen concentration increases), and when the x (x = 0) decreases can do. When x is 0, LaTiO _{3 + x} operates as the Mott insulator shown in FIG. 2A, and when x increases, the Ti 3d orbital filling state is changed from 3d 1 to 3d 1 - 2x so that LHB (low The Hubbard band may change from full-filling to half-filling. Half-filling of these LHB subbands is similar to the absence of bandgaps in electron transfer. Thus, LaTiO _{3 + x} can transition from a high-resistance mote-insulator state to a low-resistance metal state with increasing x.

Consequently, the resistance of the resistance-change material layer RE itself is changed by the oxygen concentration change in the resistance-change material layer RE. In particular, the oxygen concentration of the transition metal oxide LaTiO _{3 + x} can be controlled by oxidation and reduction reactions between the first electrode EL1 and LaTiO _{3 + x} . For example, when a positive voltage is applied to the first electrode EL1, the upper electrode can obtain oxygen from the surface of LaTiO3 _{+ x} due to the large free energy of the metal oxidation reaction. On the other hand, when a negative voltage is applied to the first electrode EL1, the oxidized first electrode EL1 (i.e., the first electrode EL1 containing oxygen) can reduce oxygen ions to LaTiO3 _{+ x} have. Since LaTiO _{3 + x} has a strong coulombic repulsion, there is a bandgap corresponding to the energy difference between UHB (empty state) and LHB (full state) when x is zero.

In another embodiment, at x = 0 in LaCuO _3-x , it has a Cu ³⁺ oxidation number and a d8 electron, and generally has a low spin. The E _g band consists of an electron-filled dz2 band and a vacant dx2-y2 band, and the overlapping of the two bands can lead to metal properties. In LaCuO _3-x , when x = 0.5, it has the oxidation number of Cu ²⁺ and d9 electrons. The dx2-y2 band of E _g is filled in half, and due to the influence of the coulomb repulsion U, the insulated characteristic may be separated into a filled low Hubbard band (LHB) and an empty upper Hubbard band (UHB). This shows that it can be applied to the Mote memory of LaCuO _3-x .

In yet another embodiment, LaNiO _3-x can greatly increase its resistance value as oxygen vacancy increases at room temperature. Also, a decrease in the oxygen concentration of LaNiO _3-x can reduce the O-2p band level and bandwidth (localization of O-2p). When the gap between O-2p and 3d bands is larger than the coulomb repulsion U, a Ni band gap can be formed between 3d8 and 3d9. This shows that LaNiO _3-x is applicable to Mott memory.

As described above, a resistive switching behavior may be caused by a change in the electrical characteristic of the resistance change material layer RE itself (due to a change in the electronic structure of the Ti 3d orbit). For example, in order for LaTiO _{3 to} become a Mott insulator, a bandgap can be formed by repulsion by Ti-3d electrons, and one electron is present in the LaTiO ₃ Ti-3d orbitals, , The electrons can be located at the lowest energy level level in the Ti-3d orbitals. However, the lowest energy level of Ti-3d can be separated by the repulsive energy between the two electrons. The low energy band filled with one electron is LHB and the other energy band is UHB. The value of the bandgap can be defined as the difference between LHB and UHB. When here, increasing the oxygen concentration of the LaTiO ₃ means that the x value of the LaTiO _{3 + x} increases, and wherein Ti-3d orbital is losing more electrons, which filled half while the LHB filled (full filling) state ( half filling or no-full-filling). Thus, as x increases, LaTiO _{3 + x} changes from a moth insulator to a metallic material. In addition, an increase in oxygen concentration can convert LaTiO ₃ from a moth insulator to a metal with a decrease in resistance ( _x increase in LaTiO _{3 + x} ).

In the case of the Mott transition induced by the movement of oxygen ions, oxygen ions do not exist in the upper electrode EL1. Therefore, the oxygen ions first move from the LaTiO _{3 + x} to the upper electrode EL1, in (EL1) is moved to the LaTiO _3. Therefore, it is necessary to form LaTiO _{3 + x} in an oxygen-rich state (metal state with a half-filling lower Hubbard band) in the first step. When a positive voltage is applied to the upper electrode, the oxygen ions move from LaTiO _{3 + x} to the upper electrode EL2 due to the redox reaction between the upper electrode EL1 and LaTiO _{3 + x} . On the other hand, if oxygen ions are reduced in LaTiO _{3 + x} , electrons are generated and the half-filling LHB (see FIG. 2B) can be changed to a full-filling LHB (see FIG. In this state, LaTiO _{3 + x} can be a Mott insulator having a high resistance due to a decrease in oxygen concentration.

In the case of a conventional transition metal oxide, but the band gap, the band gap adjusted for application to the cursor Mott memory difficulties, LaTiO _3, LaNiO _3, LaCuO ₃ is used as a Mott insulator of the present invention, each ~ 0.2 eV or less, - And has a band gap of 0.02-0.29 eV or less, and a band gap of ~0.14-0.28 eV or less, preferably 0.01 eV to 0.5 eV, so that the band gap can be easily controlled and applicable to a memory.

3 is a flowchart illustrating a method of manufacturing a resistance-variable memory device according to an embodiment of the present invention.

Referring to FIG. 2, a method of fabricating a resistance-variable memory device includes forming a first electrode that can be oxidized on a substrate (S10), forming a perovskite structure on the first electrode, (S20) of forming a resistance change material layer that generates a metal insulator transition having a crystal structure, and forming a second electrode (S30) on the resistance change material layer to form a Schottky barrier layer can do.

(2)

AMO ₃ (where A is a lanthanide element, M is a transition metal element, and O is an oxygen element).

In one embodiment, the resistance change material layer may comprise any one of LaTiO ₃ , LaNiO ₃ , LaCuO ₃ , LaScO ₃ , LaVO ₃ , LaMnO ₃ , LaCrO ₃ , LaCoO ₃ , and LaCO ₃ .

In one embodiment, the second electrode includes platinum (Pt), iridium (Ir), palladium (Pd), gold (Au), ruthenium (Ru), or an alloy thereof as the non- The one electrode may include titanium (Ti), tungsten (W), aluminum (Al), molybdenum (Mo), tantalum (Ta), or an alloy thereof as an oxidizable reactive metal.

The substrate may be a semiconductor substrate such as a Si single crystal substrate, a compound semiconductor substrate, an SOI substrate, and a modified substrate, but the present invention is not limited thereto. For example, the substrate may be a ceramic substrate or a polymer substrate for implementing a flexible device, or even a fabric layer. In addition, an oxide film may be deposited on the substrate or an upper portion of the substrate may be oxidized to form an oxide film. For example, silicon oxide (SiO2) may be deposited or oxidized on a silicon substrate.

At least one of the first electrode, the resistance change material layer and the second electrode may be formed by sputtering, pulsed laser deposition (PLD), thermal evaporation, electron-beam evaporation, May be formed using the same physical vapor deposition (PVD), molecular beam epitaxy (MBE), or chemical vapor deposition (CVD).

4 is a block diagram illustrating a storage device 1000 including a solid state disk (SSD) according to an embodiment of the invention.

Referring to FIG. 4, a storage device 1000 may include a host 1100 and an SSD 1200. The SSD 1200 may include an SSD controller 1210, a buffer memory 1220, and a resistance change memory element 1230. The SSD controller 1210 provides electrical and physical connections between the host 1100 and the SSD 1200. In one embodiment, the SSD controller 1210 may provide interfacing with the SSD 1200 in response to the bus format of the host 1100. In addition, the SSD controller 1210 can access the resistance-change memory element 1230 according to the decoded result of decoding the instruction provided from the host 1100. [ (PCI) express, Advanced Technology Attachment (ATA), Parallel ATA (PATA), SATA (Serial ATA), and the like, as a non-limiting example of the bus format of the host 1100. [ Serial ATA), and Serial Attached SCSI (SAS).

In the buffer memory 1220, write data provided from the host 1100 or data read from the resistance-change memory element 1230 can be temporarily stored. When data existing in the resistance change memory element 1230 is cached at the time of a read request of the host 1100, the buffer memory 1220 is provided with a cache function for directly providing the cached data to the host 1100 . In general, the data transfer rate by the host 1100 bus format (e.g., SATA or SAS) may be faster than the transfer rate of the memory channel of the SSD 1200. [ In this case, a large-capacity buffer memory 1220 is provided to minimize the performance degradation caused by the speed difference. The buffer memory 1220 for this purpose may be, but is not limited to, a synchronous DRAM to provide sufficient buffering. The resistance change memory element 1230 may be provided as a storage medium of the SSD 1200.

5 is a block diagram illustrating a memory system 2000 in accordance with another embodiment of the present invention.

Referring to FIG. 5, a memory system 2000 according to the present invention may include a memory controller 2200 and a resistance-change memory element 2100. The resistance-change memory element 2100 may include the resistance-change memory element 1000 disclosed with reference to FIG. 1B. The resistance-change memory element 2100 can detect memory cells having an abnormal speed when verifying target states, and can have high-speed reliable program performance.

The memory controller 2200 may be configured to control the resistance-change memory element 2100. The SRAM 2230 can be used as an operation memory of the CPU 2210. [ The host interface 2220 may implement a data exchange protocol of the host connected to the memory system 2000. The error correction circuit 2240 included in the memory controller 2200 can detect and correct an error included in data read from the resistance change memory element 2100. The memory interface 2260 may interface with the non-volatile resistance-change memory 2100 of the present invention. The CPU 2210 can perform all control operations for data exchange of the memory controller 2200. [ The memory system 2000 according to the present invention may further include a ROM (not shown) for storing code data for interfacing with a host.

The memory controller 2100 is configured to communicate with external circuitry (e.g., a host) through any of a variety of interface protocols such as USB, MMC, PCI-E, SAS, SATA, PATA, SCSI, ESDI, . The memory system 2000 according to the present invention may be implemented in a computer, a portable computer, an UMPC (Ultra Mobile PC), a workstation, a netbook, a PDA, a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, a digital camera, a digital audio recorder, a digital audio player, a digital picture recorder, a digital video player, a digital video player, a device capable of transmitting and receiving information in a wireless environment, and a home network, Can be applied.

6 is a block diagram illustrating a data storage device 3000 according to another embodiment of the present invention.

Referring to FIG. 6, the data storage device 3000 according to the present invention may include a resistance change memory 3100 and a resistance change controller 3200. The resistance change controller 3200 can control the resistance change memory 3100 based on control signals received from an external circuit of the data storage device 3000. [ The three-dimensional memory array structure of the resistance change memory 3100 can be, for example, a channel stacked structure, a linear BICs structure (straight-shaped Bit Cost Scalable structure), and a pipe-shaped BICs And the structure is illustrative only, and the present invention is not limited thereto.

The data storage device 3000 of the present invention can constitute a memory card device, an SSD device, a multimedia card device, an SD card, a memory stick device, a hard disk drive device, a hybrid drive device, or a universal serial bus ferroelectric memory device. For example, the data storage device 3000 of the present invention may be a memory card that meets standards or specifications for using electronic devices such as digital, camera, or personal computers.

FIG. 7 is a block diagram illustrating a resistance-change memory device 4100 and a computing system 4000 including the same according to an embodiment of the present invention.

7, a computing system 4000 in accordance with the present invention includes a resistance change memory element 4100 electrically coupled to a bus 4400, a memory controller 4200, a modem 4300, such as a baseband chipset, ), A microprocessor 4500, and a user interface 4600.

The resistance-change memory element 4100 shown in Fig. 6 may be the resistance-change memory element described above. The computing system 4000 according to the present invention may be a mobile device, in which case a battery 4700 may be further provided for supplying the operating voltage of the computing system 4000. Although not shown, an application chipset, a camera image processor (CIS), or a mobile DRAM may be further provided in the computing system according to the present invention. The memory controller 4200 and the resistance change memory element 4100 can constitute, for example, a solid state drive / disk (SSD) using a resistance change memory element for storing data.

The resistance change memory element and / or the memory controller according to the present invention can be mounted using various types of packages. For example, the ferroelectric memory device and / or the memory controller according to the present invention can be implemented as a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PLCC) Linear Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WSP). ≪ / RTI >

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It will be clear to those who have knowledge.

10: Resistance change memory element
EL1: first electrode
EL2: second electrode
RE: resistance change material layer

Claims (8)

An oxidizable first electrode;
A resistance change material layer disposed on the first electrode, the resistance change material layer having a perovskite crystal structure represented by Chemical Formula 1 and having a metal insulator transition characteristic and a rectification characteristic of a diode; And
And a second electrode disposed on the resistance change material layer,
The resistance value of the resistance change material layer is controlled according to the oxygen concentration in the resistance change material layer, thereby determining the metal insulator transition characteristic,
Wherein the resistance change material layer has an initial state of a low resistance state in which oxygen ions are excessively supplied,
Wherein the metal insulator transition characteristic is such that when a positive voltage is applied to the first electrode, the oxygen ions in the resistance change material layer migrate to the first electrode, the oxygen ion concentration decreases, and the oxygen ion concentration decreases, State to a high-resistance state, and when a negative voltage is applied to the first electrode, oxygen ions in the first electrode move to the resistance change material layer to increase the oxygen ion concentration, and the oxygen concentration increases The high resistance state is transited to the low resistance state,
The rectification characteristic of the diode is determined according to the polarization of the resistance change material layer,
Wherein the resistance change material layer comprises any one of LaTiO ₃ , LaNiO ₃ , LaCuO ₃ , LaScO ₃ , LaVO ₃ , LaMnO ₃ , and LaCrO ₃ ;
[Chemical Formula 1]
AMO ₃ (where A is a lanthanide element, M is a transition metal element, and O is an oxygen element). The method according to claim 1,
Wherein the first electrode comprises a reactive metal capable of being oxidized, the electrode comprising titanium (Ti), tungsten (W), aluminum (Al), or an alloy thereof,
Wherein the second electrode comprises platinum (Pt), iridium (Ir), palladium (Pd), gold (Au), ruthenium (Ru), or an alloy thereof as a non-reactive noble metal. The method according to claim 1,
Wherein the adjustment of the resistance value is performed through band gap adjustment of the resistance change material layer. The method according to claim 1,
Wherein the metal insulator transition comprises a mott transition. The method according to claim 1,
An energy barrier is formed at an interface between the first electrode and the resistance change material layer when a positive voltage is applied to the first electrode. When a negative voltage is applied to the first electrode, And a diode characteristic is determined by eliminating the energy barrier at the interface between the resistance change memory element and the resistance change memory element. The method of claim 1, wherein
Wherein a Schottky barrier layer is disposed at an interface between at least one of the first electrode and the second electrode and the resistance change material layer. A semiconductor memory device having a cross point structure of memory cells including the resistance-variable memory element according to claim 1 as an information storage element. Forming an oxidizable first electrode;
Forming a resistance change material layer having a perovskite crystal structure represented by the following Chemical Formula 2 on the first electrode and having a metal insulator transition characteristic and a diode rectification characteristic; And
And forming a second electrode disposed on the resistance change material layer,
The resistance value of the resistance change material layer is controlled according to the oxygen concentration in the resistance change material layer, thereby determining the metal insulator transition characteristic,
Wherein the resistance change material layer has an initial state of a low resistance state in which oxygen ions are excessively supplied,
Wherein the metal insulator transition characteristic is such that when a positive voltage is applied to the first electrode, the oxygen ions in the resistance change material layer migrate to the first electrode, the oxygen ion concentration decreases, and the oxygen ion concentration decreases, State to a high-resistance state, and when a negative voltage is applied to the first electrode, oxygen ions in the first electrode move to the resistance change material layer to increase the oxygen ion concentration, and the oxygen concentration increases The high resistance state is transited to the low resistance state,
The rectification characteristic of the diode is determined according to the polarization of the resistance change material layer,
Wherein the resistance change material layer comprises any one of LaTiO ₃ , LaNiO ₃ , LaCuO ₃ , LaScO ₃ , LaVO ₃ , LaMnO ₃ , and LaCrO ₃ ;
(2)
AMO ₃ (where A is a lanthanide element, M is a transition metal element, and O is an oxygen element).

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