JP2013135065A - Resistance change type memory element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a resistance change type memory element capable of improving reliability and memory holding characteristics of switching operations at On/Off.SOLUTION: A resistance change type memory element comprises: a lower electrode 11 and an upper electrode 12, a trap layer 13 that is disposed between the lower electrode 11 and the upper electrode 12 and includes a conductive dot 13a; a tunnel layer 14 disposed between the lower electrode 11 and the trap layer 13; and a tunnel layer 15 disposed between the upper electrode 12 and the trap layer 13.

Description

  Embodiments described herein relate generally to a two-terminal variable resistance memory element having a switching layer whose resistance value is electrically variable.

  As a semiconductor nonvolatile memory for data storage, a NOR type or NAND type flash memory is generally used. However, in these semiconductor nonvolatile memories, the limit of miniaturization is pointed out because a large voltage is required for writing and erasing and the number of electrons injected into the floating gate is limited.

  At present, resistance variable memory devices such as PMC (Programmable Metallization Cell) and ReRAM (Resistance Random Access Memory) have been proposed as next-generation nonvolatile memories because they may surpass the bit cost of flash memory.

  For example, a memory element using an ion conduction phenomenon (hereinafter referred to as an ion conduction memory) is known as one of resistance change type memory elements. The ion conduction memory has a stacked structure in which a high-resistance layer is sandwiched between an electrode containing mobile ions and an electrode containing no mobile ions.

  Among ion-conducting memories, for example, a memory in which amorphous silicon (a-Si) is used as a high resistance layer and silver (Ag) element is used as a movable ion has a high switching probability and can be miniaturized. Many proposals have been made based on sex. In this ion conduction memory, the metal of the electrode moved into the amorphous layer forms a conductive path, and a memory function is generated by the magnitude of resistance due to the formation of the conductive path.

  However, although the on state and the off state are confirmed in the switching characteristics, how the metal conductive path is formed and what structure is formed in the high resistance layer to form the on state and the off state. However, direct experimental observation has not been obtained. That is, the formation mechanism of the conductive path has not been clarified yet. Therefore, it is difficult to control the formation and position of the conductive path, and it is difficult to control the on / off resistance ratio, writing, erasing, and reading voltage and current conditions.

  Further, the data retention characteristic of the ion conduction memory is only four years, which is insufficient as a nonvolatile memory element. This is considered because the ionic metal path easily moves during data holding or data reading and the data holding state is unstable.

JP 2011-216146 A

  Provided is a resistance change type memory element capable of improving the reliability of switching operation and memory retention characteristics during on / off.

  In one embodiment, the resistance change type memory device includes first and second electrodes, a first trap layer disposed between the first electrode and the second electrode, and adjacent to a conductive dot, and the first trap layer. A first tunnel layer disposed between an electrode and the first trap layer; and a second tunnel layer disposed between the second electrode and the first trap layer. .

It is a figure which shows the IV characteristic in the ion conduction memory which has a laminated structure of a silicon substrate / a-Si layer / Ag nanoprobe. It is sectional drawing which shows the structure of the resistance change memory element of 1st Embodiment. FIG. 3 is a cross-sectional view illustrating a switching operation of the resistance change type memory element according to the first embodiment. FIG. 3 is a cross-sectional view illustrating a switching operation of the resistance change type memory element according to the first embodiment. It is a figure which shows the write-in characteristic of the resistance change type memory element of 1st Embodiment. It is a figure which shows the read-out characteristic of the resistance change type memory element of 1st Embodiment. It is sectional drawing which shows the manufacturing method of the resistance change type memory element of 1st Embodiment. It is sectional drawing which shows the manufacturing method of the resistance change type memory element of 1st Embodiment. It is sectional drawing which shows the structure of the resistance change memory element of the 1st modification of 1st Embodiment. It is sectional drawing which shows the structure of the resistance change memory element of the 2nd modification of 1st Embodiment. It is sectional drawing which shows the structure of the resistance change type memory element of 2nd Embodiment. It is sectional drawing which shows the switching operation | movement of the resistance change memory element of 2nd Embodiment. It is sectional drawing which shows the switching operation | movement of the resistance change memory element of 2nd Embodiment. It is sectional drawing which shows the switching operation | movement of the resistance change memory element of 2nd Embodiment. It is sectional drawing which shows the switching operation | movement of the resistance change memory element of 2nd Embodiment. It is a figure which shows the write-in characteristic of the resistance change type memory element of 2nd Embodiment. It is a figure which shows the read-out characteristic of the resistance change type memory element of 2nd Embodiment. It is a circuit diagram which shows the structure of the non-volatile semiconductor memory of 3rd Embodiment. FIG. 19 is a perspective view illustrating a structure of the memory cell array illustrated in FIG. 18.

  Before describing the embodiment, first, the inventors of the present application first made an experimental result and obtained by microscopically examining the mechanism of the ion conduction memory using conductive atomic force microscopy (CAFM). I will describe the new findings.

  The element structure of the ion conduction memory is a silicon substrate / a-Si layer / Ag nanoprobe in which an Ag nanoprobe for CAFM measurement is used instead of the Ag electrode in a laminated structure of silicon substrate / a-Si layer / Ag electrode. It was set as the laminated structure. That is, a structure in which an a-Si layer was stacked on a silicon substrate and an Ag nanoprobe was brought into contact with the a-Si was used. In this structure, the Ag nanoprobe was grounded, and a negative voltage was applied to the silicon substrate side, whereby the current-voltage characteristics (hereinafter referred to as IV characteristics) at local locations were obtained using CAFM.

  FIG. 1 is a diagram showing IV characteristics in an ion conduction memory having a laminated structure of silicon substrate / a-Si layer / Ag nanoprobe.

  In the IV characteristic shown in FIG. 1, an increase in current that increases stepwise, which is not observed in a macro device, was observed. The characteristics of this current increase can be explained as follows.

  First, the reason why the current rises vertically by one digit or more near the voltage of −4 V is that the resistance of the a-Si layer changes to a low resistance for the following reason. Ag atoms supplied from the Ag nanoprobe are ionized by a negative voltage applied to the substrate to become Ag ions and migrate into the a-Si layer.

  Then, Ag ions in the a-Si layer meet electrons trapped at the trap site in the a-Si layer, are reduced to Ag dots, and are deposited at the trap site. The deposited Ag dots form a conductive path, and the resistance of the a-Si layer changes to a low resistance.

Here, in the voltage region where the voltage is from −4 to −4.5 V, there is a phenomenon in which the current is constant even though the voltage is increasing. This is an indication that when electrons tunnel through Ag dots using a conductive path, the size of the Ag dots is extremely small, so that a Coulomb blockade phenomenon, that is, a so-called single electron tunneling phenomenon occurs in the current. That is, in order for electrons to tunnel the conductive path, it is necessary to store energy for ΔEc = e ² / 2C. When the size of the Ag dots is extremely small, the capacity C is small and ΔEc is so large that it cannot be ignored. From FIG. 1, it can be said that the size of the Ag dots is extremely small because a region where the current does not increase, which is considered to be a Coulomb blockade phenomenon, is observed.

  From the above IV characteristics, the inventors of the present application have found that the writing process of the ion conduction memory is a composite phenomenon of the migration of Ag ions to the trap site, the precipitation of Ag, and the single electron tunneling phenomenon. .

  Further, when the voltage is further increased, electrons are trapped at a new trap site, and Ag ions are also trapped and reduced to Ag dots. As described above, the inventors have also experimentally found that ion migration, Ag precipitation, and single electron tunneling are repeated.

  From the above experimental results, the process of decreasing the resistance of the a-Si layer when the Ag nanoprobe is used is considered as follows.

  First, electrons are trapped at a trap site of the a-Si layer by applying a voltage. Next, neutral Ag particles are ionized by voltage application. Next, the ionized Ag ions are trapped at the electron sites trapped in the a-Si layer, and are reduced to neutral Ag dots by the electrons. Then, an island of Ag dots is formed in the a-Si layer, which forms a conductive path, and switches the resistance of the a-Si layer from the high resistance state to the low resistance state.

  However, from the IV characteristic curve of FIG. 1, in the voltage range of −4.5 to −5 V, it is observed that the current value is not flat but has a large variation, and the current value is unstable. Has been.

  This suggests that the Ag dots forming the conductive path are not in a stable state in the film and are moving during the switching operation. The inventors of the present application have found that the unstable position of the Ag dots in the a-Si layer is due to an insufficient trap function of the trap site for trapping the Ag dots. In other words, in order to obtain stable writing and memory retention characteristics, it is necessary to design a trap site so that Ag dots do not move.

  The inventors of the present invention use an a-Si layer in a conventional ion conduction memory, and switch resistance by utilizing migration of metal ions into the a-Si layer. I found out that

  (1) In the ON state (low resistance state), both ionizable conductive dots (hereinafter referred to as conductive dots) and electrons easily move, and the memory retention characteristics are insufficient. Therefore, a film structure that blocks the movement of electrons and conductive dots in the on state is required.

  (2) During the reset operation, the movement of the conductive dots is not preferable for increasing the operation speed of the device. Therefore, a structure that can block the movement of conductive dots during reset operation and moves only electrons is required.

  (3) Since the arrangement of conductive dots is random and the switching resistance varies, multilevel control is difficult. Therefore, it is necessary to control the conductive dots at the same interval in the film stacking direction.

  The embodiments described below have been made in view of the above-described problems, can improve the reliability and memory retention characteristics of the switching operation during on / off, and can further improve the multivalue of three or more values of the memory element. Can be realized.

  Hereinafter, a resistance change type memory element according to an embodiment will be described with reference to the drawings. In the following description, components having the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

[First Embodiment]
The resistance change type memory element according to the first embodiment will be described in the order of the memory element structure, the switching operation principle, and the manufacturing method.

[1] Memory Element Structure First, the structure of the resistance change type memory element will be described.

  FIG. 2 is a cross-sectional view showing the structure of the resistance change memory element according to the first embodiment.

  The resistance change memory element includes a lower electrode (first electrode) 11, an upper electrode (second electrode) 12, and a variable resistance unit 16 disposed between the lower electrode 11 and the upper electrode 12. The variable resistance unit 16 includes a high resistance trap layer 13, a first high resistance tunnel layer 14, and a second high resistance tunnel layer 15.

  A trap layer 13 is disposed between the lower electrode 11 and the upper electrode 12. The trap layer 13 includes conductive dots 13a. A first tunnel layer 14 is arranged between the lower electrode 11 and the trap layer 13. A second tunnel layer 15 is disposed between the upper electrode 12 and the trap layer 13. That is, a structure in which the first tunnel layer 14, the trap layer 13, and the second tunnel layer 15 are stacked in this order from the lower electrode 11 side is disposed between the lower electrode 11 and the upper electrode 12. .

  The lower electrode 11 is formed of a semiconductor layer, for example, a silicon layer doped with boron. The upper electrode 12 is made of, for example, a single metal such as Pt, W, Ru, or Rh, a metal silicide such as PtSi or WSi, a metal carbide such as WxC, TaC, or TiC, or a metal nitride such as TiN or TaN.

  The trap layer 13 is formed of a film capable of trapping the conductive dots 13a, for example, a film having a high dielectric constant (High-k insulating film). Conductive dots 13 a are arranged in the trap layer 13. The high-k insulating film is formed of, for example, a silicon nitride film or a silicon oxynitride film, hafnium oxide, titanium oxide, hafnium silicate, or titanium silicate. The conductive dot is an aggregate of a plurality of atoms or molecules, and includes conductive fine particles or clusters.

  The first tunnel layer 14 and the second tunnel layer 15 are layers that can tunnel electrons and block the movement of the conductive dots 13a. The first and second tunnel layers 14 and 15 are made of, for example, a silicon oxide film.

  In the variable resistance memory element having the above structure, the conductive dots 13a are controlled based on the ionization and reduction phenomenon of the ionic metal by controlling the magnitude and polarity of the voltage applied between the lower electrode 11 and the upper electrode 12. Can be selectively controlled. Thereby, the resistance value of the variable resistance part 16 between the lower electrode 11 and the upper electrode 12 can be switched.

[2] Principle of Switching Operation Hereinafter, the principle of switching operation between the low resistance state and the high resistance state in the resistance change type memory element will be described.

  3 and 4 are cross-sectional views showing the switching operation of the resistance change memory element according to the first embodiment. FIG. 5 and FIG. 6 are diagrams showing write characteristics and read characteristics of the resistance change type memory element.

  In the initial state of the resistance change memory element, as shown in FIG. 2, the conductive dots 13a are neutral, and a conductive path is formed as the conductive dots 13a. For this reason, the variable resistance portion 16 is in a low resistance state, and the memory element is in a low resistance state. This low resistance state is an on state (here, “0”), and the high resistance state is an off state (here, “1”).

  In order to bring the memory element into a high resistance state, that is, to turn it off, a voltage for erasing (also called reset) is applied between the lower electrode 11 and the upper electrode 12. That is, as shown in FIG. 3, a negative bias voltage V <b> 1 is applied to the upper electrode 12 with respect to the lower electrode 11. That is, V1 <0V is applied.

  By such an erasing operation, an electric field is generated between the lower electrode 11 and the upper electrode 12, and the conductive dots 13a disposed in the trap layer 13 are ionized by the application of the electric field. When the conductive dots 13a are ionized, electrons tunnel through the tunnel layer 14 and flow to the lower electrode 11, and the ionized conductive dots 13a remain in the trap layer 13 and become charged particles 13b.

  The charged particles 13b that have lost the carriers do not become conductive paths, and the variable resistance portion 16 is in a high resistance state, that is, an off state. When the threshold voltage of the erase operation is Va, the bias voltage V1 is V1 ≦ Va <0V.

  As a feature of the erasing characteristics by the memory element of the present embodiment, the conductive dots 13a are trapped by the trap layer 13 in the variable resistance portion 16, and thus the position is fixed. As shown in FIG. 3, when a voltage is applied in the erasing operation, only electrons flow to the lower electrode 11, and ions that have become charged particles 13b do not move from the trap layer.

  Further, it is necessary to prevent electrons from being supplied from the upper electrode 12 in order to maintain the charged state of the charged particles 13b during voltage application in the erase operation. For this purpose, the following structural measures are taken. The tunnel layer 15 is made thicker than the tunnel layer 14. With this contrivance, the charged particles 13b can be kept charged during the erasing operation, and the high resistance state can be stably maintained.

  Furthermore, when applying a voltage in the erasing operation, only electrons can be tunneled, while the structure of the tunnel layer 14 and the trap layer 13 is devised so that the charged particles 13b do not move. That is, when an erase voltage is applied, electrons are detrapped from the trap layer 13 and the tunnel layer 14 can be tunneled. On the other hand, the charged particles 13b remain trapped in the trap layer 13 without detrapping, and the tunnel layer 14 also has a sufficiently large band gap to block the movement of the charged particles 13b.

  Next, in a write operation for setting the memory element in a low resistance state, a positive bias voltage V2 is applied to the upper electrode 12 with respect to the lower electrode 11, as shown in FIG. Here, V2 ≧ Vb, where Vb is the minimum voltage that can reduce the charged particles 13b to the conductive dots 13a, that is, the minimum voltage that can be switched from the high resistance state to the low resistance state. Electrons are supplied from the lower electrode 11 and tunnel through the tunnel layer 14 to reach the charged particles 13b. The charged particles 13b are reduced and returned to the conductive dots 13a. By this writing operation, the variable resistance unit 16 is brought into a low resistance state (ON state).

  FIG. 5 shows the relationship between the applied voltage and the resistance in the above erase operation and write operation. Further, the reading operation of data stored in the memory element is determined by applying a positive voltage V3 and comparing the obtained resistance value R with the off-state resistance value R1, as shown in FIG. . If the obtained resistance value R is smaller than the resistance value R1, that is, if R <R1, it is determined to be in the on state, and otherwise, it is determined to be in the off state. The voltage V3 is 0V <V3 <Vb.

  As described above, the operation principle of the memory element shown in FIG. 3 and FIG. 4 is based on controlling the charge state of the ionizable conductive dots 13a arranged in the trap layer 13 of the variable resistance unit 16. The resistance value of the memory element is switched. When the conductive dots 13a are neutral metal particles, the resistance becomes low and contributes to the conductive path. However, when the conductive dots 13a are ionized, they exist in the trap layer 13 as charges and become high resistance. Do not form a conductive path. That is, the resistance of the variable resistance portion 16 can be switched by switching between the two states of the conductive dots (neutral metal particles) 13a and the ionized charged particles 13b.

  According to the nonvolatile memory element of this embodiment, in the on state, the conductive dots and electrons are trapped in the trap layer 13, so that the on state memory retention time can be kept long. Further, in the off state, the conductive dots 13a are ionized and exist in the film as electric charges, so there is no conductive path, and the high resistance state can be kept long. Furthermore, since the conductive dots are blocked by the high-resistance wide band gap tunnel film at the time of writing, only electrons can be tunneled without causing the movement of the conductive dots. Thereby, a stable high-speed switching operation between the on state and the off state is possible.

  As described above, according to the present embodiment, it is possible to provide a resistance change type memory element capable of improving the reliability of the switching operation during on / off and the memory retention characteristic.

[3] Manufacturing Method and Material Next, a manufacturing method of the resistance change memory element according to the first embodiment will be described.

  Here, for example, a silicon oxide film (SiOx) is used as the high resistance tunnel layer 14, a silicon nitride film (SiNx) is used as the high resistance trap layer 13, and a silicon oxide film is used as the high resistance tunnel layer 15. A method for manufacturing a memory element using (SiOx) and arranging Ag dots as the conductive dots 13a in the silicon nitride film 13 will be described as an example. The variable resistance portion 16 has a laminated structure of silicon oxide film 14 / silicon nitride film (including Ag dots 13a) 13 / silicon oxide film 15.

  7 and 8 are cross-sectional views illustrating the method of manufacturing the resistance change memory element according to the first embodiment.

  As shown in FIG. 7A, first, the lower electrode 11 is formed on the silicon semiconductor substrate 10 by doping, for example, boron. In this case, if the resistivity of the lower electrode 11 is in the range of 10 to 0.0001 Ωcm, it can be used as the lower electrode. For boron doping, for example, an ion implantation method or a coating method using a liquid diffusion source can be used.

  Next, as shown in FIG. 7B, for example, a silicon oxide film is formed on the lower electrode 11 as the first high-resistance tunnel layer 14. The thickness of the silicon oxide film 14 is, for example, 1 to 3 nm. The method for forming the silicon oxide film 14 may be a normal thermal oxidation method or a deposition method using a gas source such as CVD. Moreover, it is not restricted to these methods.

  Next, as shown in FIG. 7C, a silicon nitride film including, for example, Ag dots 13 a is formed on the silicon oxide film 14 as the trap layer 13. The film thickness of the silicon nitride film 13 is, for example, about 2 nm.

  The film forming method of the silicon nitride film 13 including the Ag dots 13a may be a method of forming a silicon nitride film and then depositing and aggregating a thin film containing Ag, or the Ag dots may be formed when forming the silicon nitride film. You may use the method of adding. Further, after the silicon nitride film is formed, Ag may be introduced into the silicon nitride film by ion implantation.

  A method of depositing and aggregating a thin film containing Ag after forming the silicon nitride film 13 is performed as follows.

  A silicon nitride film 13 is formed on the silicon oxide film 14. The method for forming the silicon nitride film 13 may be a CVD method or a method using a target such as a sputtering method. Moreover, it is not restricted to these methods. Subsequently, for example, an Ag nano-coating liquid is applied as an organic film containing Ag on the silicon nitride film 13.

  Thereafter, the Ag dots 13a are aggregated as nanodots having a particle diameter Φ of about 2 nm, and heat treatment is applied at an appropriate annealing temperature such that the distance between the Ag dots 13a is 3 nm or more in the surface. The temperature and time of the heat treatment differ depending on the components of the nano coating liquid, and the Ag dots 13a are always arranged in the silicon nitride film 13 under the optimum heat treatment conditions suitable for the material. By this heat treatment, the Ag dots 13 a are trapped in the silicon nitride film 13.

  As another manufacturing method, when the silicon nitride film 13 is formed, a method of adding the Ag dots 13a is performed as follows.

  When the silicon nitride film 13 and the Ag dots 13a are formed at the same time, for example, a sputtering method can be used. Using a silicon nitride film target and a Ag-containing target, the sputtering conditions are optimized so that the Ag dots 13 a are trapped in the silicon nitride film 13. Thereby, the silicon nitride film 13 containing the Ag dots 13a can be formed.

  Next, as shown in FIG. 8A, for example, a silicon oxide film is formed on the silicon nitride film 13 as the second high-resistance tunnel layer 15. The silicon oxide film 15 is thicker than the silicon oxide film 14. For example, the thickness of the silicon oxide film 15 is about 1 nm thicker than the thickness of the silicon oxide film 14. When the thickness of the silicon oxide film 14 is 1 nm, the thickness of the silicon oxide film 15 is 2 nm. When the thickness of the silicon oxide film 14 is 3 nm, the thickness of the silicon oxide film 15 is 4 nm. The formation method of the silicon oxide film 15 is the same as that of the first silicon oxide film 14.

  Next, as shown in FIG. 8B, an Ag layer, for example, is formed as an upper electrode 12 on the silicon oxide film 15 by a vacuum deposition method or the like. The resistance change type memory element according to the first embodiment is manufactured through the above steps.

  Next, materials constituting the resistance change type memory element of the first embodiment will be described in detail.

  First, the electrode material constituting the lower electrode 11 will be described. It is required that electrons are injected from the lower electrode 11 through the tunnel layer 14 into the trap layer 13 during the write operation, and positive carrier holes are injected from the lower electrode 11 into the trap site of the trap layer 13 during the erase operation. From this, the lower electrode 11 can be formed from, for example, a p-conductivity type silicon semiconductor substrate doped with boron. If the writing and erasing operations can be realized, the lower electrode 11 is not limited to silicon, and other semiconductor materials or metal electrode materials may be used.

Next, materials constituting the first high-resistance tunnel layer 14 will be described. At the time of writing, electrons are provided from the lower electrode 11 and the tunnel layer 14 is required to be tunneled. For this reason, it is required that a current of 1 × 10 ⁻¹³ A or more can flow through the tunnel layer 14 when a voltage is applied.

  For example, when a silicon oxide film is used as the tunnel layer 14, a current flows based on FN tunneling, and the thickness of the silicon oxide film 14 is desirably 5 nm or less. Further, in order to keep the leakage current sufficiently small in the memory retention state, the film thickness of the silicon oxide film 14 is set to 1.5 nm or more so that tunneling called direct tunneling does not occur. That is, for example, when a silicon oxide film is used as the tunnel layer 14, the film thickness of the silicon oxide film is desirably 1.5 to 5 nm.

  In this embodiment, a silicon oxide film is used for the tunnel layer 14. However, a high-k insulating film having a dielectric constant higher than that of the silicon oxide film can be used in combination with the trap layer 13. Examples of the high-k insulating film include a silicon oxynitride film, a silicon nitride film, a metal oxide film, and a metal oxynitride film. When a high-k insulating film is used, the equivalent oxide film thickness (EOT) may be the same as that when a silicon oxide film is used.

  Next, materials constituting the high resistance trap layer 13 will be described. The trap layer 13 is required to have a sufficiently deep energy level so that the conductive dots 13a cannot move while being trapped during the write and erase operations. On the other hand, the energy level for trapping or detrapping electrons during write and erase operations must be at a reasonable level.

  When, for example, a silicon nitride film is used as the trap layer 13, the trap level and density in the silicon nitride film 13 can be adjusted by the composition ratio of the silicon nitride film and the amount of gas added at the time of formation. It is also possible to adjust according to the thickness and the size of the Ag dot 13a.

  In the present embodiment, a silicon nitride film is used as the trap layer 13. However, if the trap function can be achieved, a material having another trap function, for example, a metal oxide such as hafnium oxide, hafnium oxynitride, or the like. Metal oxynitride, silicon oxynitride, amorphous silicon, or the like may be used. Furthermore, according to the principle of the present embodiment, if sites that can be trapped can be formed in the variable resistance portion, the conductive dots 13a are trapped in these trap sites to form a conductive path.

  Therefore, the trap sites are not limited to layers, and the arrangement of trap sites may be discrete as long as a conductive path is formed by the conductive dots 13a in the variable resistance portion, and element addition to the variable resistance portion is possible. Can also be realized.

  Next, materials constituting the conductive dots 13a will be described. At the time of writing, the ionized conductive dots need to receive electrons and be reduced to the conductive dots 13a. On the other hand, at the time of erasing, the conductive dots 13a are required to be ionized and remain in the trap layer 13 as charged particles 13b. For this reason, the conductive dots 13a need to be conductive dots that can be ionized.

  For this reason, for example, an Ag dot is used as the conductive dot 13a, but the present invention is not limited to this, and any metal dot that can be ionized and reduced by applying a voltage or a current may be used. One of Au, Cr, Cu, Ti, and Ni, or an alloy containing these or a compound such as silicide containing these may be used.

Next, materials constituting the second high resistance tunnel layer 15 will be described. At the time of writing, electrons are provided from the lower electrode 11 and it is required to tunnel the tunnel layer 15. For this reason, it is required that a current of 1 × 10 ⁻¹³ A or more can flow through the tunnel layer 15 when a voltage is applied. For example, when a silicon oxide film is used as the tunnel layer 15, a current flows based on the FN tunnel ring, and the thickness of the silicon oxide film 15 is preferably 5 nm or less.

  On the other hand, at the time of erasing, in order to keep the ionized conductive dots as charged particles 13b, it is necessary to make the silicon oxide film 15 sufficiently thick so that electrons are not supplied from the upper electrode 12 to the trap layer 13. is there. Therefore, for example, the film thickness of the silicon oxide film 15 is thicker than the silicon oxide film 14 and smaller than 5 nm, and the thickness in the vicinity of 4 nm is appropriate.

  In this embodiment, a silicon oxide film is used for the tunnel layer 15. However, for example, a high-k insulating film other than the silicon oxide film can be used in combination with the trap layer 13. When a high-k insulating film is used, the equivalent oxide thickness (EOT) may be the same as that when a silicon oxide film is used.

  Further, in the present embodiment, an example in which a silicon oxide film is used as the tunnel layers 14 and 15 is shown, and it has been described that the film thickness of the silicon oxide film 14 is preferably smaller than that of the silicon oxide film 15. Another material may be used as long as the barrier height is lower than the barrier height of the tunnel layer 15. For example, the tunnel layer 14 may be formed from a hafnium oxide film, and the tunnel layer 15 may be formed from a silicon oxide film. In this case, the thickness of the hafnium oxide film may be greater than that of the silicon oxide film.

  Next, the electrode material constituting the upper electrode 12 will be described. The upper electrode 12 may not be a material constituting the conductive dots. That is, even when Ag dots are used as the conductive dots 13a, the upper electrode 12 may not be Ag. For example, Ta, Al, Au, Cr, Cu, Ti, Ni, Cu, Ti, Co, Nb, W One of Cr, an alloy containing these, or a compound such as silicide containing these may be used.

  Next, a resistance change memory element according to a modification of the first embodiment will be described.

  FIG. 9 is a cross-sectional view showing the structure of the resistance change memory element according to the first modification.

  In the first embodiment described above, the trap layer 13 includes the conductive dots 13a. However, in the first modification, the structure in which the thickness of the high resistance trap layer 17 is smaller than the particle size of the conductive dots 13a. Indicates. Here, although the case where the trap layer 17 forms a layer is shown, the trap layer 17 does not necessarily have to be formed.

  As shown in FIG. 9, the resistance change memory element includes a lower electrode 11, an upper electrode 12, tunnel layers 14 and 15, a trap layer 17, and conductive dots 13a. The trap layer 17 is disposed between the tunnel layer 14 and the tunnel layer 15. The conductive dots 13 a are disposed in the vicinity of the trap layer 17. That is, the conductive dots 13a do not have to be arranged in the trap layer 17, and it is sufficient that the trap layer 17 and the conductive dots 13a are close to each other.

  As in the first embodiment, the trap layer 17 is formed of, for example, a silicon nitride film, a metal oxide such as hafnium oxide, a metal oxynitride such as hafnium oxynitride, silicon oxynitride, or amorphous silicon.

  The thickness of the trap layer 17 is less than 2 nm, and the particle size of the conductive dots 13a is about 1 nm to 4 nm. Other configurations and effects are the same as those of the first embodiment described above.

  FIG. 10 is a cross-sectional view showing the structure of the resistance change memory element according to the second modification.

  In the first embodiment described above, an example in which the trap layer 13 and the tunnel layers 14 and 15 are formed as separate layers has been described. However, in the second modification, an example in which these layers are formed in one layer is illustrated.

  As shown in FIG. 10A, the resistance change memory element includes a lower electrode 11, an upper electrode 12, a high resistance tunnel layer 18, and conductive dots 13a. The tunnel layer 18 is disposed between the lower electrode 11 and the upper electrode 12. The conductive dots 13 a are disposed in the tunnel layer 18.

  The tunnel layer 18 is formed from, for example, a silicon oxynitride film 18. The concentration distribution of nitrogen in the silicon oxynitride film 18 is shown in FIG. The horizontal axis indicates the nitrogen concentration, and the vertical axis indicates the position of the silicon oxynitride film 18 in the thickness direction. The concentration peak of nitrogen in the silicon oxynitride film 18 is slightly below the center in the thickness direction. The conductive dots 13a are arranged in the vicinity of the nitrogen concentration peak. Nitrogen added to the silicon oxide film functions as a trap site.

  In the second modification, a silicon oxynitride film in which nitrogen is added to the silicon oxide film is used as the tunnel layer 18, but a film in which fluorine, silicon, or a metal element is added to the silicon oxide film may be used. good. These elements are added by, for example, an ion implantation method.

  Other configurations and effects are the same as those of the first embodiment described above.

[Second Embodiment]
In the second embodiment, an example will be described in which a plurality of variable resistance portions are stacked in order to form a multi-value memory element. The resistance change type memory element according to the second embodiment will be described in the order of the memory element structure, the switching operation principle, and the manufacturing method. In addition, since the material which comprises the resistance change type memory element of 2nd Embodiment is the same as that of 1st Embodiment, description is abbreviate | omitted.

[1] Memory Element Structure First, the structure of the resistance change type memory element will be described.

  FIG. 11 is a cross-sectional view showing the structure of the resistance change memory element according to the second embodiment.

  The resistance change memory element includes a lower electrode 11, an upper electrode 12, and a variable resistance unit 26 disposed between the lower electrode 11 and the upper electrode 12. The variable resistance section 26 has a structure in which high resistance tunnel layers 14-n and high resistance trap layers 13-n are alternately stacked. n represents a natural number of 1 or more.

  The trap layer 13-n includes conductive dots 13a-n that can be ionized. That is, conductive dots 13a-n that can be ionized are arranged in the trap layer 13-n.

  A structure in which a trap layer 13-n is sandwiched between upper and lower tunnel layers 14-n, 14- (n + 1), that is, a stacked structure of a tunnel layer 14-n, a trap layer 13-n, and a tunnel layer 14- (n + 1). One variable resistor 16-n is used. The variable resistance section 26 has a structure in which n layers of variable resistance sections 16-n are stacked, that is, as shown in FIG. 11, the variable resistance sections 16-1, 16-2,. It has a structure in which it is laminated toward the upper electrode 12.

  In the variable resistance memory element having the above structure, the conductive dots 13a are controlled based on the ionization and reduction phenomenon of the ionic metal by controlling the magnitude and polarity of the voltage applied between the lower electrode 11 and the upper electrode 12. The charge state of −n can be selectively controlled. Thereby, the lower electrode 11 and the upper electrode 12 can be switched to n + 1 resistance values, and a multi-value memory element having n + 1 values can be realized.

  In the second embodiment, it is necessary to apply a large voltage between the lower electrode 11 and the upper electrode 12 as compared with the first embodiment in which the variable resistance portion is one layer. Therefore, for example, a silicon nitride film having a high trap function is preferably used for the trap layer 13-n so that the conductive dots 13a do not escape from the trap layer 13-n, and an ion source is used for the upper electrode 12. It is preferable to use a metal that does not come out, such as Pt.

[2] Switching Operation Principle In the first embodiment, as described above, based on the mechanism of ionization and reduction phenomenon of the conductive dots 13a, the operation principle of the memory element when the variable resistance portion is one layer, that is, n = 1. Explained.

  Also in the second embodiment, based on the mechanism of ionization and reduction phenomenon of the same conductive dots 13a-n, in the memory element composed of the variable resistance portion stacked on the n layer, it is arranged in each trap layer 13-n. By selectively controlling the ionization and reduction states of the conductive dots 13a-n, the ON state can be controlled to n + 1 resistance values. Thereby, the lower electrode 11 and the upper electrode 12 can be switched to n + 1 resistance values, and a multi-value memory element having n + 1 values can be realized.

  Hereinafter, the operation principle of the memory element when the variable resistance unit 16-n has two or more layers (n> 1) will be described. Here, in order to make the explanation easy to understand, the operation principle of the memory element in the case of n = 2 will be described.

  12 to 15 are cross-sectional views showing the switching operation of the resistance change memory element according to the second embodiment. FIG. 16 and FIG. 17 are diagrams showing write characteristics and read characteristics of the resistance change type memory element.

  As shown in FIG. 12, the memory element in the case where the variable resistance portion 16-n has two layers has a high resistance trap layer 13 including a high resistance tunnel layer 14-1 and conductive dots 13a-1 on the lower electrode 11, as shown in FIG. -1, the high resistance tunnel layer 14-2, the high resistance trap layer 13-2 including the conductive dots 13a-2, the high resistance tunnel layer 14-3, and the upper electrode 12 are sequentially stacked. The laminated structure sandwiched between the lower electrode 11 and the upper electrode 12 functions as the variable resistance section 26, and the variable resistance section 26 is composed of two layers of variable resistance sections 16-1 and 16-2.

  In the initial state of the resistance change memory element having the above structure, the conductive dots 13a-1 and 13a-2 disposed in the trap layers 13-1 and 13-2 are neutral, and the conductive path is formed as a metallic dot. Form. For this reason, the two layers of variable resistance portions 16-1 and 16-2 are both in a low resistance state. That is, the variable resistance unit 26 is in a low resistance state. This low resistance state is defined as “00” in the case of n = 2.

  As in the case of n = 1, the principle of the erase operation is that a negative bias voltage V4 is applied to the upper electrode 12 with respect to the lower electrode 11 as shown in FIG. That is, V4 <0V is applied. By such an erasing operation, an electric field is generated between the lower electrode 11 and the upper electrode 12, and the conductive dots 13a-1 and 13a-2 disposed in the trap layers 13-1 and 13-2 are all ionized by the application of the electric field. Is done. For this reason, electrons tunnel through the tunnel layers 14-1 and 14-2 and flow to the lower electrode 11. On the other hand, the ionized conductive dots remain in the trap layers 13-1 and 13-2, and these become the charged particles 13b-1 and 13b-2.

  At this time, the charged particles 13b-1 and 13b-2 that have lost carriers do not become conductive paths, and the variable resistance portion 26 is in a high resistance state, that is, in an off state. This off state is assumed to be “11”. If the threshold voltage of the erase operation is Vc, the bias voltage V4 is V4 ≦ Vc <0V.

  On the other hand, in the write operation for setting the low resistance state, unlike the case where the variable resistance portion is for one layer, that is, n = 1, the write operation is performed so that the ON state becomes binary. First, as shown in FIG. 14, a positive bias voltage V <b> 5 is applied to the upper electrode 12 with respect to the lower electrode 11.

  Here, the first trap layer 13-1 has a minimum voltage that can reduce the charged particles 13b-1 to the conductive dots 13a-1, that is, from a high resistance state (off state) to a first low resistance state (first state). A threshold voltage that can be switched to the ON state is applied. When the threshold voltage is Vd, the bias voltage V5 is V5 ≧ Vd.

  Further, if a threshold voltage that can reduce the charged particles 13b-2 arranged in the second high-resistance trap layer 13-2 to the conductive dots 13a-2 is defined as Ve, Ve> V5 ≧ Vd is established. That is, the charged particles 13b-2 arranged in the second trap layer 13-2 are not reduced to conductive dots, but remain in the trap layer 13-2 as charged particles. This state is defined as a first low resistance state and is set to “01”.

  In this switching, electrons are supplied from the lower electrode 11, tunneled through the first tunnel layer 14-1, and supplied to the charged particles 13b-1 in the first trap layer 13-1. Then, the charged particles 13b-1 are reduced to return to the neutral conductive dots 13a-1.

  Next, a write operation to the second low resistance state (second on state) will be described. This second low resistance state is set to “00”. As shown in FIG. 15, a positive bias voltage V <b> 6 is applied to the upper electrode 12 with respect to the lower electrode 11. Here, the bias voltage V6 is larger than the minimum threshold voltage Ve that can reduce the charged particles 13b-2 in the second trap layer 13-2 to the conductive dots 13a-2, that is, V6> Ve.

  By applying the bias voltage V6, the charged particles 13b-2 arranged in the second trap layer 13-2 are also reduced to the conductive dots 13a-2, and all the variable resistance portions of the two layers are brought into a low resistance state. Thus, the variable resistance unit 26 returns to the second low resistance state.

  FIG. 16 shows the relationship between the applied voltage and the resistance in the above erase operation and write operation. In the data read operation, a positive bias voltage V7 is applied to the upper electrode 12, as shown in FIG. At this time, the voltage V7 does not exceed the threshold voltage Vd of the write operation.

  That is, voltage application is performed in the range of 0V <V7 <Vd, and the resistance value R11 in the off state, the resistance value R01 in the first on state, the resistance value R00 in the second on state, and the obtained resistance value R To determine the data stored in the memory element.

  When the obtained resistance value R is smaller than the resistance value R11 in the off state and is equal to or more than the first resistance value R01 in the on state, that is, R01 ≦ R <R11, it is determined as the first low resistance state. 01 ”.

  Further, when the obtained resistance value R is smaller than the first on-state resistance value R01 and is equal to or greater than the second on-state resistance value R00, that is, R00 ≦ R <R01, it is determined that the second low-resistance state. That is, it is determined as “00”.

  On the other hand, when the obtained resistance value R is equal to or greater than the resistance value R11 in the off state, that is, when R ≧ R11, it is determined that the resistance state is high, that is, “11”.

  As described above, according to the present embodiment, multivalued write, erase, and read operations can be performed.

[3] Manufacturing Method Next, a manufacturing method of the resistance change type memory element according to the second embodiment will be described.

  In the manufacturing method, as shown in FIG. 7C, the tunnel layer 14 and the trap layer 13 are formed on the lower electrode 11, and then the tunnel layer 14 and the trap layer 13 are alternately formed. Other manufacturing methods are the same as those in the first embodiment.

[Third Embodiment]
Next, a nonvolatile semiconductor memory to which the resistance change type memory element according to the first and second embodiments is applied will be described.

  FIG. 18 is a circuit diagram showing a configuration of the nonvolatile semiconductor memory according to the third embodiment.

The memory cell array has a cross point type. The word lines WL _i−1 , WL _i , WL _{i + 1} extend in the X direction, and the bit lines BL _j−1 , BL _j , BL _{j + 1} extend in the Y direction.

One end of each of the word lines WL _i−1 , WL _i , WL _{i + 1} is connected to the word line driver & decoder 31 via a MOS transistor RSW as a selection switch. One end of each of the bit lines BL _j−1 , BL _j , BL _{j + 1} is connected to the bit line driver & decoder & read circuit 32 via a MOS transistor CSW as a selection switch.

Selection signals R _i−1 , R _i and R _{i + 1} for selecting one word line (row) are input to the gate of the MOS transistor RSW. Selection signals C _j−1 , C _j , C _{j + 1} for selecting one bit line (column) are input to the gate of the MOS transistor CSW.

The memory cell 33 is arranged at the intersection of the word lines WL _i−1 , WL _i , WL _{i + 1} and the bit lines BL _j−1 , BL _j , BL _{j + 1,} and constitutes a so-called cross-point type cell array structure. As the memory cell 33, for example, the resistance change type memory element of the first and second embodiments is used.

  Further, a diode 34 for preventing a sneak current during recording / reproduction is added to the memory cell 33.

  FIG. 19 shows the structure of the memory cell array shown in FIG.

On the semiconductor substrate 10, word lines WL _i−1 , WL _i , WL _{i + 1} and bit lines BL _j−1 , BL _j , BL _{j + 1} are arranged, and a memory cell 33 and a diode 34 are connected in series at the intersection of these wirings. Connected.

  Such a cross-point type cell array structure is advantageous for high integration because it is not necessary to individually connect a MOS transistor to the memory cell 33. For example, the memory cells 33 can be stacked to form a three-dimensional memory cell array.

  As described above, the memory cell 33 is the variable resistance memory element according to the first embodiment or the modification thereof and the second embodiment. Accordingly, one memory cell 33 can store binary data or multi-value data of three or more values. In addition to the PN junction diode, a PIN (SIS) diode, MIS diode, MIM diode, or the like can be used as the diode 34.

  The diode 34 can be omitted when the set / reset is changed only by the direction / magnitude of the voltage.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 10 ... Silicon semiconductor substrate, 11 ... Lower electrode (1st electrode), 12 ... Upper electrode (2nd electrode), 13, 13-n ... High resistance trap layer, 13a, 13a-n ... Conductive dot, 13b, 13b -N ... charged particles, 14, 14-n ... high resistance tunnel layer, 15 ... high resistance tunnel layer, 16, 16-n ... variable resistance portion, 17 ... high resistance trap layer, 18 ... high resistance tunnel layer, 26 ... Variable resistor section 31... Word line driver & decoder, 32... Bit line driver & decoder & read circuit, 33... Memory cell, 34.

Claims (5)

First and second electrodes;
A first trap layer disposed between the first electrode and the second electrode and adjacent to the conductive dots;
A first tunnel layer disposed between the first electrode and the first trap layer;
A second tunnel layer disposed between the second electrode and the first trap layer;
A resistance change type memory device comprising:   The resistance change type memory device according to claim 1, wherein the first trap layer includes at least one of a silicon nitride film, a silicon oxynitride film, hafnium oxide, titanium oxide, hafnium silicate, and titanium silicate.   3. The variable resistance memory element according to claim 1, wherein the second electrode includes at least one of Pt, PtSi, W, Ru, Rh, WC, TaC, TiC, TiN, and TaN. A second trap layer disposed between the second tunnel layer and the second electrode and adjacent to the conductive dots;
A third tunnel layer disposed between the second trap layer and the second electrode;
The resistance change memory element according to claim 1, further comprising: First and second electrodes;
A tunnel layer disposed between the first electrode and the second electrode, doped with an element and having conductive dots;
Comprising
The resistance variable memory element, wherein the tunnel layer has a peak of the concentration distribution of the element in the thickness direction, and the conductive dots are arranged in the vicinity of the peak.

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