KR101802293B1 - Non-volatile Resistive Memory Device and Process for Manufacturing the Same - Google Patents

Non-volatile Resistive Memory Device and Process for Manufacturing the Same Download PDF

Info

Publication number
KR101802293B1
KR101802293B1 KR1020140023701A KR20140023701A KR101802293B1 KR 101802293 B1 KR101802293 B1 KR 101802293B1 KR 1020140023701 A KR1020140023701 A KR 1020140023701A KR 20140023701 A KR20140023701 A KR 20140023701A KR 101802293 B1 KR101802293 B1 KR 101802293B1
Authority
KR
South Korea
Prior art keywords
oxide
layer
metal
electrode
metal oxide
Prior art date
Application number
KR1020140023701A
Other languages
Korean (ko)
Other versions
KR20150101866A (en
Inventor
김대형
현택환
손동희
이종하
Original Assignee
서울대학교산학협력단
기초과학연구원
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 서울대학교산학협력단, 기초과학연구원 filed Critical 서울대학교산학협력단
Priority to KR1020140023701A priority Critical patent/KR101802293B1/en
Publication of KR20150101866A publication Critical patent/KR20150101866A/en
Application granted granted Critical
Publication of KR101802293B1 publication Critical patent/KR101802293B1/en

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/14Selection of switching materials
    • H01L45/145Oxides or nitrides
    • H01L45/146Binary metal oxides, e.g. TaOx
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/08Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory based on migration or redistribution of ionic species, e.g. anions, vacancies
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites

Abstract

The present invention relates to a nonvolatile resistance-change memory element and a method of manufacturing the same. More particularly, the present invention relates to a nonvolatile resistance-change memory element comprising a nonconductive layer formed between conductor layers, comprising: a first electrode; A non-conductive layer made of a first metal oxide formed adjacent to the first electrode; A metal nanoparticle layer formed adjacent to the first metal oxide nonconductor layer; A non-conductive layer made of a second metal oxide formed adjacent to the metal nanoparticle layer; And a second electrode formed adjacent to the second metal oxide layer, and a method of manufacturing the same.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a non-volatile resistance-variable memory device,

The present invention relates to a nonvolatile resistance-change memory element and a method of manufacturing the same. More particularly, the present invention relates to a nonvolatile resistance-change memory element comprising a nonconductive layer formed between conductor layers, comprising: a first electrode; A non-conductive layer made of a first metal oxide formed adjacent to the first electrode; A metal nanoparticle layer formed adjacent to the first metal oxide nonconductor layer; A non-conductive layer made of a second metal oxide formed adjacent to the metal nanoparticle layer; And a second electrode formed adjacent to the second metal oxide layer, and a method of manufacturing the same.

Conventional storage techniques (flash memory with floating gate, and DRAM including capacitor and transistor together) are based on storage of charge for inorganic silicon based materials. These techniques for storing the charge will reach the scale limit in the near future. Therefore, research on other methods for storing information is increasing.

Examples of semiconductor memory devices widely used in recent years include dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, and the like. These semiconductor memory devices can be classified into volatile memory devices and non-volatile memory devices. The non-volatile memory device is a memory device that retains the data stored in the memory cell, even if the power supply is interrupted, such as a flash memory or the like.

Resistive Random Access Memory (RRAM) devices, which have been studied since the 1960s, are memory devices that exhibit the characteristic that the resistance state changes to a high resistance or a low resistance state depending on the voltage. Is a memory element that holds a resistance value even when the value changes and the power source after the change is shut off.

The resistance change memory device is based on a resistance switching phenomenon in which a resistance varies depending on a voltage, a resistance change memory device having high integration, fast information input / output speed, and nonvolatile characteristics.

Various kinds of resistance change memory, which are operated through conductive path breakdown and formation, are a principle of storing one or more data bits per memory cell using a change in the resistance value of a metal oxide caused by applying a voltage.

A thin film showing electrical resistance is used as a memory element, and a voltage is applied to flow a current to change the resistance value. In general, data is stored by setting a reset state having a high resistance to 0 and a set state having a low resistance to 1.

The basic structure of the memory cell of the resistance change memory is the same as that of the flash memory. A high density nonvolatile memory having a storage capacity of flash memory level can be realized by constituting memory cells with one memory element. Resistive memory cells can theoretically reduce the volume to 3-4 nm 3 , which is much smaller than for all memory devices based on conventional charge scales.

The RRAM element is generally a metal-insulator-metal (MIM) structure using a metal oxide. When an appropriate electrical signal is applied, the RRAM element is in a state in which the resistance is low state is displayed. The current controlled negative differential resistance (CCNR) or the voltage controlled negative differential resistance (VCNR) may be classified according to the electrical method that implements ON / OFF memory characteristics. In the case of VCNR, the current changes from a large state to a small state as the voltage increases. The ON / OFF memory characteristic can be realized by using a considerably large resistance difference. The switching mechanism that causes this ON / OFF behavior has not yet been clarified.

Korean Patent Application No. 10-2011-0146243 discloses a plasma display panel comprising a first electrode; A second electrode; A variable resistance layer interposed between the first electrode and the second electrode; And a nanoparticle disposed in the variable resistance layer and having a dielectric constant lower than that of the variable resistance layer, and a method of manufacturing the variable resistance memory device.

In the Korean Patent Application No. 10-2011-0146243, the nanoparticles are contained in the variable resistance layer, the first variable resistance layer and the second variable resistance layer are physically contacted with each other, and the nanoparticles are not layered, There is a difference from the present invention.

Korean Patent Application No. 10-2009-0035389 discloses a plasma display panel comprising a first electrode; Conductive nanoparticles positioned on the first electrode; A resistance change material film located on the conductive nanoparticles; And a second electrode positioned on the resistance-change material film, and a method of manufacturing the nonvolatile memory device.

The Korean Patent Application No. 10-2009-0035389 has a difference from the present invention in that the nanoparticles do not have a layered structure and the nanoparticles are contained in the metal oxide film while being in contact with the first electrode .

Korean Patent Registration No. 10-0817752 discloses a nonvolatile memory cell comprising: a first conductive electrode region; A second conductive electrode region; Wherein the metal oxide nanoparticles are arranged between the first conductive electrode region and the second conductive electrode region and contain one or more metal oxide nanoparticles, Wherein the metal oxide nanoparticles exhibit bistable resistance when an external voltage is applied, the metal oxide nanoparticles are NiO 1 -x nanoparticles, and x is 0.5 To 0.95, and a method of manufacturing the non-volatile memory cell.

The Korean Patent No. 10-0817752 discloses that the nanoparticle is a metal oxide other than a metal and that the nanoparticles are in contact with the upper electrode and the lower electrode and that the nanoparticles are contained in the insulating layer There is a difference from the present invention.

Korean Patent No. 10-1295888 discloses a method of manufacturing a thin film transistor comprising a first electrode on a substrate; An electron channel layer located on the first electrode; And a second electrode on the electron channel layer, wherein an upper surface of the electron channel layer at a lower portion of the second electrode protrudes toward the second electrode, and a method of manufacturing the same .

The Korean Patent No. 10-1295888 discloses that the organic thin film layer is used and the electron channel layer is formed by including the nanoparticles in the organic thin film layer and the nanoparticles do not form a layer, Lt; / RTI >

The present inventors have completed the present invention in view of the fact that a driving current of a resistance variable memory element can be remarkably reduced by forming a metal nanoparticle layer between metal oxide nonconductor layers.

In particular, the metal nanoparticle layer can be formed by Langmuir-Blodgett assembly, layer-by-layer assembly or spin-coating assembly And the driving current of the resistance variable memory element can be reduced to an order of magnitude by increasing the number of the metal nanoparticle layers one by one.

A basic object of the present invention is to provide a nonvolatile resistance-change memory element comprising a nonconductive layer formed between conductor layers, comprising: a first electrode; A non-conductive layer made of a first metal oxide formed adjacent to the first electrode; A metal nanoparticle layer formed adjacent to the first metal oxide nonconductor layer; A non-conductive layer made of a second metal oxide formed adjacent to the metal nanoparticle layer; And a second electrode formed adjacent to the second metal oxide layer.

Still another object of the present invention is to provide a method of manufacturing a semiconductor device, comprising: (i) forming a first electrode on a substrate; (ii) forming a nonconductive layer of a first metal oxide adjacent to the first electrode; (iii) forming a metal nanoparticle layer adjacent to the first metal oxide nonconductor layer; (iv) forming a non-conductive layer of a second metal oxide adjacent to the metal nanoparticle layer; (v) forming a second electrode adjacent to the second metal oxide nonconductor layer.

The basic object of the present invention is to provide a nonvolatile resistance-variable memory device comprising a nonconductive layer formed between conductor layers, comprising: a first electrode; A non-conductive layer made of a first metal oxide formed adjacent to the first electrode; A metal nanoparticle layer formed adjacent to the first metal oxide nonconductor layer; A non-conductive layer made of a second metal oxide formed adjacent to the metal nanoparticle layer; And a second electrode formed adjacent to the second metal oxide layer. ≪ Desc / Clms Page number 5 >

The first electrode included in the nonvolatile resistance variable memory device of the present invention may be selected from Al, Cu, Ag, Au, Pt, TiN, indium tin oxide (ITO), TaN, W, Mg, .

The first metal oxide included in the nonvolatile resistance variable memory element of the present invention may be selected from the group consisting of titanium dioxide, tantalum oxide, vanadium oxide, molybdenum oxide, aluminum oxide, cobalt oxide, zinc oxide, magnesium oxide, zirconium oxide or hafnium oxide Can be selected. Also, the thickness of the first metal oxide non-conductive layer may be 5 nm to 200 nm.

The metal nanoparticles constituting the metal nanoparticle layer are nanoparticles of a metal selected from Au, Pt or Ag. The size of the metal nanoparticles may be 2 nm to 40 nm.

Furthermore, the metal nanoparticle layer may be formed by Langmuir-blowing, layer-by-layer, or spin-coating of the metal nanoparticles. The number of the metal oxide nanoparticle layers is, for example, determined according to the number of the Langmuir-Blodgett assembly processes, and the number of nanoparticle layers can be selected according to the range of allowable operating current in the system. For example, the number of the nanoparticle layers is preferably one to ten layers, and more preferably three layers.

As used herein, the term " Langmuir-blowjar assembly "refers to a solid substrate that is immersed in a liquid and then withdrawn to transfer one or more nanoparticle monolayers from the liquid subphase onto the solid substrate to form a two- Is formed.

As used herein, "self-assembly" refers to the process by which disordered systems of certain components form structured structures or patterns as a result of specific local interactions between the components.

The second metal oxide of the memory element of the present invention may be selected from titanium dioxide, tantalum oxide, vanadium oxide, molybdenum oxide, aluminum oxide, cobalt oxide, zinc oxide, magnesium oxide, zirconium oxide or hafnium oxide. The thickness of the second metal oxide nonconductor layer may be 5 nm to 200 nm.

The second electrode of the memory element of the present invention may be selected from Al, Cu, Ag, Au, Pt, TiN, ITO, TaN, W, Mg, Zn or Fe.

Yet another object of the present invention is to provide a method of manufacturing a semiconductor device, comprising: (i) forming a first electrode on a substrate; (ii) forming a nonconductive layer of a first metal oxide adjacent to the first electrode; (iii) forming a metal nanoparticle layer adjacent to the first metal oxide nonconductor layer; (iv) forming a non-conductive layer of a second metal oxide adjacent to the metal nanoparticle layer; (v) forming a second electrode adjacent to the second metal oxide nonconductor layer. < Desc / Clms Page number 14 >

The step (i) of the method of the present invention may be performed by thermal evaporation, electron bean evaporation, or magnetron sputtering. The first electrode may be selected from Al, Cu, Ag, Au, Pt, TiN, ITO, TaN, W, Mg, Zn or Fe.

The step (ii) of the method of the present invention can be performed by magnetron sputtering or atomic layer deposition. The first metal oxide may be selected from titanium dioxide, tantalum oxide, vanadium oxide, molybdenum oxide, aluminum oxide, cobalt oxide, zinc oxide, magnesium oxide, zirconium oxide or hafnium oxide. Further, the thickness of the first metal oxide nonconductor layer may be 5 nm to 200 nm.

The step (iii) of the method of the present invention may be carried out by Langmuir-blowjoint assembly, layer-by-layer assembly or spin-coating assembly of metal nanoparticles. The metal nanoparticles may be selected from Au, Pt or Ag. Furthermore, the number of the metal oxide nanoparticle layers is determined by, for example, the number of times of the Langmuir-Blodgett assembly process, and the number of nanoparticle layers can be selected according to the range of allowable operating current in the system. For example, the number of the nanoparticle layers is preferably one to ten layers, and more preferably three layers.

The step (iv) of the method of the present invention may be performed by magnetron sputtering or atomic layer deposition. The second metal oxide may be selected from titanium dioxide, tantalum oxide, vanadium oxide, molybdenum oxide, aluminum oxide, cobalt oxide, zinc oxide, magnesium oxide, zirconium oxide or hafnium oxide. Further, the thickness of the second metal oxide non-conductive layer may be 5 nm to 200 nm.

The step (v) of the method of the present invention may be performed by thermal evaporation, electron beam evaporation, or magnetron sputtering. The second electrode may be selected from Cu, Ag, Au, Pt, TiN, ITO, TaN, W, Mg, Zn or Fe.

The resistance variable memory element of the present invention has low power consumption as compared with the conventional resistance variable memory element. Particularly, as the number of the metal nanoparticle layers is increased by one, the set current and the reset current are reduced by an order of magnitude, so that the number of the metal nanoparticle layers is increased, You can save even more.

1A is a diagram illustrating Langmuir-BlowJet (LB) assembly and stearic acid (SAM) functionalization; FIG. 1B is a photograph of the LB assembly process (top) and plane TEM photographs (bottom) for 1-layer gold nanoparticles and 3-layer gold nanoparticles; Figure 1C is a cross-sectional TEM image of fabricated memory cells; FIG. 1D is an EDS profile showing the thickness of a three-layer gold nanoparticle in MINIM (metal-insulator-nanoparticle-nonconductor-metal).
Figure 2a shows the IV characteristics of bimolar resistive switching of MIM (metal-insulator-metal), MISIM (metal-insulator-self-assembled monolayer (SAM) -conductor-metal) and MINIM structures; Figure 2b is a diagram illustrating low current resistive switching due to gold NP-induced traps; 2C is an IV curve at MIM and MINIM; Figure 2d shows IV characteristics at a compliance current of about 100 A or less at MIM and MINIM; Figure 2e shows the results of the reliability test (durability (left) and retention (right)) of MINIM (resistance value measurement at -0.5 V); FIG. 2F is a cumulative probability at MIM and MINIM; Figure 2g shows MLC (left-hand side) and MINIM (right) MLC (multi-layer cell) operation.

Hereinafter, the present invention will be described in more detail with reference to the following examples or drawings. It is to be understood, however, that the following description of the embodiments or drawings is intended to illustrate specific embodiments of the invention and is not intended to be exhaustive or to limit the scope of the invention to the precise forms disclosed.

Example  1. Synthesis of gold nanoparticles

0.4 g of HAuCl 4 · 3H 2 O (99.9 %, Strem, USA), oleyl amine (90%, Acros, USA) and 30 mL of 1-octadecene (90%, Sigma Aldrich, USA ) at room temperature for 50 mL glass vial. The vial was placed in an oil bath and heated to 90 ° C. The solution was heated for 2 hours, after which the nanoparticles were precipitated, washed twice with ethanol and then centrifuged. The precipitated nanoparticles were redispersed in 5 mL of chloroform.

Example  2. Fabrication of Nonvolatile Resistive Memory Device

(PMMA) (A11, Microchem, USA; about 1 μm, spin coated at 3000 rpm for 30 seconds) and polyamic acid (PI) (polyamic acid, Sigma Aldrich, coated for 60 seconds at rpm) was spin-coated onto a silicon handle wafer (test grade, 4science, Korea). After the PMMA and PI were cured at 200 ° C for 2 hours, aluminum used as a first electrode was deposited by thermal evaporation (350 nm thick), patterned by photolithography, and wet etched. Then, a first TiO 2 nanomembrane (66 nm thick) was RF magnetron sputtered (base pressure: 5 × 10 -6 Torr, room temperature, deposition pressure: 5 mTorr, 20 sccm, RF Power 150 W) (first metal oxide nonconductor layer).

The gold nanoparticles synthesized in Example 1 were assembled on the first TiO 2 nanomembrane through a LB assembly process as follows (FIG. 1A). First, gold nanoparticles capped with oleylamine were dispersed in chloroform (50 mg / mL). The dispersion was added dropwise onto the water sub-phase of an LB trough (IUD 1000, KSV instrument, Finland). After evaporating the solvent, the surface layer was compressed using a mobile barrier (5 mm / min). After the surface pressure reached 30 mN / m, the substrate was lifted and immersed at a rate of 1 mm / min to assemble the gold nanoparticle layer on the substrate.

1B shows photographs (upper part) for the LB assembly process and plane TEM photographs (lower) for one layer of gold nanoparticles and three layers of gold nanoparticles. The number of assembly layers can be controlled by the number of dipping / pulling cycles. Instead of the gold nanoparticle layer, the first TiO 2 nanomembrane was coated with a self-assembled monolayer (stearic acid) to confirm the ligand effect on memory performance (FIG. 1A). (ii) a metal-non-conductor-nanoparticle (NP) comprising a layer of gold nanoparticles (about 12 nm), a nonconductor- (MINIM), iii) a MINIM containing three closely packed gold nanoparticles (about 26 nm) is shown in FIG. The thickness of the three-layered gold nanoparticle layer was confirmed through an energy dispersive X-ray spectroscopy profile of the cross section (Fig. 1d). In the LB assembly, a closely-packed monolayer assembly plays an important role in device uniformity as well as precise thickness control of a plurality of single layers.

Then, using the same method as the deposition of the TiO 2 nano-membrane of claim 1, it was deposited to a second TiO 2 nano-membrane (second non-conductive metal oxide layer) on the gold nanoparticle layer (66 nm thick). An aluminum second electrode was deposited adjacent to the second TiO 2 nanomembrane by thermal evaporation.

Example  3. Characterization of Nonvolatile Resistive Memory Devices

To evaluate the electrical performance, a bipolar I-V curve for the MIM, MISIM and MINIM structures was determined (Figure 2a). The inset of FIG. 2A shows the bias order. The initial state is a high-resistance state (HRS), and a low-resistance state (LRS) transition occurs when a negative voltage ("set") is applied. Thereafter, the structures are switched to the HRS by a positive voltage ("reset"). The I-V characteristics of MIM and MISIM were nearly identical; The formation of one gold nanoparticle layer in the TiO2 layer reduced the set and reset currents by an order of magnitude compared to the MIM structure. The current level was further reduced by an order of three in the MIMIN containing three layers of gold nanoparticles. These results indicate that the assembly of uniform gold nanoparticles in the active layer plays an important role in reducing power consumption and that the stearic acid ligand has little effect on current reduction. This low power consumption characteristic plays an important role in the long-term use of the memory device.

Figure 2B is a diagram illustrating low current switching due to gold nanoparticle-induced traps. 2C is a log-log I-V curve highlighting the negative voltage region. The conduction mechanism at MINIM is similar to the conduction mechanism of MIM and follows the trap-controlled space-charge-limited-current (SCLC) theory. Figure 2d shows I-V curves at different compliance currents for MIM (left) and MINIM (right). At less than 100 μA of compliance current, MINIM showed better on / off ratio than MIM and MISIM. The reliability (endurance and retention) of MINIM, MIM and MISIM are shown in Figure 2E, respectively. The durability was not substantially degraded in continuous sweeping over 100 cycles (left in FIG. 2e), and good retention rate from room temperature to 1,000 seconds was confirmed (right in FIG. 2e). Multi-level cell (MLC) operation means that multiple data storage is possible in a single cell with a discrete compliance current that has a discrete resistance value (FIG. 2D). Such different resistance values can store multiple information in a single cell (Figure 2g). MLC with a current value of -100 μA or less was performed in the MINIM, and the data was preserved even in a read operation over 100 times.

Claims (27)

  1. A nonvolatile resistance variable memory device comprising a nonconductive layer formed between conductor layers,
    A first electrode;
    A non-conductive layer made of a first metal oxide formed adjacent to the first electrode;
    A metal nanoparticle layer formed adjacent to the first metal oxide nonconductor layer;
    A non-conductive layer made of a second metal oxide formed adjacent to the metal nanoparticle layer; And
    And a second electrode formed adjacent to the second metal oxide layer,
    Wherein the number of the metal nanoparticle layers is 1 to 10 layers.
  2. The nonvolatile resistance variable memory device according to claim 1, wherein the first electrode is selected from the group consisting of Al, Cu, Ag, Au, Pt, TiN, ITO, TaN, W, Mg, .
  3. The method of claim 1, wherein the first metal oxide is selected from the group consisting of titanium dioxide, tantalum oxide, vanadium oxide, molybdenum oxide, aluminum oxide, cobalt oxide, zinc oxide, magnesium oxide, zirconium oxide, Volatile resistance change memory element.
  4. The nonvolatile resistance variable memory device according to claim 1, wherein the first metal oxide nonconductor layer has a thickness of 5 nm to 200 nm.
  5. The nonvolatile resistance variable memory device according to claim 1, wherein the metal nanoparticles are nanoparticles of a metal selected from the group consisting of Au, Pt, and Ag.
  6. The nonvolatile resistance variable memory device according to claim 1, wherein the metal nanoparticles have a size of 2 nm to 40 nm.
  7. The non-volatile resistor according to claim 1, wherein the metal nanoparticle layer is formed by a process selected from the group consisting of Langmuir-Blodgett assembly, layer-by-layer assembly and spin- Change memory element.
  8. delete
  9. delete
  10. The method of claim 1 wherein said second metal oxide is selected from the group consisting of titanium dioxide, tantalum oxide, vanadium oxide, molybdenum oxide, aluminum oxide, cobalt oxide, zinc oxide, magnesium oxide, zirconium oxide and hafnium oxide Volatile resistance change memory element.
  11. The nonvolatile resistance variable memory device according to claim 1, wherein the thickness of the second metal oxide nonconductor layer is 5 nm to 200 nm.
  12. The nonvolatile resistance variable memory device according to claim 1, wherein the second electrode is selected from the group consisting of Al, Cu, Ag, Au, Pt, TiN, ITO, TaN, W, Mg, .
  13. (i) forming a first electrode on a substrate;
    (ii) forming a nonconductive layer of a first metal oxide adjacent to the first electrode;
    (iii) forming a metal nanoparticle layer adjacent to the first metal oxide nonconductor layer;
    (iv) forming a non-conductive layer of a second metal oxide adjacent to the metal nanoparticle layer; And
    (v) forming a second electrode adjacent to the second metal oxide nonconductor layer,
    Wherein the number of the metal nanoparticle layers is one to ten layers.
  14. 14. The method of claim 13, wherein step (i) is performed by a process selected from the group consisting of thermal deposition, electron beam deposition, and magnetron sputtering.
  15. The nonvolatile resistance variable memory device according to claim 13, wherein the first electrode is selected from the group consisting of Al, Cu, Ag, Au, Pt, TiN, ITO, TaN, W, Mg, Gt;
  16. 14. The method of claim 13, wherein step (ii) is performed by magnetron sputtering or atomic layer deposition.
  17. 14. The method of claim 13, wherein the first metal oxide is selected from the group consisting of titanium dioxide, tantalum oxide, vanadium oxide, molybdenum oxide, aluminum oxide, cobalt oxide, zinc oxide, magnesium oxide, zirconium oxide, Wherein the nonvolatile resistance change memory element is formed of a nonvolatile memory.
  18. 14. The method of claim 13, wherein the thickness of the first metal oxide nonconductor layer is 5 nm to 200 nm.
  19. 14. The method of claim 13, wherein step (iii) is performed by a process selected from the group consisting of Langmuir-Blowjar assembly, layer-by-layer assembly and spin- Gt;
  20. 14. The method of claim 13, wherein the metal nanoparticles are nanoparticles of a metal selected from the group consisting of Au, Pt, and Ag.
  21. delete
  22. delete
  23. 14. The method of claim 13, wherein step (iv) is performed by magnetron sputtering or atomic layer deposition.
  24. 14. The method of claim 13 wherein said second metal oxide is selected from the group consisting of titanium dioxide, tantalum oxide, vanadium oxide, molybdenum oxide, aluminum oxide, cobalt oxide, zinc oxide, magnesium oxide, zirconium oxide, Wherein the nonvolatile resistance change memory element is formed of a nonvolatile memory.
  25. 14. The method of claim 13, wherein the thickness of the second metal oxide nonconductor layer is 5 nm to 200 nm.
  26. 14. The method of claim 13, wherein step (v) is performed by a process selected from the group consisting of thermal evaporation, electron beam evaporation, and magnetron sputtering.
  27. The nonvolatile resistance variable memory device according to claim 13, wherein the second electrode is selected from the group consisting of Al, Cu, Ag, Au, Pt, TiN, ITO, TaN, W, Mg, Gt;
KR1020140023701A 2014-02-27 2014-02-27 Non-volatile Resistive Memory Device and Process for Manufacturing the Same KR101802293B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020140023701A KR101802293B1 (en) 2014-02-27 2014-02-27 Non-volatile Resistive Memory Device and Process for Manufacturing the Same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020140023701A KR101802293B1 (en) 2014-02-27 2014-02-27 Non-volatile Resistive Memory Device and Process for Manufacturing the Same
PCT/KR2015/001904 WO2015130114A1 (en) 2014-02-27 2015-02-27 Non-volatile resistive random access memory element and method for producing same

Publications (2)

Publication Number Publication Date
KR20150101866A KR20150101866A (en) 2015-09-04
KR101802293B1 true KR101802293B1 (en) 2017-11-28

Family

ID=54009363

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020140023701A KR101802293B1 (en) 2014-02-27 2014-02-27 Non-volatile Resistive Memory Device and Process for Manufacturing the Same

Country Status (2)

Country Link
KR (1) KR101802293B1 (en)
WO (1) WO2015130114A1 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090065764A1 (en) * 2004-06-08 2009-03-12 Nanosys, Inc. Methods and devices for forming nanostructure monolayers and devices including such monolayers
US20110240949A1 (en) 2010-03-31 2011-10-06 Yuichiro Mitani Information recording device and method of manufacturing the same
JP2013135065A (en) 2011-12-26 2013-07-08 Toshiba Corp Resistance change type memory element
US20130187116A1 (en) 2012-01-19 2013-07-25 Globalfoundries Singapore Pte Ltd RRAM Device With Free-Forming Conductive Filament(s), and Methods of Making Same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040026682A1 (en) * 2002-06-17 2004-02-12 Hai Jiang Nano-dot memory and fabricating same
KR20060070716A (en) * 2004-12-21 2006-06-26 한국전자통신연구원 Organic memory device and method for fabricating the same
KR101096203B1 (en) * 2010-04-08 2011-12-22 주식회사 하이닉스반도체 Semiconductor device and method for manufacturing the same
KR101882850B1 (en) * 2011-12-29 2018-07-30 에스케이하이닉스 주식회사 Resistance variable memory device and method for fabricating the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090065764A1 (en) * 2004-06-08 2009-03-12 Nanosys, Inc. Methods and devices for forming nanostructure monolayers and devices including such monolayers
US20110240949A1 (en) 2010-03-31 2011-10-06 Yuichiro Mitani Information recording device and method of manufacturing the same
JP2013135065A (en) 2011-12-26 2013-07-08 Toshiba Corp Resistance change type memory element
US20130187116A1 (en) 2012-01-19 2013-07-25 Globalfoundries Singapore Pte Ltd RRAM Device With Free-Forming Conductive Filament(s), and Methods of Making Same

Also Published As

Publication number Publication date
WO2015130114A1 (en) 2015-09-03
KR20150101866A (en) 2015-09-04

Similar Documents

Publication Publication Date Title
US9240549B2 (en) Memory component, memory device, and method of operating memory device
Choi et al. Electrical performance and scalability of Pt dispersed SiO2 nanometallic resistance switch
Seok et al. A review of three‐dimensional resistive switching cross‐bar array memories from the integration and materials property points of view
Valov et al. Cation-based resistance change memory
Celano et al. Three-dimensional observation of the conductive filament in nanoscaled resistive memory devices
Yoon et al. Highly uniform, electroforming‐free, and self‐rectifying resistive memory in the Pt/Ta2O5/HfO2‐x/TiN structure
US8450709B2 (en) Nonvolatile resistance change device
TWI434408B (en) Resistive memory and methods of processing resistive memory
Edwards et al. Reconfigurable memristive device technologies
US8958234B2 (en) Selector type electronic device functioning by ionic conduction
US8686390B2 (en) Nonvolatile memory element having a variable resistance layer whose resistance value changes according to an applied electric signal
KR101239962B1 (en) Variable resistive memory device comprising buffer layer on lower electrode
US7307270B2 (en) Memory element and memory device
JP5088036B2 (en) Storage element and storage device
CN101097988B (en) Variable resistance random access memory device containing n+ interface layer
US20140070160A1 (en) Nonvolatile memory device
DE602005001924T2 (en) A method of manufacturing a non-volatile memory device of electrical resistance material
US8816317B2 (en) Non-volatile resistive switching memories formed using anodization
Liu et al. Controllable growth of nanoscale conductive filaments in solid-electrolyte-based ReRAM by using a metal nanocrystal covered bottom electrode
CN1144231C (en) Programmable metallization cell and method of making
US8988927B2 (en) Non-volatile variable capacitive device including resistive memory cell
Huang et al. ZnO1–x nanorod arrays/ZnO thin film bilayer structure: from homojunction diode and high-performance memristor to complementary 1D1R application
CN102132408B (en) Storage element and storage device
US6838720B2 (en) Memory device with active passive layers
KR101078541B1 (en) Memory element and memory device

Legal Events

Date Code Title Description
E902 Notification of reason for refusal
GRNT Written decision to grant