CN108550696B

CN108550696B - Phase change memory

Info

Publication number: CN108550696B
Application number: CN201810339585.8A
Authority: CN
Inventors: 吴孝哲
Original assignee: Being Advanced Memory Taiwan Ltd; Jiangsu Advanced Memory Technology Co Ltd; Jiangsu Advanced Memory Semiconductor Co Ltd
Current assignee: Beijing Times Full Core Storage Technology Co ltd; Being Advanced Memory Taiwan Ltd; Jiangsu Advanced Memory Semiconductor Co Ltd
Priority date: 2016-03-08
Filing date: 2016-03-08
Publication date: 2022-02-25
Anticipated expiration: 2036-03-08
Also published as: CN108550696A; CN105789437A; CN105789437B

Abstract

The present invention discloses a phase change memory. The phase change memory comprises a phase change layer, a conductive layer, a heating element, a first insulating pad and a contact structure. The phase change layer is provided with a main surface, and the conducting layer is positioned on one side of the main surface of the phase change layer and is electrically connected with the phase change layer. The heating element contacts a major surface of the phase change layer. The first insulating pad contacts the main surface of the phase change layer and comprises a first side surface and a second side surface which are opposite and respectively contact the heating element and the conductive layer. The contact structure is electrically connected with the heating element. The phase change memory has low production cost, stable quality and high memory cell density.

Description

Phase change memory

The present application is a divisional application of patent applications entitled "phase change memory and method for manufacturing phase change memory" filed 2016, 03, 08, and 201610130129.3.

Technical Field

The invention relates to a phase change memory and a method for manufacturing the same.

Background

Computers or other electronic devices are often configured with various types of memory, such as Random Access Memory (RAM), Read Only Memory (ROM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Phase Change Random Access Memory (PCRAM), or flash memory. Phase change memories are non-volatile memories in which data stored therein can be obtained by measuring the resistance of the memory cells. Generally, a phase change memory cell includes a heating element and a phase change cell, which undergoes a phase change when heated. When a current is applied to the heating element, the heating element converts the electrical energy into heat, which causes the phase change cell to change phase, for example, from an amorphous phase (amorphus) to a polycrystalline phase (polycrystalline). The phase change unit has different resistance values in different phases, and the data type of the memory unit can be judged by detecting or reading the resistance value of the phase change unit. It is a constant aim of phase change memory manufacturers to further reduce the manufacturing cost of the memory and to improve the quality of the memory.

Disclosure of Invention

One aspect of the present invention provides a phase change memory. The phase change memory comprises a phase change layer, a conductive layer, a heating element, a first insulating pad and a contact structure. The phase change layer has a main surface extending in a plane and a side surface adjoining the main surface. The conductive layer is located on one side of the main surface of the phase change layer and far away from the side surface, and the conductive layer is electrically connected with the phase change layer. The heating element contacts a major surface of the phase change layer. The first insulating pad contacts the main surface of the phase change layer and comprises a first side surface and a second side surface which are opposite, and the first side surface and the second side surface respectively contact the heating element and the conductive layer. The contact structure is spaced from the side surface of the phase change layer by a distance, the contact structure is parallel to the side surface of the phase change layer, and the contact structure is electrically connected with the heating element.

In some embodiments, the heating element includes a first sidewall and a second sidewall opposite to each other, and the first sidewall contacts the first side of the first insulating pad.

In some embodiments, the phase change memory further comprises a first dielectric layer overlying the phase change layer and substantially parallel to the major surface. The conductive layer, the heating element, and the first insulating pad are sandwiched between the first dielectric layer and the phase change layer.

In some embodiments, the phase change memory further comprises a second dielectric layer disposed below the phase change layer and substantially parallel to the major surface. The phase change layer is sandwiched between the conductive layer, the heating element, and the first and second dielectric layers.

In some embodiments, the phase change memory further includes a second insulating pad and a semiconductor structure. The second insulating pad contacts the second sidewall of the heating element. The semiconductor structure penetrates through the second insulating pad and is provided with a second side wall with one end embedded into the heating element. The contact structure is electrically connected to the heating element through the semiconductor structure.

In some embodiments, the contact structure extends in a direction substantially perpendicular to the major surface, and the contact structure contacts the semiconductor structure.

In some embodiments, the phase change memory further comprises a first dielectric layer disposed over the phase change layer and substantially parallel to the major surface, wherein the conductive layer, the heating element, the first insulating pad and the second insulating pad are sandwiched between the first dielectric layer and the phase change layer.

In some embodiments, the phase change memory further comprises a second dielectric layer disposed substantially parallel to the major surface and below the phase change layer, wherein the phase change layer is sandwiched between the conductive layer, the heating element, the first and second insulating pads, and the second dielectric layer.

In some embodiments, the contact structure includes a conductive barrier layer and a conductive pillar. One side of the conductive barrier layer is in contact with the first dielectric layer, the semiconductor structure, and the first insulating layer. The conductive post contacts the other side of the conductive barrier layer.

In some embodiments, the semiconductor structure is a diode structure.

Drawings

FIG. 1A is a flow chart illustrating a method of fabricating a phase change memory according to various embodiments of the present invention;

FIG. 1B depicts a flow chart of steps according to certain preferred embodiments of the present invention;

FIGS. 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A and 12A respectively illustrate schematic top views of some embodiments of the present invention at different stages of processing;

FIGS. 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B and 12B respectively illustrate cross-sectional views along line B-B' at different stages of the process according to some embodiments of the present invention;

FIGS. 2C, 3C, 4C, 5C, 6C, 7C, 8C, 9C, 10C and 12C respectively illustrate cross-sectional views along line C-C' at different stages of the process according to some embodiments of the present invention;

FIGS. 2D, 3D, 4D, 5D, 6D, 7D, 8D, 9D, 10D and 12D respectively illustrate schematic cross-sectional views along line D-D' at different stages of the process according to some embodiments of the present invention;

FIGS. 6B-1, 6D-1, 7B-1, 7D-1, 8B-1, 8D-1, 9B-1, 9D-1, and 10B-1 are enlarged views of respective portions;

FIG. 11 is an enlarged view of each of the phase change memory cells of FIG. 10D.

Detailed Description

In order to make the description of the invention more complete and thorough, the following illustrative description is given for implementation aspects and embodiments of the invention; it is not intended to be the only form in which the embodiments of the invention may be practiced or utilized. The various embodiments disclosed below may be combined with or substituted for one another where appropriate, and additional embodiments may be added to one embodiment without further recitation or description.

In the following description, numerous specific details are set forth to provide a thorough understanding of the following embodiments. However, embodiments of the invention may be practiced without these specific details. In other instances, well-known structures and devices are shown schematically in order to simplify the drawing.

Spatially relative terms, such as "below," "beneath," "above," "over," and the like, may be used herein for ease of describing the relative relationship of one element or feature to another element or feature as illustrated in the figures. The true meaning of these spatially relative terms encompasses other orientations. For example, when turned over 180 degrees, the relationship of one element to another may change from "below" to "above" or "above" the relationship. Spatially relative descriptors used herein should be interpreted as such.

One aspect of the present invention provides a method of fabricating a phase change memory. FIG. 1A is a flow chart of a method 1 of fabricating a phase change memory according to various embodiments of the invention. Method 1 includes operation 10, operation 20, operation 30, operation 40, operation 50, operation 60, and operation 70. Fig. 2A-12C are schematic diagrams illustrating various embodiments of the present invention at various stages of processing. Although the methods disclosed herein are illustrated below as a series of acts or steps, the order in which the acts or steps are presented should not be construed as a limitation of the present invention. For example, certain operations or steps may be performed in a different order and/or concurrently with other steps. Moreover, not all illustrated steps may be required to implement a particular embodiment of the invention. Further, each operation or step herein may comprise several sub-steps or actions.

In operation 10, a plurality of stacked structures are formed. FIG. 2A is a schematic top view of some embodiments of the present invention after operation 10 is performed, and FIGS. 2B, 2C, and 2D are schematic cross-sectional views taken along line B-B ', line C-C ', and line D-D ' of FIG. 2A, respectively. As shown in fig. 2B and 2D, each stacked structure 110 includes a plurality of dielectric layers 112, a plurality of phase change material layers 114, and a plurality of conductive layers 116. Each conductive layer 116 and each phase change material layer 114 are sandwiched between two adjacent dielectric layers 112. In some embodiments, dielectric layer 112, phase change material layer 114, and conductive layer 116 are repeatedly deposited sequentially on semiconductor substrate 102. Then, a protection layer 108 is formed on the uppermost dielectric layer 112, and the material of the protection layer 108 may be, for example, silicon nitride (SiN), but not limited thereto. The protective layer 108 may also be formed of other insulating protective materials, such as silicon oxide (SiO)₂) Alumina (Al)₂O₃) Aluminum nitride (AlN), glass or similar materials, or combinations of the above. Thereafter, a plurality of stacked structures 110 are formed by photolithography and etching processes. For example, the top view pattern of the stacked structure 110 may be defined by forming the patterned photoresist layer 104, then performing a dry anisotropic etch to form the stacked structure 110, and then removing the patterned photoresist layer 104. The deposition sequence of the phase change material layer 114 and the conductive layer 116 can be varied, for example, in some other embodiments, the dielectric layer 112, the conductive layer 116, and the phase change material are repeatedly deposited sequentiallyA layer 114.

The dielectric layer 112 may comprise any suitable dielectric material, such as silicon nitride, silicon oxide, doped silicate glass, etc., and the dielectric layer 112 may also be formed of a dielectric material with a low dielectric constant, such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), silicon carbide material, or combinations thereof, or the like. The thickness of the dielectric layer 112 may be adjusted according to practical requirements, for example, from about 5nm to about 300 nm.

In some embodiments, phase change material layer 114 comprises a germanium-antimony-tellurium (GST) material, such as Ge₂Sb₂Te₅、Ge₁Sb₂Te₄、Ge₁Sb₄Te₇Or combinations of the above or similar materials. Other phase change materials may be GeTe, Sb₂Te₃GaSb, InSb, Al-Te, Te-Sn-Se, Ge-Sb-Te, In-Sb-Te, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, Te-Ge-Sb-S, Te-Ge-Sn-O, Sb-Te-Bi-Se, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ag-In-Sb-Te, Ge-Te-Sn-Pt, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd, and Ge-Sb-Se-Te. The thickness of the phase change material layer 114 can be adjusted according to practical requirements, for example, from about 5nm to about 100 nm.

In some embodiments, the top view pattern of the stacked structure 110 is a straight bar, and the conductive layer 116 in the stacked structure 110 serves as a word line (word line) of the phase change memory. The material of the conductive layer 116 may be, for example, a metal material containing tungsten (W), and the conductive layer 116 may also contain other metal materials, such as titanium (Ti), aluminum (Al), copper (Cu), silver (Ag), gold (Au), or a combination of the above materials, or the like. The thickness of the conductive layer 116 can be adjusted according to practical requirements, for example, from about 5nm to about 100 nm.

In the subsequent fig. 3A to 10C, the drawings with the letter "a" included in the figure number, for example, fig. 3A, 4A, 5A and the like, are schematic top views; the figure number includes the primary and secondary drawings "B", for example, the figures such as FIGS. 3B, 4B, 5B, etc., which are schematic cross-sectional views along line B-B'; the figure with the primary and secondary "C" included in the figure number, such as fig. 3C, 4C, 5C, etc., is a schematic cross-sectional view along line C-C'; the figures including the son-mother unit "D" in the figure number, for example, fig. 3D, 4D, 5D, etc., are schematic cross-sectional views along line D-D'.

In operation 20 of fig. 1A, an insulating layer is formed between two adjacent stacked structures, the insulating layer having at least one contact hole exposing sidewalls of the stacked structures. FIGS. 3A-3D and 4A-4D illustrate a schematic diagram of an implementation operation 20 of some embodiments of the present invention. First, as shown in fig. 3A to 3D, an insulating layer 120 is formed between two adjacent stacked structures 110. For example, a deposition process is used to deposit a layer of insulating material to cover the stacked structures 110 and fill the gap between two adjacent stacked structures 110. Then, a chemical mechanical polishing process is performed to remove the insulating material layer deposited on the stacked structures 110, so as to form an insulating layer 120 between two adjacent stacked structures. Subsequently, as shown in fig. 4A-4D, a patterned photoresist layer 106 is formed over the insulating layer 120, and an etching process is performed, thereby forming at least one contact hole 122 in the insulating layer 120. As shown in fig. 4D, contact holes 122 expose sidewall portions 112a of dielectric layers 112, sidewall portions 114a of phase change material layers 114 and sidewall portions 116a of conductive layers 116.

In operation 30 of fig. 1A, the exposed sidewall portions of each conductive layer are removed to form a first void between adjacent dielectric layers and phase change material layers. Referring to fig. 5A-5D, exposed sidewall portions 116a of each conductive layer 116 are removed through contact holes 122, thereby forming first voids 131 (shown in fig. 5A, 5B and 5D) between adjacent dielectric layers 112 and phase change material layers 114. In accordance with various embodiments of the present invention, operation 30 is performed using a wet etch process. The etchant of the wet etching process etches the sidewall portion 116a of each conductive layer 116 through the contact hole 122 to form the first void 131, so that the first void 131 and the contact hole 122 communicate with each other. In addition, since the wet etching is isotropic etching, the conductive layer 116 of the stacked structure 110 is etched by the etchant from the X direction and the Y direction shown in fig. 5A, and thus the width W1 of the first gap 131 is greater than the width Z of the contact hole 122. In one embodiment, when the conductive layer 116 comprises a tungsten material, the wet etching process may optionally comprise hydrogen peroxide (H)₂O₂) Is/are as followsAnd (3) an etching agent. In some embodiments, the height of the first gap 131 is substantially determined by the thickness of the conductive layer 116.

In operation 40 of fig. 1A, insulating material 140 is formed in each first void 131, as in fig. 5A-5D. In some embodiments, a layer of insulating material is blanket deposited, such as by a chemical vapor deposition or atomic layer deposition process, filling the first gap 131 and covering the other structures; an anisotropic etching process is then performed to remove the insulating material layer outside the first voids 131, thereby obtaining the insulating material 140 filled in the first voids 131. In various embodiments, the thickness of the insulating material 140 is substantially the same as the thickness of the conductive layer 116, and the sidewall portions 142 of the insulating material 140 are exposed through the contact holes 122 (shown in fig. 5D). Further, the width of insulating material 140 is substantially equal to width W1 of first void 131. According to various embodiments of the present invention, the insulating material 140 and the dielectric layer 112 are made of different materials. For example, the insulating material 140 may be alumina or the like, and the dielectric layer 112 may be silicon oxide or the like.

In operation 50, the sidewall portions 142 of each of the insulating materials 140 are removed to form a plurality of second voids 132, as shown in fig. 6A to 6D-1, wherein fig. 6B-1 is an enlarged view of a region F1 in fig. 6B, and fig. 6D-1 is an enlarged view of a region F2 in fig. 6D. In accordance with various embodiments of the present invention, the second voids 132 are formed by removing the sidewall portions 142 of each insulating material 140 using a wet etch process with an appropriate etchant. The etchant is selected such that the ratio of the insulating material 140 to the dielectric layer 112 is selected such that the etchant does not substantially remove the sidewalls of the dielectric layer 112, but is effective to remove the sidewall portions 142 of the insulating material 140, thereby forming the second voids 132. For example, when the insulating material 140 is composed of alumina and the dielectric layer 112 is composed of silicon oxide, an etchant containing potassium hydroxide (KOH) may be selected to etch the sidewall portions 142 of the insulating material 140, thereby forming the second voids 132. Since the wet etching is isotropic, the insulating material 140 is etched by the etchant from the X direction and the Y direction shown in fig. 5A, and thus the width W2 of the second void 132 is larger than the width Z of the contact hole 122.

In operation 60, a heating material layer 150 is formed in each second void 132. There are many possible variations to operation 60 and the operations or steps that follow. According to some embodiments of the present invention, a semiconductor structure, such as a diode, may be selectively formed in the second void 132. However, the semiconductor structure in the second void is not an essential element of the present invention; in other embodiments, no semiconductor structure may be formed in the second void.

The steps for forming diode structures in the second voids 132 according to some embodiments of the present invention are described in detail below. First, operation 60 further comprises forming a first type semiconductor material 160 in each of the second voids 132, as shown in fig. 6A-6D. The first-type semiconductor material 160 is laterally embedded in each heating material layer 150 from the contact hole 122, as shown in fig. 6D. There are various ways to form the structures shown in fig. 6A-6D. In one embodiment, a deposited layer of heating material is first conformally formed by an atomic layer deposition process, which coats the inner surfaces of the second voids 132 and other structures, but does not fill the second voids 132 and/or the contact holes 122. Then, a first type semiconductor material layer is formed on the heating material deposition layer, and the first type semiconductor material layer fills the remaining space of the second gap 132. Thereafter, an anisotropic etching process is performed to remove the heating material deposition layer and the first type semiconductor material layer outside the second gap 132, so as to obtain the heating material layer 150 and the first type semiconductor material 160 filled in the second gap 132. Thereby, a first type semiconductor material 160 is obtained which is laterally embedded in the heating material layer 150, the first type semiconductor material 160 may for example be a P + -type semiconductor material. In some embodiments, the heating material layer 150 includes a first portion 151 and a second portion 152 respectively disposed above and below the first type semiconductor material 160. In addition, the width of the heating material layer 150 is substantially equal to the width W2 of the second void 132.

After the first type semiconductor material 160 is formed, steps 61, 62, 63, 64, 65 and 66 shown in fig. 1B are performed to form a diode structure in the second void 132.

In step 61, a portion of each heating material layer 150 is removed to form a plurality of third voids 133, as shown in fig. 7A to 7D-1, wherein fig. 7B-1 is an enlarged view of a region F3 in fig. 7B, and fig. 7D-1 is an enlarged view of a region F4 in fig. 7D. According to various embodiments of the present invention, the third voids 133 are formed by removing the exposed portions of the heating material layers 150 in the contact holes 122 by a wet etching process with an appropriate etchant. For example, when the heating material layer 150 comprises a metal nitride such as tantalum nitride (TaN), ammonium hydroxide (NH) may be optionally contained₄OH) and hydrogen peroxide (H)₂O₂) The exposed portions of each heating material layer 150 are removed by the etchant to form third voids 133. Since the wet etching is isotropic, the etchant etches the insulating material 140 from the X direction and the Y direction shown in fig. 5A, and thus the width W3 of the third gap 133 is larger than the width Z of the contact hole 122. In some embodiments, the third voids 133 include

voids

133a and 133b, the

voids

133a and 133b being respectively located above and below the first-type semiconductor material 160.

In step 62, first insulation plugs 171 are formed in each third gap 133, as shown in fig. 7A to 7D-1. In some embodiments, a layer of insulating material is blanket deposited, for example using cvd or ald techniques, filling the third gap 133 and covering the other structures; an anisotropic etching process is then performed to remove the insulating material layer outside the third gap 133, so as to obtain the first insulating plug 171 filled in the third gap 133. The width of the first insulation plugs 171 is substantially equal to the width W3 of the third voids 133. In one embodiment, the first insulating plug 171 is made of silicon nitride (SiN). In some embodiments, the first insulating plug 171 includes an insulating plug 171a and an insulating plug 171b, and the insulating plug 171a and the insulating plug 171b are respectively located above and below the first-type semiconductor material 160. In some embodiments, the material of the first insulation plugs 171 may be the same as or different from the dielectric layer 112. In some other embodiments, the material of the first insulating plug 171 may be the same as or different from the insulating material 140.

In step 63, a portion of each of the first-type semiconductor materials 160 is removed to form a plurality of fourth voids 134, as shown in fig. 8A to 8D-1, wherein fig. 8B-1 is an enlarged view of a region F5 in fig. 8B, and fig. 8D-1 is an enlarged view F6 of a region in fig. 8D. In some embodiments, the fourth voids 134 are formed by removing exposed sidewall portions of each of the first-type semiconductor materials 160 through the contact holes 122 by a wet etching process with an appropriate etchant. Since the wet etching is isotropic, the first-type semiconductor material 160 is etched by the etchant from the X direction and the Y direction shown in fig. 5A, and thus the width W4 of the fourth void 134 is greater than the width Z of the contact hole 122.

In step 64, a second type of semiconductor material 180 is formed in each fourth void 134, as shown in FIGS. 8A-8D-1. The second type of semiconductor material 180 may comprise, for example, an N-type semiconductor material. In some embodiments, a layer of semiconductor material of the second type is blanket deposited, for example, by cvd or ald techniques, filling the fourth gap 134 and covering the other structures; then, an anisotropic etching process is performed to remove the second-type semiconductor material layer outside the fourth gap 134, thereby forming a second-type semiconductor material 180 embedded in the fourth gap 134. The width of the second-type semiconductor material 180 is substantially equal to the width W4 of the fourth void 134. The second type semiconductor material 180 may be, for example, an N-type semiconductor material, the second type semiconductor material 180 being in contact with the first type semiconductor material 160 to form a diode structure 184.

In step 65, the sidewall portions 114a (shown in FIG. 8D) of each phase change material layer 114 exposed in the contact hole 122 are removed to form a plurality of fifth voids 135, as shown in FIGS. 9A to 9D-1, wherein FIG. 9B-1 is an enlarged view of a region F7 in FIG. 9B, and FIG. 9D-1 is an enlarged view of a region F8 in FIG. 9D. According to various embodiments of the present invention, the fifth void 135 is formed by removing the sidewall portion 114a of the phase change material layer 114 exposed in the contact hole 122 through the contact hole 122 by a wet etching process and selecting an appropriate etchant. For example, when the phase change material layer 114 comprises a germanium-antimony-tellurium material, an etchant containing nitric acid (20 wt%) may be selected to remove the sidewall portions 114a of the phase change material layer 114, thereby forming the fifth voids 135. Since the wet etching is isotropic etching, the phase change material layer 114 is etched by the etchant from the X direction and the Y direction shown in fig. 5A, and thus the width W5 of the fifth void 135 is larger than the width Z of the contact hole 122.

In step 66, second insulating plugs 172 are formed in the respective fifth voids 135, as shown in fig. 9A to 9D-1. In some embodiments, a layer of insulating material is blanket deposited, for example, using cvd or ald techniques, filling the fifth gap 135 and covering the other structures; then, an anisotropic etching process is performed to remove the insulating material layer outside the fifth gap 135, so as to obtain the second insulating plug 172 embedded in the fifth gap 135. The width of the second insulation plug 172 is substantially equal to the width W5 of the fifth space 135. The second insulating plug 172 blocks the phase change material layer 114 from the contact hole 122, so as to prevent the phase change material layer 114 from being exposed through the contact hole 122. In some embodiments, the second insulating plugs 172 are made of the same material as the first insulating plugs 171.

As described above, according to other embodiments of the present invention, a semiconductor structure such as a diode structure may not be formed in the second gap 132 (shown in fig. 6D). Therefore, the steps of forming the first-type semiconductor material 160 and the steps 61 to 66 are only preferred embodiments of the present invention. For example, when the semiconductor structure is not formed, the heating material layer 150 in operation 60 may fill the second gap 132. Subsequently, a portion of each phase change material layer 114 is removed to form a plurality of fifth voids 135 in step 65, and then a second insulating plug 172 is formed in each fifth void 135 in step 66.

In operation 70, a contact structure 190 is formed in contact hole 122, as shown in FIGS. 10A-10D, wherein FIG. 10B-1 is an enlarged view of region F9 in FIG. 10B. In some embodiments, the contact structure 190 includes a conductive barrier layer 191 and a conductive pillar 192. In some embodiments, a layer of conductive barrier material is first conformally deposited overlying contact hole 122, and then a layer comprising a conductive material is deposited to fill the remaining space within contact hole 122. In one embodiment, the deposited conductive barrier material layer and the conductive material layer are also deposited on the structure other than the contact hole 122. therefore, after the conductive material layer is deposited, a chemical mechanical polishing process is performed to remove the conductive barrier material layer and the conductive material layer other than the contact hole 122, thereby obtaining the phase change memory structure shown in fig. 10A-10D. Referring to FIG. 10D, the phase change memory structure fabricated herein includes a plurality of phase change memory cells 100. In some embodiments, the material of the conductive barrier layer 191 may be titanium nitride, and the material of the conductive pillar 192 may be a metal material including tungsten, for example. The conductive barrier layer 191 serves to prevent tungsten atoms in the conductive pillars 192 from diffusing into adjacent structures. The contact structure 190 may also be other materials, such as titanium (Ti), aluminum (Al), copper (Cu), silver (Ag), gold (Au), or combinations thereof, or the like. FIG. 11 shows an enlarged view of each of the phase change memory cells 100 of FIG. 10D, and the elements of FIG. 11 are described in more detail below.

Other structures may optionally be formed on the contact structure 190 after performing operation 70. For example, as shown in FIGS. 12A-12D, a bit line (bit line)194 is formed over the contact structure 190. The bit line 194 is electrically connected to the phase change material layer 114 through the contact structure 190, the diode structure 184 and the heating material layer 150.

In the conventional three-dimensional phase change memory, the deposition-lithography-etching process must be repeated to fabricate the three-dimensional phase change memory. In the method disclosed herein, the dielectric layer 112, the phase change material layer 114 and the conductive layer 116 are sequentially deposited repeatedly, and then a photolithography and etching process is performed to form a plurality of stacked structures 110, thereby reducing the number of photolithography-etching processes and the manufacturing cost of the phase change memory. In addition, the phase change material layer 114 is deposited on a flat surface, so that it can be formed by using a physical vapor deposition technique without using a chemical vapor deposition process or an atomic layer deposition process. In the prior art, when a chemical vapor deposition technique or an atomic layer deposition technique is used to form the phase change layer, the problem of poor quality of the deposited film layer is often encountered. Thus, the method disclosed herein ameliorates the disadvantages of the prior art.

In accordance with the above disclosure, another aspect of the present invention is to provide a phase change memory. Referring to fig. 11, the phase change memory 200 includes a phase change layer 210, a conductive layer 220, a heating element 230, a first insulating pad 240, and a contact structure 250. The phase change layer 210 has a major surface 210a, and the major surface 210a extends in a plane. The conductive layer 220 is located on one side of the main surface 210a of the phase change layer 210 and is electrically connected to the phase change layer 210. In some embodiments, conductive layer 220 contacts major surface 210a of phase change layer 210 and is substantially parallel to phase change layer 210. The heating element 230 contacts the major surface 210a of the phase change layer 210. In certain embodiments, the heating element 230 comprises opposing first 231 and second 232 sidewalls. In various embodiments, the heating element 230 further includes a third surface 233, the third surface 233 is adjacent to the first sidewall 231 and the second sidewall 232, and the third surface 233 of the heating element 230 contacts the main surface 210a of the phase change layer 210. In addition, the first insulation pad 240 contacts the main surface 210a of the phase change layer 210, the first insulation pad 240 includes a first side 241 and a second side 242 opposite to each other, and the first side 241 and the second side 242 respectively contact the heating element 230 and the conductive layer 220. The contact structure 250 is electrically connected to the heating element 230. In some embodiments, the contact structure 250 includes a conductive barrier layer 251 and a conductive pillar 252.

In various embodiments, the phase change memory 200 further includes a second insulating pad 260 and a semiconductor structure 270. The second insulating pad 260 contacts the second sidewall 232 of the heating element 230. The semiconductor structure 270 laterally extends through the second insulating pad 260, and the semiconductor structure 270 has an end 272 embedded in the second sidewall 232 of the heating element 230. The contact structure 250 is electrically connected to the heating element 230 through the semiconductor structure 270. In an embodiment, the contact structure 250 extends in a direction substantially perpendicular to the main surface 210a of the phase change layer 210, and the conductive barrier layer 251 of the contact structure 250 directly contacts the semiconductor structure 270. When the phase change memory is in an operating state, current is routed as shown in path E of fig. 11, from the contact structure 250 through the semiconductor structure 270 to the heating element 230, and from the heating element 230 through the phase change layer 210 to the conductive layer 220. The long distance conduction of current is primarily through the conductive pillars 251, and current will only pass through the conductive barrier layer 251 between the conductive pillars 252 and the semiconductor structure 270 when current is conducted between the conductive pillars 252 and the semiconductor structure 270. When a current passes through the heating element 230, the heating element 230 converts part of the electrical energy into heat, and the third surface 233 of the heating element 230 heats the phase change layer 210, so that a local portion of the main surface 210a of the phase change layer 210, which is in contact with the heating element 230, changes phase, thereby storing data. As previously described, semiconductor structure 270 may not be formed according to some embodiments of the present invention, in which current may be conducted from contact structure 250 to heating element 230, and from heating element 230 to conductive layer 220 via phase change layer 210; or the current may be conducted from the conductive layer 220 to the phase change layer 210 and from the phase change layer 210 to the conductive layer 220 via the heating element 230.

In another embodiment, the phase change memory 200 further comprises a first dielectric layer 281 and a second dielectric layer 282. The first dielectric layer 281 is located above the phase change layer 210 and substantially parallel to the main surface 210a of the phase change layer 210. Conductive layer 220, heating element 230, and first insulating pad 240 are sandwiched between first dielectric layer 281 and phase change layer 210. The second dielectric layer 282 is disposed below the phase change layer 210.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A phase change memory, comprising:

a phase change layer having a main surface extending in a plane and a side surface adjacent to the main surface;

a conductive layer located on one side of the main surface of the phase change layer and away from the side surface, wherein the conductive layer is electrically connected with the phase change layer;

a heating element contacting the major surface of the phase change layer;

a first insulating pad contacting the main surface of the phase change layer and including a first side and a second side opposite to each other, the first side and the second side contacting the heating element and the conductive layer, respectively; and

and the contact structure is spaced from the side surface of the phase change layer by a distance, is parallel to the side surface of the phase change layer and is electrically connected with the heating element.

2. A phase change memory as claimed in claim 1, wherein said heating element comprises a first sidewall and a second sidewall opposite to each other, said first sidewall contacting said first side of said first insulating pad.

3. A phase change memory as claimed in claim 1, further comprising:

a first dielectric layer disposed over the phase change layer and substantially parallel to the major surface, wherein the conductive layer, the heating element, and the first insulating pad are sandwiched between the first dielectric layer and the phase change layer.

4. A phase change memory as claimed in claim 3, further comprising:

a second dielectric layer disposed below the phase change layer and substantially parallel to the major surface, wherein the phase change layer is sandwiched between the conductive layer, the heating element, and the first and second dielectric layers.

5. A phase change memory as claimed in claim 2, further comprising:

a second insulating pad contacting the second sidewall of the heating element; and

a semiconductor structure penetrating the second insulating pad and having a second sidewall with one end embedded in the heating element;

wherein the contact structure is electrically connected to the heating element through the semiconductor structure.

6. A phase change memory as claimed in claim 5, wherein said contact structure extends in a direction perpendicular to said main surface and said contact structure contacts said semiconductor structure.

7. A phase change memory as claimed in claim 5, further comprising:

a first dielectric layer over the phase change layer and substantially parallel to the major surface, wherein the conductive layer, the heating element, the first insulating pad and the second insulating pad are sandwiched between the first dielectric layer and the phase change layer.

8. A phase change memory as claimed in claim 7, further comprising:

a second dielectric layer disposed below the phase change layer and substantially parallel to the major surface, wherein the phase change layer is sandwiched between the conductive layer, the heating element, the first and second insulating pads, and the second dielectric layer.

9. A phase change memory as claimed in claim 7, wherein said contact structure comprises:

a conductive barrier layer, one side of the conductive barrier layer contacting the first dielectric layer, the semiconductor structure and the second insulating pad; and

a conductive post contacts the other side of the conductive barrier layer.

10. A phase change memory as claimed in any one of claims 5 to 9, characterized in that the semiconductor structure is a diode structure.