CN108550696A - Phase-change memory - Google Patents

Phase-change memory Download PDF

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Publication number
CN108550696A
CN108550696A CN201810339585.8A CN201810339585A CN108550696A CN 108550696 A CN108550696 A CN 108550696A CN 201810339585 A CN201810339585 A CN 201810339585A CN 108550696 A CN108550696 A CN 108550696A
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layer
phase
phase change
heating element
main surface
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CN201810339585.8A
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CN108550696B (en
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吴孝哲
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Beijing Times Full Core Storage Technology Co ltd
Being Advanced Memory Taiwan Ltd
Jiangsu Advanced Memory Semiconductor Co Ltd
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British Vigin Islands Manufacturer Epoch Quan Xin Science And Technology Ltd
Jiangsu Advanced Memory Technology Co Ltd
Jiangsu Advanced Memory Semiconductor Co Ltd
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20Multistable switching devices, e.g. memristors
    • H10N70/231Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011Manufacture or treatment of multistable switching devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801Constructional details of multistable switching devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801Constructional details of multistable switching devices
    • H10N70/861Thermal details
    • H10N70/8613Heating or cooling means other than resistive heating electrodes, e.g. heater in parallel

Abstract

The invention discloses a kind of phase-change memories.Phase-change memory includes phase change layer, conductive layer, heating element, the first felt pad and contact structures.Phase change layer has a main surface, and conductive layer is located at the side of the main surface of phase change layer, and is electrically connected phase change layer.The main surface of heating element contact phase change layer.First felt pad contacts the main surface of phase change layer, and includes opposite first side and second side, contacts heating element and conductive layer respectively.Contact structures are electrically connected heating element.This phase-change memory has low production cost, the quality of stabilization and high mnemon density.

Description

Phase-change memory
The application be the applying date be on 03 08th, 2016, application No. is 201610130129.3, entitled " phase transformations The divisional application of the patent application of the method changed memory body and manufacture phase-change memory ".
Technical field
The invention relates to a kind of phase-change memory and the methods for manufacturing phase-change memory.
Background technology
Computer or other electronic devices are commonly configured with various types of memory bodys, such as random access memory (RAM), read-only memory (ROM), Dynamic Random Access Memory (DRAM), synchronous dynamic random-access memory body (SDRAM), Phase change random access memory (PCRAM) or fast flash memory bank.Phase-change memory is non-volatile memory body, can be passed through It measures the resistance value of memory cell and obtains and be stored in data therein.In general, phase-change memory unit includes to add Thermal element and phase change cell, phase change cell can be because be heated and undergoing phase transition.When being passed through electric current to heating element, Heating element converts electric energy into heat, and generated heat promotes phase change cell to occur the change of phase, such as from amorphous phase (amorphous) it is transformed into polycrystalline phase (polycrystalline).Phase change cell mutually has different resistance in different Value is just able to judge the data types of memory cell via the resistance value for detecting or reading phase change cell.For phase change For memory body manufacturer, further decreases the manufacturing cost of memory body and improve the quality of memory body, be always effort Target.
Invention content
It is an aspect of the present invention to provide a kind of phase-change memories.This phase-change memory includes a phase change layer, one Conductive layer, a heating element, one first felt pad and a contact structures.There is phase change layer a main surface to prolong in a plane It stretches and side surface contiguous main surface.Conductive layer is located at the side of the main surface of phase change layer and separate side surface, and conductive Layer is electrically connected phase change layer.The main surface of heating element contact phase change layer.First felt pad contacts the main table of phase change layer Face, and include an opposite first side and a second side, first side and second side contact respectively heating element with And conductive layer.The side surface of contact structures and phase change layer is at a distance, the side surface of the parallel phase change layer of contact structures, and Contact structures are electrically connected heating element.
In some embodiments, heating element includes opposite a first side wall and a second sidewall, the first side wall Contact the first side of the first felt pad.
In some embodiments, the phase-change memory also includes one first dielectric layer, is located at phase change layer Top, and substantial parallel main surface.Conductive layer, heating element and the first felt pad are interposed in the first dielectric layer and phase change layer Between.
In some embodiments, the phase-change memory also includes one second dielectric layer, is located at phase change layer Lower section, and substantial parallel main surface.Phase change layer is interposed in conductive layer, heating element and the first felt pad and the second dielectric layer Between.
In some embodiments, the phase-change memory also includes one second felt pad and semiconductor knot Structure.Second felt pad contacts the second sidewall of heating element.Semiconductor structure runs through the second felt pad, and adds with one end insertion The second sidewall of thermal element.Contact structures are electrically connected heating element via semiconductor structure.
In some embodiments, a direction of the substantially vertical main surface of contact structures extends, and contact structures connect Touch semiconductor structure.
In some embodiments, the phase-change memory also includes one first dielectric layer, is located at phase change layer Top, and substantial parallel main surface, wherein conductive layer, heating element, the first felt pad and the second felt pad are interposed in first Between dielectric layer and phase change layer.
In some embodiments, the phase-change memory also includes one second dielectric layer, is located at phase change layer Lower section, and substantial parallel main surface, wherein phase change layer are interposed in conductive layer, heating element, the first felt pad and second absolutely Between edge pad and the second dielectric layer.
In some embodiments, contact structures include a conductive barrier layers and a conductive column.The one of conductive barrier layers Side is contacted with the first dielectric layer, semiconductor structure and the first insulating layer.Another side contacts of conductive column and conductive barrier layers.
In some embodiments, semiconductor structure is a diode structure.
Description of the drawings
Figure 1A is painted the flow chart of the method for the manufacture phase-change memory according to the various embodiments of the present invention;
Figure 1B is painted the step flow chart according to the certain preferred embodiments of the present invention;
Fig. 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A and 12A are painted certain embodiments of the present invention in different systems respectively The upper schematic diagram in journey stage;
Fig. 2 B, 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B and 12B are painted certain embodiments of the present invention in different systems respectively Diagrammatic cross-section of the journey stage along line segment B-B ';
Fig. 2 C, 3C, 4C, 5C, 6C, 7C, 8C, 9C, 10C and 12C are painted certain embodiments of the present invention in different systems respectively Diagrammatic cross-section of the journey stage along line segment C-C ';
Fig. 2 D, 3D, 4D, 5D, 6D, 7D, 8D, 9D, 10D and 12D are painted certain embodiments of the present invention in different systems respectively Diagrammatic cross-section of the journey stage along line segment D-D ';
Fig. 6 B-1,6D-1,7B-1,7D-1,8B-1,8D-1,9B-1,9D-1,10B-1 are respectively partial enlarged view;
Figure 11 is painted the enlarged drawing of each phase change mnemon in Figure 10 D.
Specific implementation mode
In order to make the description of the present invention more exhaustive and complete, the state sample implementation below for the present invention and specific implementation Example proposes illustrative description;But this not implements or uses the unique forms of the specific embodiment of the invention.It is disclosed below Each embodiment, beneficial in the case of can be combined with each other or replace, can also add others embodiments in one embodiment, and Without further record or explanation.
In the following description, many specific details be will be described in detail so that reader can fully understand embodiment below. However, the embodiment of the present invention can be put into practice without these specific details.In other cases, ripe to simplify attached drawing The structure known only symbolically is illustrated in figure with device.
Space relative terms used herein, for example, " lower section ", " under ", " top ", " on " etc., this is in order to just Relativeness between one elements or features of narration and another elements or features, as depicted in figure.These phases spatially True meaning to term includes other orientation.For example, when diagram spins upside down 180 degree, an element and another element it Between relationship, may from " lower section ", " under " become " top ", " on ".In addition, spatially opposite used herein Narration also should be explained similarly.
It is an aspect of the present invention to provide a kind of methods of manufacture phase-change memory.Figure 1A is painted various according to the present invention The flow chart of the method 1 of the manufacture phase-change memory of embodiment.Method 1 includes operation 10, operation 20, operation 30, operation 40, operation 50, operation 60 and operation 70.Fig. 2A to Figure 12 C is painted the various embodiments of the present invention in different process stages Schematic diagram.Although hereinafter illustrating the method disclosed herein using a series of operation or step, these operations or step The limitation of the present invention is sequentially not necessarily to be construed as shown in rapid.For example, it is certain operation or step can by different order carry out and/ Or it is carried out at the same time with other steps.In addition, it is not necessary to which embodiments of the present invention could be realized by executing all the step of being painted. In addition, each operation in this or step can include several sub-steps or action.
In operation 10, multiple stepped constructions are formed.Fig. 2A is painted certain embodiments of the present invention after executing operation 10 Upper schematic diagram, Fig. 2 B, 2C and 2D be painted respectively in Fig. 2A the section along B-B ' line segments, C-C ' line segments and D-D ' line segments signal Figure.As shown in Fig. 2 B and 2D, each stepped construction 110 includes multiple dielectric layers 112, multiple phase-change material layers 114 and multiple leads Electric layer 116.Each conductive layer 116 and each phase-change material layer 114 are interposed between two adjacent dielectric layers 112.In certain realities It applies in mode, repeatedly deposited in sequential dielectric layer 112, phase-change material layer 114 and conductive layer on semiconductor substrate 102 116.Then, a protective layer 108 is formed on the dielectric layer of top layer 112, the material of protective layer 108 may be, for example, silicon nitride (SiN), but not limited to this.Protective layer 108 can also be that other isolation protective materials are formed, such as silica (SiO2), aluminium oxide (Al2O3), aluminium nitride (AlN), glass or similar material or combinations of the above.Later, it is lost using lithographic It scribes journey and forms multiple stepped constructions 110.For example, photoresist layer 104 can be patterned by formation to define stepped construction 110 Pattern, then carry out dry type anisotropic etching and form stepped construction 110, later remove patterning photoresist layer 104. Phase-change material layer 114 and the sedimentary sequence of conductive layer 116 can change, such as in other certain embodiments, be to repeat Ground deposited in sequential dielectric layer 112, conductive layer 116 and phase-change material layer 114.
Dielectric layer 112 can include any suitable dielectric material, such as silicon nitride, silica, doping silica glass etc. Dielectric material, dielectric layer 112 can also be formed by the dielectric material of low-k, such as phosphosilicate glass (PSG), boron Phosphorosilicate glass (BPSG), fluorine silica glass (FSG), carbofrax material or combinations of the above or similar material.The thickness of dielectric layer 112 Degree can be adjusted according to actual demand, for example, about 5nm to about 300nm.
In some embodiments, phase-change material layer 114 includes germanium-antimony-tellurium (GST) material, such as Ge2Sb2Te5、 Ge1Sb2Te4、Ge1Sb4Te7Or combinations of the above or similar material.Other phase-transition materials may be, for example, GeTe, Sb2Te3、 GaSb、InSb、Al-Te、Te-Sn-Se、Ge-Sb-Te、In-Sb-Te、Ge-Se-Ga、Bi-Se-Sb、Ga-Se-Te、Sn-Sb- Te、In-Sb-Ge、Te-Ge-Sb-S、Te-Ge-Sn-O、Sb-Te-Bi-Se、Te-Ge-Sn-Au、Pd-Te-Ge-Sn、In-Se- Ti-Co, Ge-Sb-Te-Pd, Ag-In-Sb-Te, Ge-Te-Sn-Pt, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd and Ge-Sb-Se- Te.The thickness of phase-change material layer 114 can be adjusted according to actual demand, for example, about 5nm to about 100nm.
In certain embodiments, the pattern of stepped construction 110 is vertical bar shape, the conductive layer 116 in stepped construction 110 Word-line (word line) as phase-change memory.The material of conductive layer 116 may be, for example, the metal material for including tungsten (W) Material, conductive layer 116 can also include other metal materials, for example, titanium (Ti), aluminium (Al), copper (Cu), silver-colored (Ag), golden (Au) or The combination of above-mentioned material or similar material.The thickness of conductive layer 116 can be adjusted according to actual demand, and for example, about 5nm is to about 100nm。
In subsequent Fig. 3 A to 10C, the attached drawing of alphabetical " A ", such as the figures such as Fig. 3 A, 4A, 5A are included in accompanying drawing number, is Upper schematic diagram;Include the attached drawing of primary and secondary " B ", such as the figures such as Fig. 3 B, 4B, 5B in accompanying drawing number, for along the section of line segment B-B ' Schematic diagram;Include the attached drawing of primary and secondary " C ", such as the figures such as Fig. 3 C, 4C, 5C in accompanying drawing number, to illustrate along the section of line segment C-C ' Figure;Include the attached drawing of primary and secondary " D ", such as the figures such as Fig. 3 D, 4D, 5D in accompanying drawing number, for along the diagrammatic cross-section of line segment D-D '.
In the operation 20 of Figure 1A, insulating layer is formed between two adjacent stepped constructions, insulating layer has at least one A contact holes exposing goes out the side wall of stepped construction.Fig. 3 A-3D and Fig. 4 A-4D are painted the realization operation of certain embodiments of the present invention 20 schematic diagram.First, as shown in figs. 3 a-3d, insulating layer 120 is formed between two adjacent stepped constructions 110.For example, It first uses deposition manufacture process to deposit one layer of insulation material layer and covers stepped construction 110, and fill up between two adjacent stepped constructions 110 Gap.Then, it carries out CMP step and removes the insulation material layer for being deposited on the top of each stepped construction 110, and Insulating layer 120 is formed between two neighboring stepped construction.Then, as shown in figs. 4 a-4d, pattern is formed above insulating layer 120 Change photoresist layer 106, and carry out etch process, therefore forms at least one contact hole 122 in insulating layer 120.As shown in Figure 4 D, Contact hole 122 expose the sidewall sections 112a of each dielectric layer 112, each phase-change material layer 114 sidewall sections 114a and The sidewall sections 116a of each conductive layer 116.
In the operation 30 of Figure 1A, the sidewall sections that each conductive layer exposes are removed, in adjacent dielectric layer and phase transformation First gap is formed between change material layer.Fig. 5 A-5D are please referred to, the side wall of the exposing of each conductive layer 116 is removed via contact hole 122 Part 116a, and between adjacent dielectric layer 112 and phase-change material layer 114 formed first gap 131 (be shown in Fig. 5 A, In 5B and 5D).Multiple embodiments according to the present invention carry out operation 30 using wet etch process.Wet etch process Etchant etches the sidewall sections 116a of each conductive layer 116 via contact hole 122, and forms first gap 131, so first is empty Gap 131 is interconnected with contact hole 122.In addition, because wet etching is isotropic etching, the side X that etchant can be painted from Fig. 5 A To and Y-direction the conductive layer 116 of stepped construction 110 is etched, therefore the width W1 for being formed by first gap 131 is big In the width Z of contact hole 122.In one embodiment, when 116 packet tungstenic material of conductive layer, wet etch process can be selected With containing hydrogen peroxide (H2O2) etchant.In some embodiments, the height of first gap 131 is substantially by conduction The thickness of layer 116 is determined.
In the operation 40 of Figure 1A, insulating materials 140 is formed in each first gap 131, such as Fig. 5 A-5D.In certain realities It applies in example, uses one layer of insulation material layer of deposition of such as chemical vapor deposition or atomic layer deposition processing procedure whole face, this insulation Material layer fills up first gap 131, and is coated in other structures;Then anisotropic etch process is carried out, position is removed and exists Insulation material layer other than first gap 131, and obtain the insulating materials being filled in first gap 131 140.In various implementations In mode, the thickness of insulating materials 140 is substantially identical as the thickness of conductive layer 116, and the sidewall sections of insulating materials 140 142 expose and (are painted in figure 5d) via contact hole 122.In addition, the width of insulating materials 140 is substantially equal to first gap 131 width W1.Multiple embodiments according to the present invention, insulating materials 140 are that different materials is made from dielectric layer 112 At.For example, insulating materials 140 may be, for example, alundum (Al2O3) or similar material, and dielectric layer 112 may be, for example, silica Or similar material.
In operation 50, the sidewall sections 142 of each insulating materials 140 are removed, and form multiple Second gaps 132, are such as schemed Shown in 6A to 6D-1, wherein Fig. 6 B-1 are the enlarged drawing of region F1 in Fig. 6 B, and Fig. 6 D-1 are the enlarged drawing of region F2 in Fig. 6 D.Root According to multiple embodiments of the present invention, etchant appropriate is selected, and each insulating materials 140 is removed using wet etch process Sidewall sections 142, and form Second gap 132.Selected etchant is necessary for insulating materials 140 and dielectric layer 112 With appropriate selection ratio, etchant is allowed not remove the side wall of dielectric layer 112 substantially, but insulation material can be effectively removed The sidewall sections 142 of material 140, so could form Second gap 132.For example, when the composition material of insulating materials 140 is Alundum (Al2O3) when the composition material of dielectric layer 112 is silica, can select the etchant containing potassium hydroxide (KOH) The sidewall sections 142 of each insulating materials 140 are etched, and form Second gap 132.Because wet etching is isotropic etching, etching The X-direction and Y-direction that agent can be painted from Fig. 5 A are etched insulating materials 140, therefore are formed by Second gap 132 Width W2 is more than the width Z of contact hole 122.
In operation 60, heating material layer 150 is formed in each Second gap 132.Operation 60 and subsequent operation or step Suddenly there are a variety of possible variations.According to some embodiments of the present invention, optionally example is formed in Second gap 132 Such as diode semiconductor structure.But the necessary component of the semiconductor structure in Second gap and non-present invention;In other realities It applies in mode, semiconductor structure can not be formed in Second gap.
Following detailed description forms the step of diode structure according to certain embodiments of the present invention in Second gap 132 Suddenly.First, operation 60 further includes to form the first type semi-conducting material 160 in each Second gap 132, such as Fig. 6 A-6D It is shown.First type semi-conducting material 160 is laterally embedded in each heating material layer 150 from contact hole 122, as shown in Figure 6 D.Have Various ways can form the structure that 6A-6D is painted.In one embodiment, one is conformally formed with atomic layer deposition processing procedure first The sedimentary of the sedimentary of layer heating material, this heating material is coated on the inner surface of Second gap 132 and other knots On structure, but heating material sedimentary does not fill up Second gap 132 and/or contact hole 122.Then, in heating material sedimentary The first type semiconductor material layer of upper formation, the first type semiconductor material layer fill up the remaining space of Second gap 132.Later, into The anisotropic etch process of row removes heating material sedimentary and first type semi-conducting material of the position other than Second gap 132 Layer, and obtain the heating material layer being filled in Second gap 132 150 and the first type semi-conducting material 160.To obtain It is laterally embedded into the first type semi-conducting material 160 of heating material layer 150, the first type semi-conducting material 160 may be, for example, P+ type Semi-conducting material.In certain embodiments, heating material layer 150 includes a first part 151 and a second part 152, is divided Not Wei Yu the first type semi-conducting material 160 over and under.In addition, the width of heating material layer 150 is substantially equal to second The width W2 in gap 132.
After forming the first type semi-conducting material 160, step 61, step 62, step 63, step that Figure 1B is painted are carried out 64, step 65 and step 66 just can be realized and form diode structure in Second gap 132.
In a step 61, a part for each heating material layer 150 is removed, and forms multiple third gaps 133, extremely such as Fig. 7 A Shown in 7D-1, wherein Fig. 7 B-1 are the enlarged drawing of region F3 in Fig. 7 B, and Fig. 7 D-1 are the enlarged drawing of region F4 in Fig. 7 D.According to this Multiple embodiments of invention, by wet etch process, and select etchant appropriate, respectively add to remove in contact hole 122 The exposed portion of hot material layer 150, and form third gap 133.For example, when heating material layer 150 includes for example to nitrogenize When the metal nitrides such as tantalum (TaN), it can select containing ammonium hydroxide (NH4) and hydrogen peroxide (H OH2O2) etchant move Except the exposed portion of each heating material layer 150, and form third gap 133.Because wet etching is isotropic etching, etchant meeting The X-direction and Y-direction being painted from Fig. 5 A are etched insulating materials 140, therefore are formed by the width in third gap 133 W3 is more than the width Z of contact hole 122.In some embodiments, third gap 133 includes gap 133a and gap 133b, empty Gap 133a and gap 133b is located at the first type semi-conducting material 160 over and under.
In step 62, the first insulation bolt 171 is formed in each third gap 133, as shown in 7A to 7D-1 figures.At certain In a little embodiments, using one layer of insulation material layer of deposition of such as chemical vapor deposition or technique for atomic layer deposition whole face, This insulation material layer fills up third gap 133, and is coated in other structures;Then anisotropic etch process is carried out, is removed Insulation material layer of the position other than third gap 133, and obtain the be filled in third gap 133 first insulation bolt 171.First The width of insulation bolt 171 is substantially equal to the width W3 in third gap 133.In one embodiment, the material of the first insulation bolt 171 For silicon nitride (SiN).In some embodiments, the first insulation bolt 171 includes insulation bolt 171a and insulation bolt 171b, and insulate bolt 171a and insulation bolt 171b are located at the first type semi-conducting material 160 over and under.In some embodiments, first The material of insulation bolt 171 can be identical or different with dielectric layer 112.In other certain embodiments, the material of the first insulation bolt 171 Material can be identical or different with insulating materials 140.
In step 63, a part for each first type semi-conducting material 160 is removed, and forms multiple 4th gaps 134, such as Shown in Fig. 8 A to 8D-1, wherein Fig. 8 B-1 are the enlarged drawing of region F5 in Fig. 8 B, and Fig. 8 D-1 are the enlarged drawing F6 in region in Fig. 8 D. In some embodiments, by wet etch process, and etchant appropriate is selected, each first is removed via contact hole 122 The sidewall sections that type semi-conducting material 160 exposes, and form the 4th gap 134.Because wet etching is isotropic etching, etchant The X-direction and the first type of Y-direction pair semi-conducting material 160 that can be painted from Fig. 5 A are etched, therefore are formed by the 4th sky The width W4 of gap 134 is more than the width Z of contact hole 122.
In step 64, second type semi-conducting material 180 is formed in each 4th gap 134, as shown in Fig. 8 A to 8D-1. Second type semi-conducting material 180 may include the semi-conducting material of such as N-type.In certain embodiments, using such as chemical gaseous phase One layer of second type semiconductor material layer of deposition of deposition or technique for atomic layer deposition whole face, this second type semi-conducting material fill up 4th gap 134, and be coated in other structures;Then carry out anisotropic etch process, remove position the 4th gap 134 with Outer second type semiconductor material layer, and formed and be embedded the second type semi-conducting material 180 in the 4th gap 134.Second type The width of semi-conducting material 180 is substantially equal to the width W4 in the 4th gap 134.Second type semi-conducting material 180 may be, for example, The semi-conducting material of N-type, second type semi-conducting material 180 is contacted with the first type semi-conducting material 160, and forms diode knot Structure 184.
In step 65, it removes each phase-change material layer 114 and is exposed to the sidewall sections 114a of contact hole 122 and (be indicated in In Fig. 8 D), and multiple 5th gaps 135 are formed, as shown in Fig. 9 A to 9D-1, wherein Fig. 9 B-1 are the amplification of region F7 in Fig. 9 B Figure, Fig. 9 D-1 are the enlarged drawing of region F8 in Fig. 9 D.Multiple embodiments according to the present invention, by wet etch process, and Etchant appropriate is selected, the sidewall sections that phase-change material layer 114 is exposed to contact hole 122 are removed by contact hole 122 114a, and form the 5th gap 135.For example, it when phase-change material layer 114 includes germanium-antimony-tellurium material, can select Etchant containing nitric acid (20wt%) removes the sidewall sections 114a of phase-change material layer 114, and forms the 5th gap 135.Because wet etching is isotropic etching, the X-direction and Y-direction that etchant can be painted from Fig. 5 A are to phase-change material layer 114 are etched, therefore the width W5 for being formed by the 5th gap 135 is more than the width Z of contact hole 122.
In the step 66, the second insulation bolt 172 is formed in each 5th gap 135, as shown in Fig. 9 A to 9D-1.At certain In a little embodiments, using one layer of insulation material layer of deposition of such as chemical vapor deposition or technique for atomic layer deposition whole face, this Insulation material layer fills up the 5th gap 135, and is coated in other structures;Then anisotropic etch process is carried out, position is removed Insulation material layer other than the 5th gap 135, and obtain being embedded the second insulation bolt 172 in the 5th gap 135.Second insulation The width of bolt 172 is substantially equal to the width W5 in the 5th gap 135.Second insulation bolt 172 obstructs phase-change material layer 114 and connects Contact hole 122 avoids phase-change material layer 114 from exposing via contact hole 122.In certain embodiments, the second insulation bolt 172 Composition material is identical as the first insulation composition material of bolt 171.
As it was noted above, according to other embodiments of the present invention, the semiconductors such as diode structure can not be formed Structure is in Second gap 132 (being indicated in Fig. 6 D).Therefore, the step of the first type of above-mentioned formation semi-conducting material 160 and above-mentioned Step 61-66 is only the preferred embodiment of the present invention.For example, when not forming semiconductor structure, described in operation 60 Heating material layer 150 can fill up Second gap 132.Then, remove each phase-change material layer 114 one described in step 65 is carried out Multiple 5th gaps 135 partly are formed, executes form the second insulation bolt described in step 66 in each 5th gap 135 later 172。
In operation 70, contact structures 190 are formed in contact hole 122, as shown in figures 10a-10d, wherein Figure 10 B-1 are The enlarged drawing of region F9 in Figure 10 B.In some embodiments, contact structures 190 include conductive barrier layers 191 and conductive column 192.In certain embodiments, one layer of conductive barrier material layer is conformally deposited first to be coated in contact hole 122, then sink again One layer of product fills up the remaining space in contact hole 122 comprising conductive material layer.In one embodiment, the conductive barrier material of deposition Layer and conductive material layer can be also deposited in the other structures other than contact hole 122, therefore after depositing conductive material layer, into Row CMP step removes conductive barrier material layer and the conductive material layer other than contact hole 122, to The phase-change memory structure being painted to Figure 10 A-10D.Figure 10 D are referred to, herein manufactured phase-change memory structure packet Containing multiple phase change mnemons 100.In some embodiments, the material of conductive barrier layers 191 may be, for example, titanium nitride, lead The material of electric column 192 may be, for example, the metal material comprising tungsten.Conductive barrier layers 191 are with to avoid the tungsten original in conductive column 192 Son is diffused into neighbouring structure.Contact structures 190 can also be other materials, for example, titanium (Ti), aluminium (Al), copper (Cu), Combination or the similar material of silver-colored (Ag), golden (Au) or above-mentioned material.Figure 11 is painted each phase change mnemon in Figure 10 D 100 enlarged drawing, hereafter by each element in more detailed narration Figure 11.
After executing operation 70, optionally other structures are formed in contact structures 190.For example, as schemed Shown in 12A-12D, bit line (bit line) 194 is formed in contact structures 190.Bit line 194 is via contact structures 190, two poles Body structure 184 and heating material layer 150 and be electrically connected phase-change material layer 114.
In the phase-change memory of known three-dimensional, it is necessary to repeatedly carry out depositing-lithographic-etch process, could make Make three-dimensional phase-change memory.It is first repeatedly deposited in sequential dielectric layer 112, phase-transition material in the method disclosed at this Layer 114 and conductive layer 116, then forms multiple stepped constructions 110 using a micro image etching procedure, thus can reduce into The number of row lithographic-etch process, to reduce the production cost of phase-change memory.In addition, phase-change material layer 114 is heavy Product in the plane, so can be formed using physical gas phase deposition technology, without using chemical vapor deposition process or atom Layer deposition manufacture process.In known technology, when forming phase change layer using chemical vapour deposition technique or technique for atomic layer deposition When, it can often face the bad problem of the film layer quality of deposition.Therefore, the shortcomings that method disclosed herein improves known technology.
According to content disclosed above, another aspect of the present invention is to provide a kind of phase-change memory.Figure 11 is please referred to, Phase-change memory 200 includes phase change layer 210, conductive layer 220, heating element 230, the first felt pad 240 and contact knot Structure 250.There are one main surface 210a, main surface 210a to extend in a plane for the tool of phase change layer 210.Conductive layer 220 is located at phase The side of the main surface 210a of change layer 210, and it is electrically connected phase change layer 210.In some embodiments, conductive layer The main surface 210a of 220 contact phase change layers 210, and substantial parallel phase change layer 210.Heating element 230 contacts phase change The main surface 210a of layer 210.In some embodiments, heating element 230 includes opposite the first side wall 231 and the second side Wall 232.In various embodiments, heating element 230 also includes a third face 233, and third face 233 abuts the first side wall 231 And second sidewall 232, and the third face 233 of heating element 230 contacts the main surface 210a of phase change layer 210.In addition, first Felt pad 240 contacts the main surface 210a of phase change layer 210, and the first felt pad 240 includes opposite first side 241 and the Two side faces 242, first side 241 and second side 242 contact heating element 230 and conductive layer 220 respectively.Contact structures 250 are electrically connected heating element 230.In some embodiments, contact structures 250 include conductive barrier layers 251 and conduction Column 252.
In multiple embodiments, phase-change memory 200 also includes the second felt pad 260 and semiconductor structure 270. Second felt pad 260 contacts the second sidewall 232 of heating element 230.Semiconductor structure 270 extends transversely through the second felt pad 260, And semiconductor structure 270 has the second sidewall 232 that one end 272 is embedded in heating element 230.Contact structures 250 are via half Conductor structure 270 is electrically connected heating element 230.In one embodiment, contact structures 250 are substantially perpendicular to phase change layer The side of 210 main surface 210a upwardly extends, and the conductive barrier layers 251 of contact structures 250 are in direct contact semiconductor structure 270.When phase-change memory is in mode of operation, the pipeline of electric current as shown in the path E of Figure 11, from contact tie by electric current Structure 250 is transmitted to heating element 230 via semiconductor structure 270, then is transmitted to from heating element 230 via phase change layer 210 Conductive layer 220.The long range conduction of electric current is mainly transmitted via conductive column 251, only when electric current is in conductive column 252 and half When being conducted between conductor structure 270, electric current can just pass through the conductive barrier layers between conductive column 252 and semiconductor structure 270 251.When electric current is by heating element 230, the electric energy of part is changed into heat by heating element 230, and passes through heating element 230 Third face 233 phase change layer 210 is heated, make to contact heating element 230 in the main surface 210a of phase change layer 210 Undergoing phase transition of part, and achieve the purpose that store data.It, can be with as it was noted above, according to some embodiments of the present invention Semiconductor structure 270 is not formed, in these embodiments, electric current can be transmitted to heating element 230 from contact structures 250, Again conductive layer 220 is transmitted to from heating element 230 via phase change layer 210;Or electric current can be transmitted to phase from conductive layer 220 Change layer 210, then it is transmitted to conductive layer 220 from phase change layer 210 via heating element 230.
In another embodiment, phase-change memory 200 also includes the first dielectric layer 281 and the second dielectric layer 282. First dielectric layer 281 is located at the top of phase change layer 210, and the main surface 210a of substantial parallel phase change layer 210.It is conductive Layer 220, heating element 230 and the first felt pad 240 are interposed between the first dielectric layer 281 and phase change layer 210.Second is situated between Electric layer 282 is configured in the lower section of phase change layer 210.
Although the present invention is disclosed above with embodiment, however, it is not to limit the invention, any to be familiar with this skill Person, without departing from the spirit and scope of the present invention, when can be used for a variety of modifications and variations, therefore protection scope of the present invention is worked as Subject to the scope of which is defined in the appended claims.

Claims (10)

1. a kind of phase-change memory, which is characterized in that include:
There is one phase change layer a main surface to extend in a plane and the side surface contiguous main surface;
One conductive layer is located at the side of the main surface of the phase change layer and the separate side surface, and the conductive layer is electrically connected The phase change layer;
One heating element contacts the main surface of the phase change layer;
One first felt pad, contacts the main surface of the phase change layer, and includes opposite a first side and a second side Face, the first side and the second side contact the heating element and the conductive layer respectively;And
One contact structures, at a distance with the side surface of the phase change layer, the parallel phase change layer of the contact structures is somebody's turn to do Side surface, and the contact structures are electrically connected the heating element.
2. phase-change memory as described in claim 1, which is characterized in that wherein the heating element includes opposite one first Side wall and a second sidewall, the first side wall contact the first side of first felt pad.
3. phase-change memory as described in claim 1, which is characterized in that also include:
One first dielectric layer, be located at the phase change layer top, and the substantial parallel main surface, the wherein conductive layer, should plus Thermal element and first felt pad are interposed between first dielectric layer and the phase change layer.
4. phase-change memory as claimed in claim 3, which is characterized in that also include:
One second dielectric layer is located at the lower section of the phase change layer, and the substantial parallel main surface, the wherein phase change layer are sandwiched Between the conductive layer, the heating element and first felt pad and second dielectric layer.
5. phase-change memory as claimed in claim 2, which is characterized in that also include:
One second felt pad contacts the second sidewall of the heating element;And
Semiconductor structure runs through second felt pad, and the second sidewall of the heating element is embedded in one end;
Wherein the contact structures are electrically connected the heating element via the semiconductor structure.
6. phase-change memory as claimed in claim 5, which is characterized in that wherein the contact structures are in the vertical main surface One direction extends, and the contact structures contact the semiconductor structure.
7. phase-change memory as claimed in claim 5, which is characterized in that also include:
One first dielectric layer, be located at the phase change layer top, and the substantial parallel main surface, the wherein conductive layer, should plus Thermal element, first felt pad and second felt pad are interposed between first dielectric layer and the phase change layer.
8. phase-change memory as claimed in claim 7, which is characterized in that also include:
One second dielectric layer is located at the lower section of the phase change layer, and the substantial parallel main surface, the wherein phase change layer are sandwiched Between the conductive layer, the heating element, first felt pad and second felt pad and second dielectric layer.
9. phase-change memory as claimed in claim 5, which is characterized in that wherein the contact structures include:
One conductive barrier layers, the side of the conductive barrier layers and first dielectric layer, the semiconductor structure and first insulating layer Contact;And
Another side contacts of one conductive column and the conductive barrier layers.
10. such as claim 5 to 9 any one of them phase-change memory, which is characterized in that the semiconductor structure is one or two poles Body structure.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101000945A (en) * 2006-01-09 2007-07-18 财团法人工业技术研究院 Phase storage element andmanuafcturing method thereof
CN101241925A (en) * 2007-02-09 2008-08-13 财团法人工业技术研究院 Phase change memory device and its making method
CN101271862A (en) * 2007-03-19 2008-09-24 财团法人工业技术研究院 Memory element and manufacturing method thereof
US20150162528A1 (en) * 2010-08-31 2015-06-11 International Business Machines Corporation Post-fabrication self-aligned initialization of integrated devices
CN105098071A (en) * 2015-07-08 2015-11-25 宁波时代全芯科技有限公司 Method for manufacturing phase-change memory

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8173987B2 (en) * 2009-04-27 2012-05-08 Macronix International Co., Ltd. Integrated circuit 3D phase change memory array and manufacturing method
CN102148261B (en) * 2010-02-10 2013-01-23 中国科学院微电子研究所 Manufacturing method of capacitor structure
CN104733469B (en) * 2010-06-30 2018-11-06 桑迪士克科技有限责任公司 Ultra high density vertically with non-memory device and its manufacturing method
KR20130139602A (en) * 2012-06-13 2013-12-23 에스케이하이닉스 주식회사 Semiconductor device, memory system comprising the same and method of manufacturing the same
US9099637B2 (en) * 2013-03-28 2015-08-04 Intellectual Discovery Co., Ltd. Phase change memory and method of fabricating the phase change memory
CN105304638A (en) * 2015-11-16 2016-02-03 上海新储集成电路有限公司 Three-dimensional phase change memory structure and manufacturing structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101000945A (en) * 2006-01-09 2007-07-18 财团法人工业技术研究院 Phase storage element andmanuafcturing method thereof
CN101241925A (en) * 2007-02-09 2008-08-13 财团法人工业技术研究院 Phase change memory device and its making method
CN101271862A (en) * 2007-03-19 2008-09-24 财团法人工业技术研究院 Memory element and manufacturing method thereof
US20150162528A1 (en) * 2010-08-31 2015-06-11 International Business Machines Corporation Post-fabrication self-aligned initialization of integrated devices
CN105098071A (en) * 2015-07-08 2015-11-25 宁波时代全芯科技有限公司 Method for manufacturing phase-change memory

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