CN105742488B - Phase-change memory and the method for manufacturing phase-change memory - Google Patents
Phase-change memory and the method for manufacturing phase-change memory Download PDFInfo
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- CN105742488B CN105742488B CN201610107332.9A CN201610107332A CN105742488B CN 105742488 B CN105742488 B CN 105742488B CN 201610107332 A CN201610107332 A CN 201610107332A CN 105742488 B CN105742488 B CN 105742488B
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- 230000015654 memory Effects 0.000 title claims abstract description 40
- 238000000034 method Methods 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 230000008859 change Effects 0.000 claims abstract description 38
- 239000004020 conductor Substances 0.000 claims abstract description 36
- 238000010276 construction Methods 0.000 claims abstract description 31
- 238000010438 heat treatment Methods 0.000 claims description 62
- 239000004065 semiconductor Substances 0.000 claims description 22
- 239000000463 material Substances 0.000 abstract description 35
- 239000012212 insulator Substances 0.000 abstract 1
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- 238000000151 deposition Methods 0.000 description 9
- 239000003989 dielectric material Substances 0.000 description 9
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- 239000005360 phosphosilicate glass Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000012774 insulation material Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000012782 phase change material Substances 0.000 description 3
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 229910018110 Se—Te Inorganic materials 0.000 description 2
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- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
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- 229910005542 GaSb Inorganic materials 0.000 description 1
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- 229910020938 Sn-Ni Inorganic materials 0.000 description 1
- 229910020923 Sn-O Inorganic materials 0.000 description 1
- 229910002855 Sn-Pd Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/861—Thermal details
- H10N70/8613—Heating or cooling means other than resistive heating electrodes, e.g. heater in parallel
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- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
A kind of phase-change memory and the method for manufacturing phase-change memory.Phase-change memory includes stepped construction, contact structures, second insulating layer and phase change structure with multiple first conductor wires and multiple first insulating layers.First conductor wire is interposed between two neighboring first insulator layers, and each first conductor wire includes notch portion.Contact structures are substantially upwardly extended perpendicular to the side of each first conductor wire, and contact structures correspond to the notch portion of each first conductor wire.Second insulating layer covers a part for the notch portion of each first conductor wire, and another part of notch portion is not covered by second insulating layer.Phase change structure surrounds contact structures, and comprising first part and second part, first part is interposed between contact structures and second insulating layer, and second part material contact is not by described another part of each notch portion of second insulating layer covering.
Description
Technical field
The invention relates to a kind of phase-change memory and a kind of methods for manufacturing phase-change memory.
Background technology
Computer or other electronic devices are commonly configured with various types of memory bodys, such as random access memory
(RAM), read-only memory (ROM), Dynamic Random Access Memory (DRAM), synchronous dynamic random-access memory body (SDRAM),
Phase change random access memory (PCRAM) or fast flash memory bank.Phase-change memory is non-volatile memory body, can be passed through
It measures the resistance value of memory cell and obtains and be stored in data therein.Add in general, phase-change memory unit includes
Thermal element and phase change cell, phase change cell can be because be heated and undergoing phase transition.When being passed through electric current to heating element,
Heating element converts electric energy into heat, and generated heat promotes phase change cell to occur the change of phase, such as from amorphous phase
(amorphous) it is transformed into polycrystalline phase (polycrystalline).Phase change cell mutually has different resistance in different
Value via the resistance value for detecting or reading phase change cell, is just able to judge the data types of memory cell.How to improve and write
Enter the speed of data and reliability is always target that memory body manufacturer makes great efforts.
Invention content
It is an aspect of the present invention to provide a kind of phase-change memories.This phase-change memory has minimum effective heating
Region, so as to allow effective heating area domain can have high current density, therefore effectively improve write-in data speed and can
By degree.
According in the various embodiments of the present invention, this phase-change memory includes a stepped construction, a contact structures, one the
Two insulating layers and a phase change structure.Stepped construction include multiple first conductor wires and multiple first insulating layers, each first
Conductor wire is interposed between first insulating layer of adjacent two, and each first conductor wire includes a notch portion.Contact structures exist
It is upwardly extended substantially perpendicular to the side of each first conductor wire, and contact structures correspond to the notch portion of each first conductor wire.The
Two insulating layers cover a part for the notch portion of each first conductor wire, and another part of each notch portion is not covered by second insulating layer
Lid.Phase change structure surrounds contact structures, and phase change structure includes a first part and a second part, first part are sandwiched
Between contact structures and second insulating layer, second part material contact is not described in each notch portion of second insulating layer covering
Another part.
In some embodiments, each first conductor wire is also comprising a heating element, the part contact of heating element the
Two insulating layers, and the second part of another part contact phase change structure of heating element.
In some embodiments, each first conductor wire also includes a diode structure and a conductive layer, and diode
Structure is between heating element and metal layer.
In some embodiments, it is 3nm to 20nm that another part of the heating element, which has a width,.
In some embodiments, each first conductor wire is also comprising a straight line portion, straight line portion connection notch portion, and notch portion
Minimum widith for straight line portion width 40% to 60%.
Another aspect of the present invention is to provide a kind of method for manufacturing phase-change memory.It is operated below the method：(i) shape
Into multiple stepped constructions, each stepped construction includes multiple conductive layers and multiple first insulating layers, each conductive layer are interposed in adjacent
Two first insulating layers between；(ii) dielectric layer is formed, is filled between two adjacent stepped constructions；
(iii) part for a part for removal dielectric layer, a part for each conductive layer and each first insulating layer, to form a contact
Hole exposes the side wall part of each conductive layer；(iv) sidewall sections of each conductive layer are removed, in office two adjacent described the
A gap is formed between one insulating layer；(v) heating element is formed in each gap；(vi) second insulating layer covering is formed to connect
A part for each heating element in contact hole, and second insulating layer does not cover another part of each heating element；(vii) phase is formed
Change structure in contact hole, the part contact second insulating layer of phase change structure, and another part of phase change structure connects
Touch described another part of each heating element；And (viii) forms a contact structures in contact hole.
In some embodiments, the above method is after interstitial operation, but before the operation of heating element is formed,
Also include：A diode structure is formed in each gap, wherein diode structure is between conductive layer and heating element.
In some embodiments, described the step of diode structure is formed in each gap, includes：The shape in each gap
Into one first type semiconductor structure and a Second-Type semiconductor structure.
In some embodiments, the operation for forming contact hole includes：A narrow portion is formed in each conductive layer, each narrow portion
Width is the 40% to 60% of the original width of each conductive layer.
In some embodiments, in the operation for forming second insulating layer, described another part of each heating element
Width is 3nm to 20nm.
Description of the drawings
Fig. 1 is painted the flow chart of the method for the manufacture phase-change memory according to the various embodiments of the present invention；
Fig. 2A, 3A, 4A, 5A, 6A, 7A, 8A and 9A are painted certain embodiments of the present invention in different process stages respectively
Upper schematic diagram；
Fig. 2 B, 3B, 4B, 5B, 6B, 7B, 8B and 9B are painted certain embodiments of the present invention on different process stage edges respectively
The diagrammatic cross-section of line segment B-B '；
Fig. 2 C, 3C, 4C, 5C, 6C, 7C, 8C and 9C are painted certain embodiments of the present invention on different process stage edges respectively
The diagrammatic cross-section of line segment C-C '.
Specific embodiment
In order to make the description of the present invention more exhaustive and complete, below for embodiments of the present invention and specific implementation
Example proposes illustrative description；But this not implements or the unique forms with the specific embodiment of the invention.It is disclosed below
Each embodiment, beneficial in the case of can be combined with each other or replace, can also add others embodiments in one embodiment, and
Without further record or explanation.
In the following description, many specific details be will be described in detail so that reader can fully understand following embodiment.
However, the embodiment of the present invention can be put into practice in the case of without these specific details.In other cases, it is ripe to simplify attached drawing
The structure known only symbolically is illustrated in figure with device.
Space relative terms used herein, for example, " lower section ", " under ", " top ", " on " etc., this is in order to just
Relativeness between one elements or features of narration and another elements or features, as depicted in figure.These phases spatially
Other orientation are included to the true meaning of term.For example, when diagram spins upside down 180 degree, an element and another element it
Between relationship, may from " lower section ", " under " become " top ", " on ".In addition, spatially opposite used herein
Narration also should be explained similarly.
It is an aspect of the present invention to provide a kind of methods for manufacturing phase-change memory.Fig. 1 is painted various according to the present invention
The flow chart of the method 1 of the manufacture phase-change memory of embodiment.Method 1 includes operation 10, operation 20, operation 30, operation
40th, operation 50, operation 60, operation 70 and operation 80.Fig. 2A to Fig. 8 C is painted the operations 10 of various embodiments to operation 80
The schematic diagram of middle difference process stage.Although hereinafter illustrating the method disclosed herein using a series of operation or step,
But these operation or step shown in sequence be not necessarily to be construed as the present invention limitation.For example, certain operations or step can be with
It carries out by different order and/or is carried out at the same time with other steps.In addition, it is not necessary to which performing all the step of being painted could realize
Embodiments of the present invention.In addition, each operation in this or step can include several sub-steps or action.
In operation 10, multiple stepped constructions are formed.Fig. 2A is painted certain embodiments of the present invention after operation 10 is performed
Upper schematic diagram, Fig. 2 B and Fig. 2 C is painted in Fig. 2A respectively along the diagrammatic cross-section of line segment B-B ' and C-C '.Such as Fig. 2A-Fig. 2 C
It is shown, multiple stepped constructions 110 are formed on semiconductor base material 102, each stepped construction 110 includes multiple conductive layers
112 and multiple first insulating layers 114, each conductive layer 112 be interposed between two adjacent the first insulating layers 114.At certain
In a little embodiments, 112 and first insulating layer 114 of conductive layer is alternately deposited using physically or chemically deposition manufacture process, then
Multiple stepped constructions 110 are formed using micro image etching procedure.For example, photoresist layer is patterned by formation to define stepped construction
Then 110 pattern carries out dry-etching and forms stepped construction 110, removes photoresist layer later.In some embodiments
In, the pattern of stepped construction 110 is vertical bar shape, word of the conductive layer 112 in stepped construction 110 as phase-change memory
First line (word line).The material of conductive layer 112 may be, for example, the metal material for including tungsten (W), and conductive layer 112 can also wrap
Containing other metal materials, such as titanium (Ti), the combination or similar of aluminium (Al), copper (Cu), silver-colored (Ag), golden (Au) or above-mentioned material
Material.First insulating layer, 114 material may be, for example, silicon nitride, silica, doping dielectric materials or the above-mentioned material such as silica glass
The combination of material or similar material.In some embodiments, the thickness of conductive layer 112 is about 3nm to about 20nm.
In operation 20, dielectric layer 120 is formed, is filled between two adjacent stepped constructions 110, such as Fig. 2A-Fig. 2 C
It is shown.In some embodiments, in stepped construction 110 code-pattern one layer of dielectric materials layer of deposition, and this dielectric material
The bed of material is filled in the space between two stepped constructions 110.Then, it carries out CMP step removal and is deposited on stacking knot
Dielectric materials layer on structure 110, and form the dielectric layer 120 being filled between two stepped constructions 110.Dielectric layer 120 can be with
Comprising any suitable dielectric material, for example, silicon nitride, silica, doping dielectric materials, the dielectric layer 120 such as silica glass also may be used
To be formed by the dielectric material of low-k, such as phosphosilicate glass (PSG), boron-phosphorosilicate glass (BPSG), fluorine silicon glass
Glass (FSG), carbofrax material or combinations of the above or similar material.
In subsequent Fig. 3 A to Fig. 9 C, the attached drawing of alphabetical " A ", such as Fig. 3 A, Fig. 4 A, Fig. 5 A etc. are included in accompanying drawing number
Figure is upper schematic diagram；The attached drawing of primary and secondary " B ", such as the figures such as Fig. 3 B, Fig. 4 B, Fig. 5 B are included in accompanying drawing number, are along line segment B-
The diagrammatic cross-section of B '；The attached drawing of primary and secondary " C ", such as the figures such as Fig. 3 C, Fig. 4 C, Fig. 5 C are included in accompanying drawing number, are along line segment C-
The diagrammatic cross-section of C '.
In operation 30, contact hole is formed.Fig. 3 A- Fig. 3 C are please referred to, in some embodiments, are had extremely by being formed
Lack the photoresist layer 104 of an opening 104a to define the pattern of contact hole.It note that the opening 104a ranges of photoresist layer 104
Cover the junction L of stepped construction 110 and dielectric layer 120, therefore the range for the 104a that is open covers each conductive layer in stepped construction 110
The range of a part of 114a of 112 a part of 112a and each first insulating layer 114, the 104a that is open are also covered by dielectric layer 120
A part of 122 (being indicated in Fig. 3 A).Then, it is etched the portion that processing procedure removes the dielectric layer 120 being located in opening 104a ranges
Divide the part 114a of 122, the part 112a of each conductive layer 112 and each first insulating layer 114, and form contact hole 130.At certain
In a little embodiments, the operation of formation contact hole 130 forms a narrow portion 113 included in each conductive layer 112 and (is indicated in figure
3A), the width W1 of each narrow portion 113 is the 40% to 60% of the original width W2 of each conductive layer 112.In one embodiment, shape
Into after contact hole 130, photoresist layer 104 is removed.Various embodiments according to the present invention, contact hole 130 expose each
The side wall part 112b (being indicated in Fig. 3 B and Fig. 3 C) of conductive layer 112.
In operation 40, remove the sidewall sections 112b of each conductive layer 112, with two the first adjacent insulating layers 114 it
Between formed gap 132, as shown in Fig. 4 A- Fig. 4 C.For example, it using Wet-type etching technology, is etched back respectively via contact hole 130
The sidewall sections 112b of conductive layer 112, and form gap 132.The residual fraction of conductive layer 112 is adjoined in gap 132.It note that
Since conductive layer 112 is only formed in stepped construction 110, conductive layer 112 is had no in dielectric layer 120, so gap 132 only can shape
Into in stepped construction 110, can't be formed in dielectric layer 120.In certain embodiments, the upper end out line of contact hole 130
For round or similar pattern, thus the gap 132 formed from contact hole 130 extend to ground, and formed semicircular or
The gap 132 of arc shape.In some embodiments, the height in gap 132 is determined by the thickness of conductive layer 112, therefore
The height in gap 132 is about 3nm to about 20nm.
After operation 40 is performed, optionally diode structure is formed in each gap.In certain embodiments
In, the operation for forming diode structure comprises the steps of.First, the first type semiconductor structure is formed in each gap 132
141, as shown in Fig. 4 A- Fig. 4 C.First type semiconductor structure 141 may include the semi-conducting material of such as N-type.In an embodiment
In, use such as chemical vapor deposition, technique for atomic layer deposition or one layer of first type of deposition of similar process technique whole face
Semiconductor material layer, this first type semiconductor material layer can be filled in gap 132, and be coated in other structures；Then into
The dry etch process of row anisotropic removes first type semiconductor material layer of the position other than gap 132, and is filled in
The first type semiconductor structure 141 in gap 132.
Then, Fig. 5 A- Fig. 5 C are please referred to, carry out wet etch process, the first type half of part is etched back via contact hole 130
Conductor structure 141, and form gap 134.Later, Second-Type semiconductor structure 142 is formed in gap 134.Second-Type is partly led
Body structure 142 may include the semi-conducting material of such as P+ type.In one embodiment, using such as chemical vapor deposition or atomic layer
One layer of Second-Type semiconductor material layer of deposition of deposition technique whole face, this Second-Type semiconductor material layer are filled in gap 134,
And it is coated in other structures, then carries out the dry etch process of anisotropic, to remove position the other than gap 134
Two type semiconductor material layers just obtain the Second-Type semiconductor structure 142 being filled in gap 134.Second-Type semiconductor structure
142 and first type semiconductor structure 141 form diode structure 140.Later, wet etch process is carried out, via contact hole 130
The Second-Type semiconductor structure 142 of part is etched back, and forms gap 136, as shown in Fig. 6 A- Fig. 6 C.
In operation 50, heating element 150 is formed in each gap 136, as shown in Fig. 6 A- Fig. 6 C.Heating element 150
Material may be, for example, titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti) or above-mentioned material combination or similar material.One
In embodiment, one layer of the deposition of such as physical vapour deposition (PVD), chemical vapor deposition and/or technique for atomic layer deposition whole face is used
Heating material layer, this heating material layer is filled in gap 136, and is coated in other structures；Then anisotropic is carried out
Dry etch process removes heating material layer of the position other than gap 136, just obtains the heating element being filled in gap 136
150.In certain embodiments, diode structure 140 is between conductive layer 112 and heating element 150.But in other realities
It applies in mode, the step of above-mentioned formation diode structure 140 is non-essential, so heating element 150 may be formed at script
In gap 132.In certain embodiments, the thickness of heating element 150 is about 3nm to about 20nm.
In operation 60, the part 152 that second insulating layer 160 covers each heating element 150 in contact hole 130 is formed,
As shown in Fig. 7 A- Fig. 7 C.In some embodiments, one layer of insulation material layer is conformally deposited to be coated on shown in Fig. 6 A- Fig. 6 C
Structure on, patterned photoresist layer or mask layer 106 are then formed on insulation material layer.Pattern photoresist layer or mask layer
106 have at least one opening 106a, and the range for the 106a that is open covers the junction L of stepped construction 110 and dielectric layer 120, in formation
The method system for stating patterning photoresist layer or mask layer 106 utilizes known photolithography in semiconductor and etching technique.Then, wet type is carried out
Etch process removes the insulation material layer in the range of opening 106a, and forms second insulating layer 160.Fig. 8 A are painted second insulating layer
The 160 upper end out line in contact hole 130, second insulating layer 160 cover a part for each heating element 150 in contact hole 130
152, but second insulating layer 160 does not cover another part 154 of each heating element 150.In some embodiments, it heats
Element 150 not is about 3nm to about 20nm by the width W3 of another part 154 that second insulating layer 160 covers.Forming second absolutely
After edge layer 160, photoresist layer 106 is removed.The material of second insulating layer 160 may be, for example, silicon nitride, silica, the silica glass adulterated
Dielectric materials are waited, second insulating layer 160 can also be formed by the dielectric material of low-k, such as phosphosilicate glass
(PSG), boron-phosphorosilicate glass (BPSG), fluorine silica glass (FSG), carbofrax material or combinations of the above or similar material.
In operation 70, phase change structure 170 is formed in contact hole 130, as shown in Fig. 8 A- Fig. 8 C.In certain implementations
In mode, conformal one layer of phase-change material layer of deposition in contact hole 130, and phase change structure is formed in contact hole 130
170.A part 172 for phase change structure 170 contacts second insulating layer 160, and another part 174 of phase change structure 170
Contact another part 154 that each heating element 150 is not covered by second insulating layer 160.In some embodiments, phase change knot
Structure 170 includes germanium-antimony-tellurium (GST) material, such as Ge2Sb2Te5, Ge1Sb2Te4, Ge1Sb4Te7 or combinations of the above or class
As material.Other phase-transition materials may be, for example, GeTe, Sb2Te3, GaSb, InSb, Al-Te, Te-Sn-Se, Ge-Sb-Te,
In-Sb-Te、Ge-Se-Ga、Bi-Se-Sb、Ga-Se-Te、Sn-Sb-Te、In-Sb-Ge、Te-Ge-Sb-S、Te-Ge-Sn-O、
Sb-Te-Bi-Se、Te-Ge-Sn-Au、Pd-Te-Ge-Sn、In-Se-Ti-Co、Ge-Sb-Te-Pd、Ag-In-Sb-Te、Ge-
Te-Sn-Pt, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd and Ge-Sb-Se-Te.
In operation 80, contact structures 180 are formed in contact hole 130, as shown in 8A-8C figures.In certain embodiment party
In formula, contact structures 180 include barrier layer 181 and conductive column 182.In certain embodiments, one layer of deposition conformal first
Barrier layer 181 is coated in contact hole 130, is then deposited one layer of conductive material layer comprising metal and is filled up in contact hole 130
Remaining space.In one embodiment, the phase-change material layer of above-mentioned deposition, barrier layer and conductive material layer can also be deposited on contact
In other structures other than hole 130, therefore after conductive material layer is deposited, carry out CMP step and be located to remove
Phase-change material layer, barrier layer and conductive material layer other than contact hole 130, so as to obtain the phase change that Fig. 8 A- Fig. 8 C are painted
Memory structure.The material of barrier layer 181 may be, for example, titanium nitride, and the material of conductive column 182 may be, for example, the metal comprising tungsten
Material.Barrier layer 181 is diffused into to avoid the tungsten atom in conductive column 182 in neighbouring structure.
In the structure being painted in Fig. 8 A- Fig. 8 C, each heating element 150 and the contact area meeting of phase change structure 170
Form a mnemon.Fig. 8 B are painted the enlarged drawing of single a mnemon, when phase-change memory is in use state,
Electric current is transmitted to heating element 150 from conductive layer 112 via diode structure 140, by heating element 150 to phase change structure
170 are heated, and phase change structure 170 is made to contact the undergoing phase transition of part of heating element 150, and reach the mesh of storage data
's.
Fig. 8 A are gone back to, since a part 152 for heating element 150 is covered by second insulating layer 160, so passing through conduction
The electric current of layer 112 only can not be transmitted to phase transformation from heating element 150 by another part 154 that second insulating layer 160 covers
Change structure 170.Therefore, the electric current transmitted in conductive layer 112 is pooled to the part 154 of heating element 150, allows heating element 150
Part 154 have high current density (current density be defined as the magnitude of current divided by electric current by sectional area), so as to have
Help that the part 174 of phase change structure 170 is allowed to generate high temperature, its crystalline phase is accelerated to change, therefore the speed of write-in data can be improved
Degree and reliability.As it was noted above, in some embodiments, heating element 150 is not covered another by second insulating layer 160
The width W3 of part 154 is about 3nm to about 20nm, and the thickness of heating element 150 be about 3nm to about 20nm, therefore formed
Heating surface (area) (HS can be less than 400nm2.
Referring to Fig. 3 A and Fig. 8 A, the contact with the junction L of dielectric layer 120 of stepped construction 110 is crossed over by formation
Hole 130 can go out the upper end out line of heating element 150 defined in subsequent step.Stepped construction 110 connects with dielectric layer 120
The lower edge position of the part 154 of heating element 150 is substantially defined at face.Add in addition, being defined using second insulating layer 160
The upper limb position of the part 154 of thermal element 150, therefore the narrow regions that the junior one surmounts the general lithographic techniques limit are defined, from
And the minimum effective heating part 154 of formation width in heating element 150, the part 154 of heating element 150 is allowed with high
Current density.
Performing, operation is after 80s, other structures is optionally formed in contact structures 180, such as form bit line
(bit line) 190, as shown in Fig. 9 A- Fig. 9 C.Bit line 190 via contact structures 180 be electrically connected phase change structure 170,
Heating element 150, diode structure 140 and conductive layer 112.
According to content disclosed above, another aspect of the present invention is to provide a kind of phase-change memory.Referring again to figure
8A and Fig. 8 B, phase-change memory 100 include stepped construction 110, second insulating layer 160, phase change structure 170 and contact knot
Structure 180.Stepped construction 110 includes multiple first conductor wires 116 and multiple first insulating layers 114, each first conductor wire 116
It is interposed between two adjacent the first insulating layers 114.Each first conductor wire 116 includes a notch portion 117.Contact structures
180 substantially upwardly extend perpendicular to the side of each first conductor wire 116, and the position of contact structures 180 corresponds to the
The notch portion 117 of one conductor wire 116.Second insulating layer 160 covers a part for the notch portion 117 of each first conductor wire 116
117a, but another part 117b of notch portion 117 is not covered by second insulating layer 160.Phase change structure 170 is tied around contact
Structure 180.Phase change structure 170 includes first part 172 and second part 174, and first part 172 is interposed in contact structures
Between 180 and second insulating layer 160, notch portion 117 that 174 material contact of second part is not covered by second insulating layer 160
Another part 117b.
In some embodiments, Fig. 8 B are please referred to, the first conductor wire 116 includes conductive layer 112, diode structure 140
And heating element 150.Diode structure 140 is between heating element 150 and conductive layer 112.Then, Fig. 8 A are please referred to,
A part 152 for heating element 150 contacts second insulating layer 160, but another part 154 of heating element 150 contacts phase transformation
Change the second part 174 of structure 170.In certain embodiments, the width W3 of another part 154 of heating element 150 is about 3nm
To about 20nm.In other some embodiments, for the first conductor wire 116 also comprising a straight line portion 118, straight line portion 118 connects recess
Portion 117, and about the 40% to about 60% of the width W5 that the minimum widith W4 of notch portion 117 is straight line portion 118.
Although the present invention is disclosed above with embodiment, however, it is not to limit the invention, any to be familiar with this skill
Person, without departing from the spirit and scope of the present invention, when can be used for a variety of modifications and variations, therefore protection scope of the present invention is worked as
Subject to the scope of which is defined in the appended claims.
Claims (9)
1. a kind of phase-change memory, which is characterized in that include：
One stepped construction, comprising multiple first conductor wires and multiple first insulating layers, respectively first conductor wire is interposed in adjacent
Two first insulating layers between, respectively first conductor wire include a notch portion and a heating element；
One contact structures are upwardly extended perpendicular to the side of respectively first conductor wire, and the contact structures correspond to respectively this first
The notch portion of conductor wire；
One second insulating layer covers a part for the respectively notch portion of first conductor wire, and respectively another part of the notch portion
It is not covered by the second insulating layer；And
One phase change structure, around the contact structures, the wherein phase change structure includes a first part and a second part,
The first part is interposed between the contact structures and the second insulating layer, which second is not insulated by this
The another part of the respectively notch portion of layer covering, a part for the wherein heating element contact the second insulating layer, and should add
Another part of thermal element contacts the second part of the phase change structure.
2. phase-change memory as described in claim 1, which is characterized in that respectively first conductor wire also includes a diode junction
Structure and a conductive layer, and the diode structure is located between the heating element and the conductive layer.
3. phase-change memory as described in claim 1, which is characterized in that the another part of the heating element is wide with one
It spends for 3nm to 20nm.
4. phase-change memory as described in claim 1, which is characterized in that respectively first conductor wire also includes a straight line portion,
The straight line portion connects the notch portion, and the 40% to 60% of the width that the minimum widith of the notch portion is the straight line portion.
A kind of 5. method for manufacturing phase-change memory, which is characterized in that include following operation：
Multiple stepped constructions are formed, respectively the stepped construction includes multiple conductive layers and multiple first insulating layers, respectively the conductive layer
It is interposed between first insulating layer of adjacent two；
A dielectric layer is formed, is filled between two adjacent stepped constructions；
A part, respectively a part for the conductive layer and an each part for first insulating layer for the dielectric layer is removed, to be formed
One contact holes exposing goes out the side wall part of the respectively conductive layer；
The sidewall sections of the respectively conductive layer are removed, a gap is formed between in office two adjacent first insulating layers；
A heating element is formed in the respectively gap；
It forms a second insulating layer and covers a respectively part for the heating element, and the second insulating layer does not cover respectively in the contact hole
Another part of the heating element；
A phase change structure is formed in the contact hole, a part for the phase change structure contacts the second insulating layer, and the phase
The another part for changing structure contacts the another part of the respectively heating element；And
A contact structures are formed in the contact hole.
6. the method for manufacture phase-change memory as claimed in claim 5, which is characterized in that in the operation for forming the gap
Afterwards, it but before the operation of the heating element is formed, also includes：
A diode structure is formed in the respectively gap, wherein the diode structure be located at the conductive layer and the heating element it
Between.
7. the method for manufacture phase-change memory as claimed in claim 6, which is characterized in that respectively should be formed in the respectively gap
The step of diode structure, includes：
One first type semiconductor structure and a Second-Type semiconductor structure are formed in the respectively gap.
8. the method for manufacture phase-change memory as claimed in claim 5, which is characterized in that form the operation packet of the contact hole
Contain：A narrow portion is formed in the respectively conductive layer, respectively the width of the narrow portion is the 40% to 60% of the respectively original width of the conductive layer.
9. the method for manufacture phase-change memory as claimed in claim 5, which is characterized in that forming the second insulating layer
In operation, respectively a width of the another part of the heating element is 3nm to 20nm.
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| CN102148261A (en) * | 2010-02-10 | 2011-08-10 | 中国科学院微电子研究所 | Capacitor structure and manufacturing method thereof |
| CN105304638A (en) * | 2015-11-16 | 2016-02-03 | 上海新储集成电路有限公司 | Three-dimensional phase change memory structure and manufacturing structure |
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| US8198672B2 (en) * | 2010-06-30 | 2012-06-12 | SanDisk Technologies, Inc. | Ultrahigh density vertical NAND memory device |
| KR20130139602A (en) * | 2012-06-13 | 2013-12-23 | 에스케이하이닉스 주식회사 | Semiconductor device, memory system comprising the same and method of manufacturing the same |
| US9099637B2 (en) * | 2013-03-28 | 2015-08-04 | Intellectual Discovery Co., Ltd. | Phase change memory and method of fabricating the phase change memory |
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| CN105304638A (en) * | 2015-11-16 | 2016-02-03 | 上海新储集成电路有限公司 | Three-dimensional phase change memory structure and manufacturing structure |
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