CN105098071B - The method for manufacturing phase-change memory - Google Patents
The method for manufacturing phase-change memory Download PDFInfo
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- CN105098071B CN105098071B CN201510402332.7A CN201510402332A CN105098071B CN 105098071 B CN105098071 B CN 105098071B CN 201510402332 A CN201510402332 A CN 201510402332A CN 105098071 B CN105098071 B CN 105098071B
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Abstract
A kind of method for manufacturing phase-change memory, comprising：(i) base material is formed, this base material includes a heating element heater；(ii) one first dielectric layer covering heating elements are formed；(iii) form one first opening and run through the first dielectric layer, to expose heating element heater, wherein the first opening has a bottom surface and one side；(iv) barrier layer is formed on the first dielectric layer, and serves as a contrast and wraps up in the first opening, and wherein barrier layer includes a bottom and a side wall is covered each by the bottom surface and side of the first opening；And (v) forms a phase change element and an electrode, wherein phase change element is located on the bottom of barrier layer, and electrode is located on phase change element, makes barrier layer and electrode-clad phase change element.
Description
Technical field
The invention relates to a kind of manufacture method of phase-change memory device.
Background technology
Computer or other electronic installations are commonly configured with various types of memory bodys, such as random access memory
(RAM), read-only memory (ROM), Dynamic Random Access Memory (DRAM), synchronous dynamic random-access memory body (SDRAM),
Phase change random access memory (PCRAM) or fast flash memory bank.Phase-change memory is non-volatile memory body, can be passed through
Measure the resistance value of memory cell and obtain and be stored in data therein.Add in general, phase-change memory unit includes
Thermal element and phase change cell, phase change cell can be because be heated and undergoing phase transition.When being passed through electric current to heating element heater,
Heating element heater converts electric energy into heat, and caused heat promotes phase change cell to occur the change of phase, such as from amorphous phase
(amorphous) it is transformed into more crystalline phases (polycrystalline).Phase change cell mutually has different resistance in different
Value, via the resistance value for detecting or reading phase change cell, just it is able to judge the data types of memory cell.At present, phase transformation
The manufacturing process for changing memory body still faces some problems, it is therefore necessary to proposes a kind of more preferable manufacture method.
The content of the invention
It is an aspect of the present invention to provide a kind of method for manufacturing phase-change memory, the one of which technology effect of the method
Fruit is that solve the alignment issues in exposure manufacture process.Another of the method has the technical effect that manufactured phase-change memory can
Effectively the material of phase change element is prevented to be diffused into neighbouring dielectric layer.
According to the various embodiments of the present invention, the method includes following operation：(i) heating element heater is formed in semiconductor
On base material；(ii) the first dielectric layer is formed above semiconductor substrate and heating element heater, wherein the first dielectric layer has first to open
Mouth exposes heating element heater；(iii) barrier layer is formed on the first dielectric layer, and is served as a contrast and wrapped up in the first opening；(iv) phase change material is formed
The bed of material fills the first opening on barrier layer；(v) phase-change material layer of a part and the barrier layer of a part are removed,
To expose the first dielectric layer, and the phase change element formed in the first opening；(vi) the second dielectric layer is formed in first to be situated between
In electric layer, wherein there is the second dielectric layer the second opening, which to expose phase change element (vii), forms electrode material layer in the second dielectric
On layer, and fill the second opening；And (viii) removes the part of the electrode material layer positioned at the second dielectric layer, and formed
It is embedded at the electrode structure of the second opening.
In some embodiments, above-mentioned semiconductor substrate includes at least one bottom electrode and at least one layer of dielectric layer position
In the top of bottom electrode, there is dielectric layer at least one through hole to expose bottom electrode, and heating element heater is formed in through-holes.
In some embodiments, the resistance value of heating element heater is more than the resistance value of bottom electrode, and the width of heating element heater
Less than the width of bottom electrode.
In some embodiments, the width of the first opening is the width of bottom electrode about 0.8 again to about 1.5 times.
In some embodiments, the width of the first opening is more than the width of heating element heater.
In some embodiments, barrier layer includes titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti) or combinations of the above
Or similar material, and electrode structure includes titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti) or combinations of the above or similar
Material.
In some embodiments, barrier layer, heating element heater and electrode structure include at least one identical material.
In some embodiments, the first opening has bottom surface and side, and barrier layer includes bottom and side wall is covered respectively
The bottom surface and side that lid first is open.
In some embodiments, remove the phase-change material layer of part and the operation of partial barrier layer includes：Make
The part of the barrier layer and phase-change material layer positioned at the first dielectric layer is removed with cmp.
In some embodiments, the first opening and the second opening have the first width and the second width, and second respectively
Width is 1.1 times to 1.6 times of the first width.
Brief description of the drawings
Fig. 1 illustrates the flow chart of the method for the manufacture phase-change memory according to the various embodiments of the present invention；
Fig. 2-Figure 10 illustrates diagrammatic cross-section of the various embodiments of the present invention in different process stages.
Embodiment
In order that the narration of the present invention is more detailed with complete, below for embodiments of the present invention and specific implementation
Example proposes illustrative description；But this not implements or the unique forms with the specific embodiment of the invention.It is disclosed below
Each embodiment, beneficial in the case of can be mutually combined or substitute, can also add other embodiments in one embodiment, and
Without further record or explanation.
In the following description, many specific details be will be described in detail so that reader can fully understand following embodiment.
However, embodiments of the invention can be put into practice in the case of without these specific details.In other cases, it is ripe to simplify accompanying drawing
The structure known only symbolically is illustrated in figure with device.
Space relative terms used herein, for example, " lower section ", " under ", " top ", " on " etc., this is in order to just
Relativeness between one element of narration or feature and another element or feature, as depicted in figure.These phases spatially
Other orientation are included to the true meaning of term.For example, when diagram spins upside down 180 degree, an element and another element it
Between relation, may from " lower section ", " under " become " top ", " on ".In addition, spatially relative used herein
Narration should also make same explanation.
Recently, some technical problems are faced when developing " phase-change memory " (phase change memory).Example
Such as, when deposited using in general-lithographic-etch process to form the phase change element of patterning when, micro-photographing process can face pair
The problem of quasi-.Specifically, after depositing one layer of phase-transition material on a semiconductor substrate, because the light of phase-transition material penetrates
Rate is smaller, and the phase-change material layer deposited can cover the alignment mark (alignment mark) on semiconductor substrate, cause
Follow-up micro-photographing process can not be aligned accurately.A kind of method of solution is that first the phase-change material layer of deposition is carried out
Once rough lithographic-etch process, to remove the part that alignment mark is covered in phase-change material layer, allow on semiconductor substrate
Alignment mark expose.Then, accurately aligned using the alignment mark exposed, and perform a lithographic-erosion again
Journey is scribed, and forms the phase change element with accurate pattern.Above-mentioned settling mode, do not merely have to using extra once thick
Slightly shadow-etch process, and this step has to rely on the personal experience of operational staff and judges to complete.
An aspect of of the present present invention relates to a kind of method for manufacturing phase-change memory.The manufacture method tool herein proposed
Standby multiple technologies effect, one of which technique effect is that can avoid above-mentioned alignment issues completely.
Fig. 1 illustrates the flow chart of the method 10 of the manufacture phase-change memory according to the various embodiments of the present invention.Method
10 include operation 12, operation 14, operation 16, operation 18, operation 20, operation 22, operation 24 and operation 26.Fig. 2-Fig. 9 is illustrated
The diagrammatic cross-section of the different process stages into operation 26 of operation 12.Although a series of operation used herein illustrates herein
The method of exposure, but the order shown in these operations is not construed as the limitation of the present invention.Specifically, some operations
It can carry out in a different order or with other steps while carrying out.In addition, and the not all operation illustrated is all necessary
Embodiments of the present invention can be realized.In addition, each operation described herein can include multiple steps or action, to realize
The operation described.
In operation 12, heating element heater 120 is formed on semiconductor substrate 100, as shown in Figure 2.In some embodiments
In, semiconductor substrate 100 includes active member 102, interlayer dielectric layer (ILD) 104, the electricity of vertical interconnecting structure 106 and first
Pole 108 (for example, bottom electrode of each memory cell).In some embodiments, semiconductor substrate 100 includes doping or not mixed
Miscellaneous Silicon Wafer or semiconductor upper insulator (SOI) base material.Active member 102 may be, for example, N-type metal-oxide semiconductor (MOS)
(NMOS) element, P-type mos (PMOS) element or CMOS (CMOS) element or
Similar element.In some embodiments, active member 102 includes grid 110 and source/drain region 112.Interlayer dielectric layer
(ILD) it can be any suitable dielectric material, such as silicon nitride, silica, the dielectric material such as silica glass of doping, interlayer are situated between
Electric layer (ILD) can also be formed by the dielectric material of low-k, such as phosphosilicate glass (PSG), boron-phosphorosilicate glass
(BPSG), fluorine silica glass (FSG), carbofrax material or combinations of the above or similar material.In some embodiments, partly lead
Body base material 100 also includes metal silicide layer 114, and on source/drain region 112, vertical interconnecting structure 106 is via silication gold
Category layer 114 is electrically connected to source/drain region 112.In one embodiment, vertical interconnecting structure 106 may be, for example, comprising tungsten
(W) metal via structure of material.In another embodiment, semiconductor substrate 100 also includes dielectric layer 116, dielectric layer 116
Being formed in interlayer dielectric layer 104 and the top of first electrode 108, dielectric layer 116 there is through hole 116a to be located at first electrode 108
Top.
In some embodiments, heating element heater 120 is formed in the through hole 116a of dielectric layer 116, and entity connects
First electrode 108.Heating element heater 120 has higher resistance value, when electric current is by heating element heater 120, the meeting of heating element heater 120
The electric energy of a part is transformed into heat energy, therefore produces heat.The material of heating element heater 120 may be, for example, titanium nitride (TiN), nitrogen
Change combination or the similar material of tantalum (TaN), titanium (Ti) or above-mentioned material.In certain embodiments, the resistance of heating element heater 120
Resistance value of the value higher than first electrode 108.In certain embodiments, heating element heater 120 may be, for example, column structure, and heat
The width W1 of element 120 is less than the width W2 of first electrode 108.
In operation 14, the first dielectric layer 130 is formed above semiconductor substrate 100 and heating element heater 120, such as Fig. 3 institutes
Show.There is first dielectric layer 130 first opening 132 to expose heating element heater 120.In some embodiments, the first opening 132
With bottom surface 134 and side 136, heating element heater 120 exposes via the bottom surface 134 of the first opening 132.In an embodiment
In, the width W3 of the first opening 132 is more than the width W1 (being indicated in Fig. 2) of heating element heater 120, and the face of the first opening 132
Product covers the top of heating element heater 120.In another embodiment, the width W3 of the first opening 132 is more than first electrode 108
Width W2 (is indicated in Fig. 2).In another embodiment, pact that the width W3 of the first opening 132 is the width W2 of first electrode 108
0.8 times to about 1.5 times, for example, about 0.9 times, about 1.0 times, about 1.1 times or about 1.3 times.Form the mode of the first opening 132 simultaneously
Without specifically limited.For example, one layer of eurymeric photoresistance can be coated with the first dielectric layer 130, then carry out micro-photographing process and
The photoresist layer of patterning is formed, then processing procedure is etched again and forms the first opening 132.Or can be in the first dielectric layer
Double-deck hard mask (double-layer hard mask) is formed on 130, then recycles this double-deck hard mask to carry out follow-up
Etch process and form the first opening 132.Any appropriate technology may serve to form the first opening 132.In operation 16,
Because also without any phase-transition material is deposited on semiconductor substrate 100, exposure sources are observed that semiconductor-based
Alignment mark on material, and accurately aligned and form the first opening 132.In one embodiment, the first dielectric layer 130 wraps
Silicon nitride comprising, silica, the silica glass of doping or similar dielectric material.In another embodiment, the first dielectric layer 130 includes
Phosphosilicate glass (PSG), boron-phosphorosilicate glass (BPSG), fluorine silica glass (FSG), polymer, the group of carborundum or above-mentioned material
Close or the like.First dielectric layer 130 can be for example, by rotary coating mode, chemical vapor deposition (CVD) and/or plasma
Any appropriate method such as Assisted Chemical Vapor (PECVD) is formed.
In operation 16, barrier layer 140 is formed on the first dielectric layer 130, and serves as a contrast and wraps up in the first opening 132, such as Fig. 4 institutes
Show.Barrier layer 140 includes bottom 142 and side wall 144, is covered each by the bottom surface 134 and side 136 of the first opening 132.Barrier layer
140 to avoid the phase-transition material that successive process is formed from diffusing into the first dielectric layer 130, and causes phase change to be remembered
Deterioration in performance occurs for body device, will hereafter describe in more detail.
In some embodiments, barrier layer 140 is to use the deposition technique of code-pattern and formed, such as physical vapor is sunk
Product processing procedure (PVD), chemical vapor deposition process (CVD), plasma enhanced chemical vapor (PECVD), ald processing procedure
And/or atomic layer chemical vapor deposition processing procedure (ALCVD) etc. (ALD).In one embodiment, barrier layer 140 includes titanium nitride
(TiN), tantalum nitride (TaN), the combination of titanium (Ti) or above-mentioned material or similar material.Barrier layer 140 can be single layer structure
Or sandwich construction.In one embodiment, barrier layer 140 is made up of the titanium nitride of simple layer.In another embodiment, barrier
Layer 140 includes one layer of titanium nitride and one layer of tantalum nitride.Have in another embodiment, barrier layer 140 includes one layer of titanium nitride and one
The other kinds of material (for example, carborundum) of layer.In other embodiments, barrier layer 140 includes at least one with heating element heater 120
Kind identical material.In operation 16, because forming barrier layer 140 using the deposition technique of code-pattern, operate herein
In need not use semiconductor substrate on alignment mark.
According to multiple embodiments of the present invention, the material contact heating element heater 120 of bottom 142 of barrier layer 140.Therefore,
In final obtained phase-change memory, heat can be rapidly transferred to barrier layer 140 caused by heating element heater 120.
In operation 18, phase-change material layer 150 is formed on barrier layer 140, and is filled in the first opening 132, such as
Shown in Fig. 5.In some embodiments, using such as physical vapour deposition (PVD) processing procedure (PVD), chemical vapor deposition process (CVD),
Plasma enhanced chemical vapor (PECVD), ald processing procedure (ALD) and/or atomic layer chemical vapor deposition processing procedure
Etc. (ALCVD) deposition technique of code-pattern forms phase-change material layer 150.In this operation, phase-change material layer 150 is logical
Cross the deposition technique of code-pattern and formed, need not use the alignment mark on semiconductor substrate.In some embodiments,
Phase-change material layer 150 includes germanium-antimony-tellurium (GST) material, such as Ge2Sb2Te5、Ge1Sb2Te4、Ge1Sb4Te7Or above-mentioned group
Conjunction or similar material.Other phase-transition materials may be, for example, GeTe, Sb2Te3、GaSb、InSb、Al-Te、Te-Sn-Se、Ge-
Sb-Te、In-Sb-Te、Ge-Se-Ga、Bi-Se-Sb、Ga-Se-Te、Sn-Sb-Te、In-Sb-Ge、Te-Ge-Sb-S、Te-Ge-
Sn-O、Sb-Te-Bi-Se、Te-Ge-Sn-Au、Pd-Te-Ge-Sn、In-Se-Ti-Co、Ge-Sb-Te-Pd、Ag-In-Sb-Te、
Ge-Te-Sn-Pt, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd and Ge-Sb-Se-Te.
In operation 20, the phase-change material layer 150 of a part and the barrier layer 140 of a part are removed, and is exposed
First dielectric layer 130, as shown in Figure 6.In one embodiment, operation 20 is included using cmp to remove positioned at the
The barrier layer 140 of the top of one dielectric layer 130 and the part of phase-change material layer 150, and formed and be embedded in the first opening 132
Phase change element 152.It is the phase-change material layer 150 that a part is removed using comprehensive eatch-back mode in this operation
With barrier layer 140, so this operation need not use semiconductor substrate on alignment mark.It note that after this operation is completed,
Most phase-change material layer 150 is removed, only formed with phase change element 152 in the first opening 132, therefore semiconductor
Alignment mark on base material is no longer covered by phase-change material layer 150.
In operation 22, the second dielectric layer 190 is formed on the first dielectric layer 130, as shown in Figure 7.Second dielectric layer 190
Phase change element 152 is exposed with the second opening 192.In this step, due to must accurately form the second opening 192,
It you must use the alignment mark on semiconductor substrate.But in previous operation in (operation 20), most phase transformation
Change material layer 150 is removed, the first dielectric layer 130 and the material that the second dielectric layer 190 is light-permeable, such as silica
(SiO2), so optical device can observe and capture the alignment mark on semiconductor substrate and accurately be aligned.
In some embodiments, the first opening 132 and the second opening 192 have the first width W3 and the second width respectively
W4, and the second width W4 is the first width W3 about 1.1 again to about 1.6 times.For example, the second width W4 is the first width W3's
About 1.2 times, about 1.3 times, about 1.4 times or about 1.5 times.The material of second dielectric layer 190 may be, for example, silicon nitride, silica, mix
Miscellaneous silica glass, phosphosilicate glass (PSG), boron-phosphorosilicate glass (BPSG), fluorine silica glass (FSG), polymer, carborundum or on
State the combination of material or similar material.In one embodiment, the material of the second dielectric layer 190 and the first dielectric layer 130
Material is identical.In another embodiment, the material of the second dielectric layer 190 is different from the material of the first dielectric layer 130.Second is situated between
Electric layer 190 can be for example, by rotary coating mode, chemical vapor deposition (CVD) and/or plasma enhanced chemical vapor
Etc. (PECVD) any appropriate method is formed.
In operation 24, electrode material layer 160 is formed on the second dielectric layer 190, and is filled in the second opening 192,
As shown in Figure 8.For example, physical vapour deposition (PVD) processing procedure (PVD), chemical vapor deposition process (CVD), plasma can be used
The blankets such as Assisted Chemical Vapor (PECVD), ald processing procedure (ALD) and/or atomic layer chemical vapor deposition processing procedure (ALCVD)
The deposition technique of formula is covered to form electrode material layer 160.In some embodiments, electrode material layer 160 includes titanium nitride
(TiN), tantalum nitride (TaN), the combination of titanium (Ti) or above-mentioned material or similar material.In one embodiment, electrode material layer
160 with barrier layer 140 be identical material made by.In another embodiment, barrier layer 140, heating element heater 120 and electrode
Structure 160 includes at least one identical material.In operation 24, electrode material layer 160 is the deposition technique by code-pattern
And formed, so this operation need not use the alignment mark on semiconductor substrate.
In operation 26, the part of the electrode material layer 160 positioned at the top of the second dielectric layer 190 is removed, and obtains Fig. 9 institutes
The structure shown.In some embodiments, operation 26 includes is deposited on the second dielectric layer 190 using cmp to remove
The electrode material layer 160 of top, and the second electrode 162 being embedded in the second opening 192 is formed (for example, each memory body list
The Top electrode of member).It is the electrode material layer 160 that a part is removed using the eatch-back mode of holohedral form in this operation, this behaviour
Make also use the alignment mark on semiconductor substrate.
It was found from various embodiments described above, in operation 12 into operation 26, only operation 14 and operation 22 is necessary
Use the alignment mark on semiconductor substrate.Via cleverly processing procedure arrangement, the register guide on the semiconductor substrate of operation 22
Note will not be covered by phase-change material layer, therefore efficiently solve previously described alignment issues.Technology effect described herein
Fruit is only one of them in many technological merits of the present invention, should not limit the scope of the present invention with this technique effect.
In addition, phase change element 152 is intactly enveloped by barrier layer 140 and second electrode 162, so in successive process
In can effectively prevent the material of phase change element 152 from being penetrated into because of diffusion phenomena in neighbouring dielectric layer.In addition, barrier layer
140 can preserve heat caused by heating element heater, contribute to phase change element that the change of crystalline phase occurs.Above-mentioned technique effect
Only it is one of them in many technological merits of the present invention, the present invention is not only restricted to above-mentioned technique effect.
After operation 26, method 10 can include other operations or step.For example, complete operation 26 it
Afterwards, insulating barrier 196 can be formed and cover the dielectric layer 190 of second electrode 162 and second, as shown in Figure 10.Insulating barrier 196 can example
Such as it is silicon nitride, silica or similar material.Afterwards, other various logic circuits or function can be formed on insulating barrier 196
Circuit.
Although the present invention is disclosed above with embodiment, so it is not limited to the present invention, any to be familiar with this skill
Person, without departing from the spirit and scope of the present invention, when can be used for a variety of modifications and variations, therefore protection scope of the present invention is worked as
It is defined depending on the scope of which is defined in the appended claims.
Claims (10)
- A kind of 1. method for manufacturing phase-change memory, it is characterised in that include：A heating element heater is formed on semiconductor base material；One first dielectric layer is formed above the semiconductor substrate and the heating element heater, wherein first dielectric layer has one first Opening exposes the heating element heater；A conductive barrier layer is formed on first dielectric layer, and serves as a contrast and wraps up in first opening, the Top of the Qie Fu Cover heating element heaters Surface；A phase-change material layer is formed on the conductive barrier layer, and fills first opening；The phase-change material layer of a part and the conductive barrier layer of a part are removed, to expose first dielectric layer, And the phase change element formed in first opening；One second dielectric layer is formed on first dielectric layer, wherein there is second dielectric layer one second opening to expose the phase transformation Change element；An electrode material layer is formed on second dielectric layer, and fills second opening；AndThe part of the electrode material layer positioned at second dielectric layer is removed, and forms the electrode for being embedded at the second opening Structure.
- 2. the method for manufacture phase-change memory according to claim 1, it is characterised in that the semiconductor substrate includes one Bottom electrode and a dielectric layer are located on the bottom electrode, and there is the dielectric layer through hole to expose the bottom electrode, and the heating unit Part is formed in the through hole.
- 3. the method for manufacture phase-change memory according to claim 2 a, it is characterised in that resistance of the heating element heater Value is more than a resistance value of the bottom electrode, and a width of the heating element heater is less than a width of the bottom electrode.
- 4. the method for manufacture phase-change memory according to claim 2 a, it is characterised in that width of first opening For 0.8 times to 1.5 times of a width of the bottom electrode.
- 5. the method for manufacture phase-change memory according to claim 1 a, it is characterised in that width of first opening More than a width of the heating element heater.
- 6. the method for manufacture phase-change memory according to claim 1, it is characterised in that the barrier layer includes at least one Material is the group formed selected from titanium nitride, tantalum nitride, titanium and combinations of the above, and the electrode structure includes an at least material Material is the group formed selected from titanium nitride, tantalum nitride, titanium and combinations of the above.
- 7. the method for manufacture phase-change memory according to claim 1, it is characterised in that the barrier layer, the heating unit Part and the electrode structure include at least one identical material.
- 8. the method for manufacture phase-change memory according to claim 1, it is characterised in that first opening has a bottom Face and one side, and the barrier layer includes a bottom and a side wall is covered each by the bottom surface and the side of first opening.
- 9. the method for manufacture phase-change memory according to claim 1, it is characterised in that remove the phase transformation of the part The operation for changing material layer and the barrier layer of the part includes：Removed using cmp on first dielectric layer The barrier layer of side and the part of phase-change material layer.
- 10. the method for manufacture phase-change memory according to claim 1, it is characterised in that first opening and this Two openings have one first width and one second width respectively, and second width is 1.1 times to 1.6 times of first width.
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| CN108550696B (en) * | 2016-03-08 | 2022-02-25 | 江苏时代全芯存储科技股份有限公司 | Phase change memory |
| CN112614866A (en) * | 2020-12-17 | 2021-04-06 | 长江先进存储产业创新中心有限责任公司 | Manufacturing method of phase change memory |
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