CN101150172A - Phase change memory and its making method - Google Patents
Phase change memory and its making method Download PDFInfo
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- CN101150172A CN101150172A CN 200610154300 CN200610154300A CN101150172A CN 101150172 A CN101150172 A CN 101150172A CN 200610154300 CN200610154300 CN 200610154300 CN 200610154300 A CN200610154300 A CN 200610154300A CN 101150172 A CN101150172 A CN 101150172A
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- 238000004519 manufacturing process Methods 0.000 claims abstract description 38
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- 238000005530 etching Methods 0.000 claims description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 13
- 229910052718 tin Inorganic materials 0.000 claims description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
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- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 claims description 6
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- 239000002904 solvent Substances 0.000 claims description 4
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Abstract
This invention relates to a phase-change storage and its manufacturing method, in which, the storage includes; a base, a first dielectric layer with a first aperture formed on the base, a frist elctrode formed in the first aperture and filled in it, a cylindrical second dielectric layer formed on the first electrode directly, a first conduction layer formed on the side wall of the second dielectric layer and connected to the first electrode, a third dielectric layer covering the first electrode and side walls of the first conduction layer and exposing the top surface of the first conduction layer, a phase-change layer formed on the third dielectric layer and contacted with the surface of the first conduction layer, a fourth dielectric layer formed on the third dielectric layer and the phase-change layer and exposing the top surface of the phase-change layer by a second aperture on it, a second conduction layer formed in the second aperture and filled in it and connected with the phase-change layer and the second electrode is connected with the second conduction layer.
Description
Technical field
The present invention relates to a kind of Ovonics unified memory and manufacture method thereof, particularly relate to a kind of phase change layer and long-pending Ovonics unified memory and manufacture method thereof of electrode contact surface of dwindling.
Background technology
Ovonics unified memory has high reading speed, low-power, high power capacity, high-reliability, height and writes characteristics such as wiping number of times, low-work voltage/electric current and low cost, and be fit to very much combine with CMOS technology, can be used as the stand alone type or the Embedded memory application of higher density, is the new memory of future generation that very is expected at present.Because the unique advantage of Ovonics unified memory technology, also make it be considered to might replace very much the highly competititve SRAM of present commercialization and DRAM volatile storage and Flash non-volatility memorizer technology, be expected to become following potential generation semiconductor memory.Take a broad view of the development trend of present Ovonics unified memory, can find significantly that main bottleneck is that the operating current of element is excessive, thereby the driving transistors area that can't reduce phase change memory device effectively and be connected in series, cause the oversize problem that makes that memory density can't improve of identical element.
Reduce that the Ovonics unified memory operating current can the contact area of phase change layer and electrode realizes in the phase change memory cell by dwindling, and help dwindling and the raising of memory density of cmos element.Yet the method can be subject to the restriction of photoetching and working ability, is difficult for obtaining effectively to break through.
For addressing the above problem, people such as Heon Lee propose a kind of manufacture method that forms Ovonics unified memory in U.S. Pat 6746892, please refer to Fig. 1, and this method may further comprise the steps.At first, form dielectric layer on substrate 11, then, hocket etch process and photoresist side direction downsizing technology come this dielectric layer of etching to form the dielectric projection 13 of pyramidal structure.Then, compliance depositing electrode layer 15 is on the dielectric projection 13 of this pyramidal structure.Then, form insulating barrier 17 on said structure, and further eat-back this insulating barrier 17 so that the electrode layer 15 of cone tip shape exposes this insulating barrier 17.Then, form phase change layer 19, reach the purpose of dwindling phase change layer 19 and electrode layer 15 (bottom electrode) contact area so that the awl point of this electrode layer 15 contacts with this phase change layer.At last, form top electrode 23 and interlayer insulating film 21 again.Utilize above-mentioned technology, though can reach the purpose of the contact area of dwindling phase change layer and electrode, yet, this prior art also need use etch process and photoresist side direction downsizing technology to form the dielectric layer of taper repeatedly, therefore processing step is very complicated, and the electrode net shape is wayward, can't guarantee that the taper dielectric layer of gained has the shape of homogeneous, and this stability for element is a big problem.
Given this, with easily with prerequisite that semiconductor fabrication process combines under, design the manufacturing process of brand-new phase change memory device, dwindle the contact area of phase change layer and electrode layer in the Ovonics unified memory, to dwindle electric current, to increase memory density, the real emphasis that need study for the Ovonics unified memory manufacturing process technology utmost point.
Summary of the invention
The invention provides a kind of Ovonics unified memory, mainly utilize etching to cooperate little cutting (trim) technology to reach and dwindle phase change layer and the long-pending purpose of electrode contact surface.Ovonics unified memory of the present invention comprises: substrate; First dielectric layer with first opening is formed on this substrate; First electrode is formed in this first opening and fills up this first opening; Column second dielectric layer is formed directly on this first electrode; First conductive layer is formed on the sidewall of this column second dielectric layer, and is electrically connected with this first electrode; The 3rd dielectric layer covers this first electrode fully and coats the sidewall of this first conductive layer, and exposes the upper surface of this first conductive layer; Phase change layer is formed on the 3rd dielectric layer and with the upper surface of this first conductive layer and directly contacts; The 4th dielectric layer is formed on the 3rd dielectric layer and this phase change layer, and wherein the 4th dielectric layer has the upper surface that second opening exposes this phase change layer; Second conductive layer is formed in this second opening and fills up this second opening, and is electrically connected with this phase change layer; And second electrode be electrically connected with this second conductive layer.It should be noted that, because the contact area of first conductive layer and phase change layer depends on the thickness of this first conductive layer, and present semiconductor process techniques can be controlled the thickness of this first conductive layer easily to 10nm (even lower), therefore can define very little phase change layer contact area.
Another object of the present invention is to provide a kind of manufacture method of Ovonics unified memory, comprising: at first, formation has first dielectric layer of first opening on substrate.Then, form first electrode in this first opening and fill up this first opening.Then, form second dielectric layer and photoresist layer successively on this substrate.Then, this photoresist layer is carried out little manufacturing process (trimming process) of cutting, to form the top that photoresist post (photoresist pillar) is positioned at this first electrode.Then, utilize this photoresist post, be positioned on this first electrode to form column second dielectric layer as this second dielectric layer of mask etching.Then, compliance forms first conductive layer in this substrate, and wherein this first conductive layer coats the sidewall and the upper surface of this column second dielectric layer fully.This first conductive layer of anisotropic etching is up to the upper surface that exposes this column second dielectric layer.Form the 3rd dielectric layer in this substrate, and etch-back the 3rd dielectric layer is to expose the upper surface of this first conductive layer; Then, forming phase change layer directly contacts on the 3rd dielectric layer and with the upper surface of this first conductive layer; Then, form the 4th dielectric layer on the 3rd dielectric layer and this phase change layer, wherein the 4th dielectric layer has the upper surface that second opening exposes this phase change layer; Then, form second conductive layer in this second opening and fill up this second opening, wherein this second conductive layer is electrically connected with this phase change layer.At last, forming second electrode is electrically connected with this second conductive layer.
In addition, according to another preferred embodiment of the present invention, the manufacture method of this Ovonics unified memory also can may further comprise the steps: at first formation has first dielectric layer of first opening on substrate.Then, form first dielectric layer with first opening.Then, form first electrode in this first opening and fill up this first opening.Then, form first conductive layer, second dielectric layer and photoresist layer successively on this substrate.Then, this photoresist is carried out little technology (trimming process) of cutting, to form the top that photoresist post (photoresist pillar) is positioned at this first electrode.Utilize this photoresist post as this second dielectric layer of mask etching, be positioned on this first electrode to form column second dielectric layer.Utilize this column second dielectric layer as this first conductive layer of mask etching, form conductive pole.Form the 3rd dielectric layer in this substrate, and etch-back the 3rd dielectric layer is until the upper surface that exposes this conductive pole.Forming phase change layer directly contacts on the 3rd dielectric layer and with the upper surface of this conductive pole.Form the 4th dielectric layer on the 3rd dielectric layer and this phase change layer, wherein the 4th dielectric layer has the upper surface that second opening exposes this phase change layer.Form second conductive layer in this second opening and fill up this second opening, wherein this second conductive layer is electrically connected with this phase change layer.At last, forming second electrode is electrically connected with this second conductive layer.Etching/little cut technology in semiconductor technology, be used for forming general photoetching process the trickleer figure that can't define, one of feature of the present invention is that etching/little is cut in the manufacturing process technology that technology quotes Ovonics unified memory.At first, when definition photoresist figure, utilize etching/little technology (trim/etch) of cutting to obtain less semiconductor technology yardstick (feature size), to reach the purpose of contact area downsizing.
Below by a plurality of embodiment and comparing embodiment, illustrating further method of the present invention, feature and advantage, but be not to be used for limiting the scope of the invention, scope of the present invention should be as the criterion with claims.
Description of drawings
Fig. 1 is the sectional structure chart that shows existing Ovonics unified memory.
Fig. 2 a to 2m is the making flow process profile that shows the described Ovonics unified memory of the embodiment of the invention.
Fig. 3 is the top view of Fig. 2 f figure.
Fig. 4 a to Fig. 4 j is the making flow process profile that shows the described Ovonics unified memory of another embodiment of the present invention.
The simple symbol explanation
11～substrate;
The dielectric projection of 13～pyramidal structure;
15～electrode layer;
17～insulating barrier;
19～phase change layer;
23～top electrode;
21～interlayer insulating film;
100～Ovonics unified memory;
102～substrate;
104～the first dielectric layers;
106～the first openings;
108～the first electrodes;
110～the second dielectric layers;
112～bottom anti-reflection layer;
114～photoresist layer;
116～photoresist post figure;
118～column, second dielectric layer;
The upper surface of 119～column, second dielectric layer;
120～the first conductive layers;
122～the 3rd dielectric layers;
124～first residual the conductive layer;
126～the 3rd residual dielectric layer;
The upper surface of 125～residual first conductive layer;
128～the 4th dielectric layers;
130～phase change layer;
132～the 5th dielectric layers;
136～the second conductive layers;
134～the second openings;
138～the second electrodes;
200～Ovonics unified memory;
202～substrate;
204～the first dielectric layers;
206～the first openings;
208～the first electrodes;
210～the first conductive layers;
212～the second dielectric layers;
214～bottom anti-reflection layer;
216～photoresist layer;
218～photoresist post figure;
220～column, second dielectric layer;
222～conductive pole;
224～the 3rd dielectric layers;
226～phase change layer;
228～the 4th dielectric layers;
230～the second openings;
232～the second conductive layers;
234～the second electrodes.
Embodiment
Below, in conjunction with the accompanying drawings, describe the manufacture method of the described Ovonics unified memory 100 of the preferred embodiment of the present invention in detail.
At first, please refer to Fig. 2 a, first dielectric layer 104 that formation has first opening 106 then, is filled metal level in this first opening 106, as first electrode 108 on substrate 102.Wherein, this substrate 102 can be the employed substrate of semiconductor fabrication process, for example is silicon substrate.This substrate 102 can be the substrate of finishing CMOS leading portion manufacturing process, also may comprise isolation structure, electric capacity, diode and its analog, for the purpose of simplified, only represents with smooth substrate among the figure.This first dielectric layer 104 can be siliceous compound, for example: silicon nitride or silica.The material of this first electrode can for example be Al, W, Mo, TiN or TiW.
Then, please refer to Fig. 2 b, form second dielectric layer 110, bottom anti-reflection layer 112 and photoresist layer 114 successively.In the present embodiment, the material of this second dielectric layer 110 can be siliceous compound, for example silicon nitride or silica.
Then, please refer to Fig. 2 c, this photoresist layer 114 is carried out the photoengraving carving technology, and continue and carry out little cutting (trim) technology, to form the photoresist post figure 116 that diameter of section is not more than 100nm.It should be noted that this photoresist post figure 116 be positioned at this first electrode 108 directly over.The present invention is for employed little technology and indefinite of cutting, and can for example cut technology for solvent is little or dry type is little (for example: the little technology of cutting of plasma) cuts technology.
Then, please refer to Fig. 2 d, utilize etch process to remove this photoresist post figure 116 and bottom anti-reflection layer 112 fully, with with the photoresist figure transfer to this second dielectric layer 110, form column second dielectric layer 118 that diameter of section is not more than 100nm, wherein this column second dielectric layer 118 is positioned on this first electrode 108 and with this first electrode 108 and contacts.One of technical characterictic of the present invention is to utilize photoetching etching and little cutting (trim) technology to obtain less photoresist dimension of picture, utilizes this photoresist figure as mask, on figure transfer to the second dielectric layer 110 again.
Then, please refer to Fig. 2 e, compliance forms first conductive layer 120 and the 3rd dielectric layer 122 in this substrate 102, and covers this column second dielectric layer 118 fully.Then, please refer to Fig. 2 f, this first conductive layer 120 and the 3rd dielectric layer 122 are carried out anisotropic etching, until the upper surface 119 that exposes this column second dielectric layer 118.Please refer to Fig. 3, it is the top view of Fig. 2 f figure, and first conductive layer 124 that this moment is residual and the 3rd residual dielectric layer 126 are round the sidewall of this column second dielectric layer 118, and the upper surface 125 of this first residual conductive layer 124 exposes out.Wherein, the material of this first conductive layer can be W, TiN, TiAlN, Ta, TaN, poly-Si, TiSiN or TaSiN for example, and the material of the 3rd dielectric layer can for example be siliceous compound.It should be noted that, because the contact area of first conductive layer and phase change layer depends on the thickness of this first conductive layer, and the thickness that present semiconductor process techniques can be controlled this first conductive layer easily less than 50nm, preferably less than 20nm, further less than 10nm, therefore can define very little phase change layer contact area.
Then, please refer to Fig. 2 g, form the 4th dielectric layer 128 in this substrate 102, cover this column second dielectric layer 118, this first residual conductive layer 124 and the 3rd residual dielectric layer 126 fully.Then, please refer to Fig. 2 h, planarization the 4th dielectric layer 128 is until the upper surface that exposes this first conductive layer.Wherein, the step of this planarization can for example be a chemical mechanical milling tech.The 4th dielectric layer 128 can be siliceous compound, for example: silicon nitride or silica.
Then, please refer to Fig. 2 i, form phase change layer 130 on the 4th dielectric layer 128, and directly contact, form electrical connection with the upper surface of this first residual conductive layer 124.Then, please refer to Fig. 2 j, graphically this phase change layer 130 forms graphical phase change layer 130.This phase change layer can be the material that comprises Ge, Sb, Te or its mixing, is preferably GeSbTe or InGeSbTe.
Then, please refer to Fig. 2 k, form the 5th dielectric layer 132 on the 4th dielectric layer 128 and this phase change layer 130, wherein the 5th dielectric layer 132 has the upper surface that second opening 134 exposes this phase change layer 130.The 5th dielectric layer 132 can be siliceous compound, for example: silicon nitride or silica.
Please refer to Fig. 2 l, form second conductive layer 136 in this second opening 134 and fill up this second opening 134, wherein this second conductive layer 136 is electrically connected with this phase change layer 130.At last, please refer to Fig. 2 m, form second electrode 138 and be electrically connected with this second conductive layer 136.The material of this second electrode 138 is Al, W, Mo, TiN or TiW, and the material of this second conductive layer 136 is W, TiN, TiAlN, Ta, TaN, poly-Si, TiSiN or TaSiN.
Please refer to Fig. 4 a to 4j, it is for showing the described etching/little manufacture method of cutting the Ovonics unified memory 200 of technology (trim/etch) of quoting of another preferred embodiment of the present invention:
At first, please refer to Fig. 4 a, first dielectric layer 204 that formation has first opening 206 then, is filled metal level in this first opening 206, as first electrode 208 on substrate 202.Wherein, this substrate 202 can be the employed substrate of semiconductor fabrication process, for example is silicon substrate.This substrate 202 can be the substrate of finishing CMOS leading portion manufacturing process, also may comprise isolation structure, electric capacity, diode and its analog, for the purpose of simplified, only represents with smooth substrate among the figure.This first dielectric layer 204 can be siliceous compound, for example: silicon nitride or silica.The material of this first electrode can for example be Al, W, Mo, TiN or TiW.
Then, please refer to Fig. 4 b, form first conductive layer 210, second dielectric layer 212, bottom anti-reflection layer 214 and photoresist layer 216 successively.In the present embodiment, the material of this first conductive layer 210 can for example be W, TiN, TiAlN, Ta, TaN, poly-Si, TiSiN or TaSiN, this second dielectric layer 212 is as hard mask layer, its material can be siliceous compound, for example silicon nitride or silica, the purpose that this hard mask layer is set is to make follow-up formed figure accurate, in another preferred embodiment of the present invention, also this hard mask layer can be set.
Then, please refer to Fig. 4 c, this photoresist layer 216 is carried out the photoengraving carving technology, and continue and carry out little cutting (trim) technology, to form the photoresist post figure 218 that diameter of section is not more than 100nm.It should be noted that this photoresist post figure 218 be positioned at this first electrode 208 directly over.The present invention can for example be little technology or the little technology (for example little technology of cutting of plasma) of cutting of dry type of cutting of solvent for employed little technology and indefinite of cutting.
Then, please refer to Fig. 4 d, utilize etch process to remove this photoresist post figure 218 and bottom anti-reflection layer 214 fully, with with the photoresist figure transfer to this second dielectric layer (hard mask layer) 212, form column second dielectric layer 222 that diameter of section is not more than 100nm, wherein this column second dielectric layer 222 is positioned on this first electrode 208 and with this first electrode 208 and contacts.One of technical characterictic of the present invention is to utilize photoetching etching and little cutting (trim) technology to obtain less photoresist dimension of picture, utilizes this photoresist figure as mask, on figure transfer to the second dielectric layer 212 again.Then, please refer to Fig. 4 e, as etching mask, this first conductive layer 210 carried out etching with this column second dielectric layer 222, with the figure transfer of column second dielectric layer 222 to this first conductive layer 210, form conductive pole 220.This conductive pole 222 is formed on this first electrode 208, and is in direct contact with it, and is electrically connected to form.It should be noted that, for dwindling the contact area of conductive pole 220 and the phase change layer of follow-up formation, can optionally carry out little cutting (trim) technology according to this column second dielectric layer 222 of a certain preferred embodiment of the present invention, make it obtain more this long-pending conductive pole 220 of small bore, to obtain the long-pending conductive pole 220 of small cross sections.According to the present invention, the diameter of section of this conductive pole 220 is not more than 100nm.
Then, please refer to Fig. 4 f, form the 3rd dielectric layer 224 in this substrate 202, and cover this conductive pole 220 fully.Then, please refer to Fig. 4 g, planarization the 3rd dielectric layer 224 is until the upper surface that exposes this conductive pole 220.Wherein, the step of this planarization can for example be a chemical mechanical milling tech.The 3rd dielectric layer 224 can be siliceous compound, for example silicon nitride or silica.
Then, please refer to Fig. 4 h, form phase change layer 226 on the 3rd dielectric layer 224, and directly contact, form electrical connection with the upper surface of this conductive pole 222.This phase change layer 226 can be the material that comprises Ge, Sb, Te or its mixing, is preferably GeSbTe or InGeSbTe, also can be the employed material in other this area.
Then, please refer to Fig. 4 i, form the 4th dielectric layer 228 on the 3rd dielectric layer 224 and this phase change layer 226, wherein the 4th dielectric layer 228 has the upper surface that second opening 230 exposes this phase change layer 226.The 4th dielectric layer 228 can be siliceous compound, for example silicon nitride or silica.
Please refer to Fig. 4 j, form second conductive layer 232 in this second opening 230 and fill up this second opening 230, wherein this second conductive layer 232 is electrically connected with this phase change layer 226, and is last, forms second electrode 234 and is electrically connected with this second conductive layer 232.Wherein, the material of this second conductive layer 232 is W, TiN, TiAlN, Ta, TaN, poly-Si, TiSiN or TaSiN, and the material of this second electrode 234 is Al, W, Mo, TiN or TiW.
In sum, the invention has the advantages that, quote the employed photoetching/etching of semiconductor technology-little technology of cutting in the technology of Ovonics unified memory, reduce the contact area of phase change layer and zone of heating, reduce the operating current of Ovonics unified memory, increase memory density.In addition, the present invention also utilizes photoetching/etching-little technology of cutting to form the long-pending column dielectric layer of small cross sections, utilize sedimentation to form the sidewall of thin conductive layer again at this column dielectric layer, since the contact area of conductive layer and phase change layer depends on the thickness of this conductive layer, and present semiconductor process techniques can be controlled the thickness of this first conductive layer easily, therefore can define very little phase change layer contact area.Moreover processing step of the present invention is simple, can make this Ovonics unified memory with conventional semiconductor technology and equipment.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; can carry out a little change and modification to it, so protection scope of the present invention is with being as the criterion that claims were defined.
Claims (34)
1. Ovonics unified memory comprises:
Substrate;
First dielectric layer with first opening is formed on this substrate;
First electrode is formed in this first opening and fills up this first opening;
Second dielectric layer is formed on this first electrode;
First conductive layer is formed on the sidewall of this second dielectric layer, and is electrically connected with this first electrode;
The 3rd dielectric layer covers this first electrode fully and coats the sidewall of this first conductive layer, and exposes the upper surface of this first conductive layer;
Phase change layer is formed on the 3rd dielectric layer and with the upper surface of this first conductive layer and contacts;
The 4th dielectric layer is formed on the 3rd dielectric layer and this phase change layer, and wherein the 4th dielectric layer has the upper surface that second opening exposes this phase change layer;
Second conductive layer is formed in this second opening and fills up this second opening, and is electrically connected with this phase change layer; With
Second electrode is electrically connected with this second conductive layer.
2. Ovonics unified memory as claimed in claim 1, wherein this second dielectric layer is column second dielectric layer.
3. Ovonics unified memory as claimed in claim 1 comprises that also the 5th dielectric layer covers this first conductive layer, but does not cover the upper surface of this first conductive layer.
4. Ovonics unified memory as claimed in claim 2, wherein the diameter of section of this column second dielectric layer is not more than 100nm.
5. Ovonics unified memory as claimed in claim 1, wherein the leading portion manufacturing process of CMOS has been finished in this substrate.
6. Ovonics unified memory as claimed in claim 1, wherein the material of this first dielectric layer is a silicon compound.
7. Ovonics unified memory as claimed in claim 1, wherein the material of this first dielectric layer is silicon nitride or silica.
8. Ovonics unified memory as claimed in claim 1, wherein the material of this first electrode is Al, W, Mo, TiN or TiW.
9. Ovonics unified memory as claimed in claim 1, wherein the material of this first conductive layer is W, TiN, TiAlN, Ta, TaN, poly-Si, TiSiN or TaSiN.
10. Ovonics unified memory as claimed in claim 1, wherein the material of this first conductive layer is Al, W, Mo, TiN or TiW.
11. Ovonics unified memory as claimed in claim 1, wherein the material of this second dielectric layer is a silicon compound.
12. Ovonics unified memory as claimed in claim 1, wherein this phase change layer is the material that comprises Ge, Sb, Te or its mixing.
13. Ovonics unified memory as claimed in claim 1, wherein this phase change layer is GeSbTe or InGeSbTe.
14. Ovonics unified memory as claimed in claim 1, wherein the material of the 3rd dielectric layer is a silicon compound.
15. Ovonics unified memory as claimed in claim 1, wherein the material of the 4th dielectric layer is a silicon compound.
16. Ovonics unified memory as claimed in claim 1, wherein the material of this second electrode is Al, W, Mo, TiN or TiW.
17. Ovonics unified memory as claimed in claim 1, wherein the material of this second conductive layer is W, TiN, TiAlN, Ta, TaN, poly-Si, TiSiN or TaSiN.
18. Ovonics unified memory as claimed in claim 1, wherein the thickness of this first conductive layer is less than 50nm.
19. the manufacture method of an Ovonics unified memory comprises:
Substrate is provided;
Formation has first dielectric layer of first opening;
Form first electrode in this first opening and fill up this first opening;
Form the column second dielectric layer position on this first electrode;
Compliance forms first conductive layer in this substrate, and wherein this first conductive layer coats the sidewall and the upper surface of this column second dielectric layer fully;
This first conductive layer of anisotropic etching is up to the upper surface that exposes this column second dielectric layer;
Form the 3rd dielectric layer in this substrate, and planarization the 3rd dielectric layer is to expose the upper surface of this first conductive layer;
Forming phase change layer directly contacts on the 3rd dielectric layer and with the upper surface of this first conductive layer;
Form the 4th dielectric layer on the 3rd dielectric layer and this phase change layer, wherein the 4th dielectric layer has the upper surface that second opening exposes this phase change layer;
Form second conductive layer in this second opening and fill up this second opening, wherein this second conductive layer is electrically connected with this phase change layer; And
Forming second electrode is electrically connected with this second conductive layer.
20. the manufacture method of Ovonics unified memory as claimed in claim 19, the step that wherein forms this column second dielectric layer comprises:
Form second dielectric layer and photoresist layer on this substrate;
This photoresist layer is carried out etching and little technology of cutting, to form the top that the photoresist post is positioned at this first electrode; And
Utilize this photoresist post as this second dielectric layer of mask etching, to form this column second dielectric layer.
21. the manufacture method of Ovonics unified memory as claimed in claim 19, wherein the leading portion manufacturing process of CMOS has been finished in this substrate.
22. the manufacture method of Ovonics unified memory as claimed in claim 20 also comprises forming bottom anti-reflection layer between this second dielectric layer and this photoresist layer.
23. the manufacture method of Ovonics unified memory as claimed in claim 20, wherein this little technology of cutting comprises little technology or the little technology of cutting of solvent of cutting of dry type.
24. the manufacture method of Ovonics unified memory as claimed in claim 19 wherein forms this first conductive layer after this substrate in compliance, comprises that also compliance forms the 5th dielectric layer on this first conductive layer.
25. the manufacture method of Ovonics unified memory as claimed in claim 19, wherein the thickness of this first conductive layer is less than 50nm.
26. the manufacture method of Ovonics unified memory as claimed in claim 19, wherein the diameter of section of this column second dielectric layer is not more than 100nm.
27. the manufacture method of an Ovonics unified memory comprises:
Substrate is provided;
Formation has first dielectric layer of first opening;
Form first electrode in this first opening and fill up this first opening;
Utilize second dielectric layer to form conductive pole on this first electrode;
Form the 3rd dielectric layer in this substrate, and planarization the 3rd dielectric layer is until the upper surface that exposes this conductive pole;
Forming phase change layer directly contacts on the 3rd dielectric layer and with the upper surface of this conductive pole;
Form the 4th dielectric layer on the 3rd dielectric layer and this phase change layer, wherein the 4th dielectric layer has the upper surface that second opening exposes this phase change layer;
Form second conductive layer in this second opening and fill up this second opening, wherein this second conductive layer is electrically connected with this phase change layer; And
Forming second electrode is electrically connected with this second conductive layer.
28. the manufacture method of Ovonics unified memory as claimed in claim 27 is wherein utilized second dielectric layer to form the method for this conductive pole on this first electrode and be may further comprise the steps:
Form first conductive layer, this second dielectric layer and photoresist layer on this substrate;
This photoresist layer is carried out little manufacturing process of cutting, to form the top that the photoresist post is positioned at this first electrode;
Utilize this photoresist post as this second dielectric layer of mask etching, be positioned on this first electrode to form column second dielectric layer; And
Utilize this column second dielectric layer as this first conductive layer of mask etching, form this conductive pole.
29. the manufacture method of Ovonics unified memory as claimed in claim 27, wherein the leading portion manufacturing process of CMOS has been finished in this substrate.
30. the manufacture method of Ovonics unified memory as claimed in claim 28 also comprises forming bottom anti-reflection layer between this second dielectric layer and this photoresist layer.
31. the manufacture method of Ovonics unified memory as claimed in claim 28, the method that wherein forms the photoresist post comprises little technology or the little technology of cutting of solvent of cutting of dry type.
32. the manufacture method of Ovonics unified memory as claimed in claim 27, wherein this second dielectric layer is a hard mask layer.
33. the manufacture method of Ovonics unified memory as claimed in claim 27, the method that wherein forms this conductive pole comprises:
Utilize this column second dielectric layer as this first conductive layer of mask etching, and the patterned conductive layer of gained is carried out little technology of cutting.
34. the manufacture method of Ovonics unified memory as claimed in claim 27, wherein the diameter of section of this conductive pole is not more than 100nm.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104425710A (en) * | 2013-08-20 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Phase change random access memory and forming method thereof |
| CN105098071A (en) * | 2015-07-08 | 2015-11-25 | 宁波时代全芯科技有限公司 | Method for manufacturing phase-change memory |
| CN110473886A (en) * | 2018-05-11 | 2019-11-19 | 联华电子股份有限公司 | The manufacturing method of semiconductor element |
| CN111769195A (en) * | 2020-07-13 | 2020-10-13 | 上海集成电路研发中心有限公司 | Phase change memory unit and preparation method thereof |
-
2006
- 2006-09-20 CN CNB2006101543000A patent/CN100553004C/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104425710A (en) * | 2013-08-20 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Phase change random access memory and forming method thereof |
| CN104425710B (en) * | 2013-08-20 | 2017-05-17 | 中芯国际集成电路制造(上海)有限公司 | Phase change random access memory and forming method thereof |
| CN105098071A (en) * | 2015-07-08 | 2015-11-25 | 宁波时代全芯科技有限公司 | Method for manufacturing phase-change memory |
| CN105098071B (en) * | 2015-07-08 | 2018-01-05 | 江苏时代全芯存储科技有限公司 | The method for manufacturing phase-change memory |
| CN110473886A (en) * | 2018-05-11 | 2019-11-19 | 联华电子股份有限公司 | The manufacturing method of semiconductor element |
| CN111769195A (en) * | 2020-07-13 | 2020-10-13 | 上海集成电路研发中心有限公司 | Phase change memory unit and preparation method thereof |
| CN111769195B (en) * | 2020-07-13 | 2024-05-14 | 上海集成电路研发中心有限公司 | Phase change memory unit and preparation method thereof |
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| CN100553004C (en) | 2009-10-21 |
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