CN101399314A - Phase-changing storage device and manufacture method thereof - Google Patents
Phase-changing storage device and manufacture method thereof Download PDFInfo
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- CN101399314A CN101399314A CNA200710161258XA CN200710161258A CN101399314A CN 101399314 A CN101399314 A CN 101399314A CN A200710161258X A CNA200710161258X A CN A200710161258XA CN 200710161258 A CN200710161258 A CN 200710161258A CN 101399314 A CN101399314 A CN 101399314A
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- heating source
- dielectric layer
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 238000000034 method Methods 0.000 title claims description 47
- 238000010438 heat treatment Methods 0.000 claims abstract description 85
- 239000012782 phase change material Substances 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 4
- 150000001786 chalcogen compounds Chemical class 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 55
- 239000000758 substrate Substances 0.000 description 11
- 238000005192 partition Methods 0.000 description 6
- 239000002184 metal Substances 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910000618 GeSbTe Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052714 tellurium Inorganic materials 0.000 description 1
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Abstract
The invention discloses a phase-change memory and a manufacturing method thereof. The phase-change memory comprises: an electrode; a first dielectric layer which is formed on the electrode; an opening which penetrates the first dielectric layer to expose the electrode; a heating source which is formed in the opening and contacted with the electrode, wherein, the heating source comprises a heat source extension part to be extended out of the opening; a second dielectric layer which covers the heating source to expose the top part of the heating source extension part; and a phase-change material layer which is formed on the second dielectric layer and is directly contacted with the top part of the heating source extension part.
Description
Technical field
The present invention relates to a kind of memory and manufacture method thereof, particularly a kind of Ovonics unified memory and manufacture method thereof.
Background technology
Ovonics unified memory has high reading speed, low-power, high power capacity, high-reliability, height and writes speciality such as wiping number of times, low-work voltage/electric current and low cost, and be fit to very much combine with CMOS technology, can be used as the stand alone type or the Embedded memory application of higher density, is the new memory of future generation that very is expected at present.Because the unique advantage of Ovonics unified memory technology, also make it be considered to might replace very much the highly competititve SRAM of present commercialization and DRAM volatile storage and Flash non-volatility memorizer technology, be expected to become following potential new generation semiconductor memory.
The phase change memory device framework is very simple, mainly is to make the path that electrode material is used as current flowing respectively between about the phase-transition material, and the most general at present adopted framework is a T type framework.The practice of this framework be under phase-transition material, add heating of metal fasten the plug packed layer, its benefit is the contact area that can reduce between heating of metal and the phase-transition material, can promote the efficiency of heating surface of heating electrode and reduce the operating current of phase change memory device.Under such framework, amorphous area will occur in the highest zone of current density.
Take a broad view of the development trend of present Ovonics unified memory, can find significantly that main bottleneck is to be that the operating current of element is excessive, thereby the driving transistors area that can't reduce phase change memory device effectively and be connected in series, cause the excessive problem that makes that memory density can't promote of unit sizes.Reducing the Ovonics unified memory operating current can reach by dwindling in the phase change memory cell contact area of phase change layer and electrode, and helps dwindling and the lifting of memory density of cmos element.Yet the method can be subject to the restriction of photoetching and technological ability, is difficult for obtaining to break through effectively.
For addressing the above problem, U.S. Pat 6,750 proposes a kind of manufacture method that forms Ovonics unified memory 10 in 079, please refer to Fig. 1, and it forms earlier has the patterned dielectric layer 14 of vertical sidewall in substrate 12; Then compliance forms metal level in this dielectric layer 14 and substrate 12; Follow this metal level of anisotropic etching, have the metallic partitions 16 of less thickness with formation; Then, form dielectric layer 18 so that the side of this metallic partitions 16 is coated by dielectric layer fully; At last, form phase change layer 20, electrode layer 22, and protective layer 24 in regular turn.Yet when this metal level of anisotropic etching formed this metallic partitions 16, easy this metallic partitions 16 of over etching made the dielectric layer 18 of follow-up formation after planarization, covers this metallic partitions 16, causes short circuit 30, as shown in Figure 2.
In view of this, design the technology of a brand-new phase change memory device, to overcome the shortcoming of above-mentioned known technology, the real emphasis that need study for the Ovonics unified memory technology utmost point.
Summary of the invention
The invention provides a kind of Ovonics unified memory and manufacture method thereof, utilize etch process, reach the purpose of dwindling heating source and phase change layer contact area, effectively reduce operating current and energy the further micro of the sectional width of heating source extension (shrink).The manufacture method of this Ovonics unified memory comprises: formation has first dielectric layer of opening on electrode; The formation heating comes from this opening and with this electrode and contacts, and wherein the upper surface of this heating source exceeds the upper surface of this first dielectric layer, constitutes the heating source extension with first sectional width; This heating source is carried out etch process, so that the heating source extension after the etching has second sectional width, wherein this second sectional width is less than first sectional width; Form second dielectric layer, cover the heating source extension after this etching; This second dielectric layer of planarization is to expose this heating source extension; And, form phase-change material layer on this second dielectric layer, and directly contact with this heating source extension.
In addition, the present invention also provides a kind of Ovonics unified memory.According to one embodiment of the invention, this Ovonics unified memory comprises: electrode; First dielectric layer, this first dielectric layer is formed on this electrode; Opening, this opening run through this first dielectric layer, to expose this electrode; Heating source, this heating source are formed in this opening and with this electrode and contact, and wherein this heating source has the heating source extension, extends this opening; Second dielectric layer covers this heating source, exposes the top of this heating source extension; And phase-change material layer is formed on this second dielectric layer, directly contacts with the top of this heating source extension.
Below by a plurality of embodiment and comparing embodiment, illustrating further method of the present invention, feature and advantage, but be not to be used for limiting the scope of the invention, scope of the present invention should be as the criterion with appended claim.
Description of drawings
Fig. 1 and Fig. 2 are the sectional structure charts that shows known Ovonics unified memory.
Fig. 3 a to 3h is the making flow process profile that shows the described Ovonics unified memory of one embodiment of the invention.
Description of reference numerals
Ovonics unified memory～10; Substrate～12;
Dielectric layer～14; Metallic partitions～16;
Dielectric layer～18; Phase change layer～20;
Electrode layer～22; Protective layer～24;
Short circuit takes place～30; Substrate～100;
Bottom electrode～102; Heating source～104;
Dielectric layer～105,105a; Heating source extension～106,106a;
The upper surface of this heating source～121; The upper surface of dielectric layer～122;
Etch process～125; The top of heating source extension～130;
The bottom of heating source extension～134; Dielectric layer～135;
Dielectric layer upper surface～136; Phase-change material layer～140;
Top electrode～150; Length～L;
First sectional width～W1; Second sectional width～W2.
Embodiment
Below, ask conjunction with figs., describe the manufacture method of the described Ovonics unified memory of embodiments of the invention in detail.
At first, please refer to Fig. 3 a, substrate 100 is provided, be formed with bottom electrode 102 on it, and heating source 104 is formed on this bottom electrode 102, and dielectric layer 105 coats these heating sources 104.It should be noted that in this step the upper surface of the upper surface of this dielectric layer 105 and this heating source 104 is a copline.Heating source 104 for example is the column heating source.
Wherein, this substrate 100 can be the employed substrate of semiconductor technology, for example is silicon substrate.This substrate 100 can be the substrate of finishing the CMOS FEOL, also may comprise isolation structure, electric capacity, diode and its analog, for the purpose of simplicity of illustration, only represents with smooth substrate among the figure.This bottom electrode 102 is an electric conducting material, for example is TaN, W, TiN or TiW.Dielectric layer 105 can be known employed any dielectric material.This heating source 104 has the first sectional width W1, this first sectional width W1 can between
Between, for example be
The material of heating source 104 for example comprises TaN, W, TiN or TiW.
Then, please refer to Fig. 3 b, this dielectric layer 105 of etch-back so that the upper surface 121 of this heating source 104 exceeds the upper surface 122 of remaining dielectric layer 105a, constitutes heating source extension 106.The step that removes this dielectric layer 105 can be etch process, for example is dry etching process or wet etching process.In addition, the step that removes this dielectric layer 105 also can be grinding technics, for example chemico-mechanical polishing.
Then, please refer to Fig. 3 c, utilize this heating source extension 106 of etch process 125 micros (shrink), so that the top 130 of the heating source extension 106a after the etching is contracted to the second sectional width W2 (this width can less than exposure the limit), and have length L, this length L can between
Between, for example be
,
Or
Please refer to shown in Fig. 3 d.This second sectional width W2 can between
Between, for example be
It should be noted that, when utilizing this heating source extension 106 of etch process 125 micros, owing to will make this heating source extension 106 of selective etch, avoid this dielectric layer 105a etched, therefore this etch process must be greater than the etch-rate to dielectric layer 105a to the etch-rate of heating source extension 106, in general, this etch process for example is more than 50 times of etch-rate to dielectric layer 105a for the etch-rate of heating source extension 106.This etch process can be dry etching process or wet etching process, for example can be wet etching process.Shown in Fig. 3 d, the bottom 134 of the heating source extension 106a after this etching can be lower than the upper surface 122 of this first dielectric layer.In addition, in another embodiment of the present invention, the bottom of the heating source extension after this etching also can be higher than the upper surface of this first dielectric layer.
Then, please refer to Fig. 3 e, form dielectric layer 135, cover the heating source extension 106a after this etching.This dielectric layer 135 can be known employed any dielectric material.
Then, please refer to Fig. 3 f, this dielectric layer 135 of planarization is to expose the top 130 of this heating source extension 106a.This flatening process can be CMP (Chemical Mechanical Polishing) process, or an etch-back.It should be noted that the upper surface 136 of this dielectric layer 135 and 130 surfaces, top of this heating source extension 106a trim, or 130 surfaces, top of this heating source extension 106a are higher than the upper surface 136 of this dielectric layer 135.
Then, please refer to Fig. 3 g, form phase-change material layer 140 on this dielectric layer 135,, form electrically connect so that this phase-change material layer 140 directly contacts with the top 130 of this heating source extension 106a.Wherein, this phase-transition material can be made of chalcogen compound, for example contains the material of Ge, Sb, Te or its mixing, for example can be GeSbTe or InGeSbTe.
At last, please refer to Fig. 3 h, form top electrode 150 on this phase-change material layer 140, with these phase-change material layer 140 electrically connects.So far, finish the described Ovonics unified memory of one embodiment of the invention.This top electrode 150 is an electric conducting material, for example is TaN, W, TiN or TiW.
In sum, the invention has the advantages that, utilize etch process to come the extension of this heating source of micro, obtain extension sectional width, effectively promote the efficiency of heating surface less than the exposure limit.In addition, the present invention's dielectric layer material with low thermal conductance coefficient of can arranging in pairs or groups coats this heating source extension, and the phase change generating region of this phase-transition material helps insulation in this phase change layer.
Though the present invention discloses as above with embodiment; right its is not in order to limit the present invention; those skilled in the art without departing from the spirit and scope of the present invention, when can doing a little change and retouching, so protection scope of the present invention is when looking being as the criterion that accompanying Claim defines.
Claims (20)
1. the manufacture method of an Ovonics unified memory comprises:
Formation has first dielectric layer of opening on electrode;
The formation heating comes from this opening and with this electrode and contacts, and wherein the upper surface of this heating source exceeds the upper surface of this first dielectric layer, constitutes the heating source extension with first sectional width;
This heating source is carried out etch process, so that this heating source extension after the etching has second sectional width, wherein this second sectional width is less than this first sectional width;
Form second dielectric layer, cover the heating source extension after this etching;
This second dielectric layer of planarization is to expose this heating source extension; And
Form phase-change material layer on this second dielectric layer, and directly contact with this heating source extension.
2. the manufacture method of Ovonics unified memory as claimed in claim 1, wherein this phase-transition material is made of chalcogen compound.
3. the manufacture method of Ovonics unified memory as claimed in claim 1, wherein this second sectional width is less than the exposure limit.
4. the manufacture method of Ovonics unified memory as claimed in claim 1, wherein the formation method of this heating source extension comprises:
Forming this heating comes from this opening; And
Remove this first dielectric layer of part,, constitute this heating source extension so that the upper surface of this heating source exceeds the upper surface of the first remaining dielectric layer.
5. the manufacture method of Ovonics unified memory as claimed in claim 1, wherein the length of this extension between 10～
Between.
6. the manufacture method of Ovonics unified memory as claimed in claim 1, wherein this second sectional width between 10～
Between.
7. the manufacture method of Ovonics unified memory as claimed in claim 1, wherein this etch process to the etch-rate of this heating source greater than etch-rate to this first dielectric layer.
8. the manufacture method of Ovonics unified memory as claimed in claim 1, wherein this etch process is more than 50 times of etch-rate to this first dielectric layer for the etch-rate of this heating source.
9. the manufacture method of Ovonics unified memory as claimed in claim 1, wherein this etch process is dry etching process or wet etching process.
10. the manufacture method of Ovonics unified memory as claimed in claim 1, wherein this planarisation step is a grinding technics.
11. the manufacture method of Ovonics unified memory as claimed in claim 1, wherein this heating source comprises electric conducting material.
12. the manufacture method of Ovonics unified memory as claimed in claim 1, wherein the material of this heating source comprises TaN, W, TiN or TiW.
13. an Ovonics unified memory comprises:
Electrode;
First dielectric layer, this first dielectric layer is formed on this electrode;
Opening, this opening run through this first dielectric layer, to expose this electrode;
Heating source, this heating source are formed in this opening and with this electrode and contact, and wherein this heating source has the heating source extension, extends this opening;
Second dielectric layer covers this heating source, exposes the top of this heating source extension; And
Phase-change material layer is formed on this second dielectric layer, directly contacts with the top of this heating source extension.
14. Ovonics unified memory as claimed in claim 13, wherein this phase-transition material is made of chalcogen compound.
15. Ovonics unified memory as claimed in claim 13, wherein the length of this heating source extension between 10～
Between.
16. Ovonics unified memory as claimed in claim 13, wherein the top sectional width of this heating source extension between 10～
Between.
17. Ovonics unified memory as claimed in claim 13, wherein the material of this heating source comprises TaN, W, TiN or TiW.
18. Ovonics unified memory as claimed in claim 13, wherein the upper surface of the upper surface at the top of this heating source extension and this second dielectric layer trims.
19. Ovonics unified memory as claimed in claim 13, wherein the upper surface at the top of this heating source extension is higher than the upper surface of this second dielectric layer.
20. Ovonics unified memory as claimed in claim 13, wherein the bottom of this heating source extension is lower than the upper surface of this first dielectric layer.
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| CN200710161258XA CN101399314B (en) | 2007-09-25 | 2007-09-25 | Phase-changing storage device and manufacture method thereof |
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|---|---|---|---|
| CN200710161258XA CN101399314B (en) | 2007-09-25 | 2007-09-25 | Phase-changing storage device and manufacture method thereof |
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| CN101399314A true CN101399314A (en) | 2009-04-01 |
| CN101399314B CN101399314B (en) | 2010-06-09 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104900806A (en) * | 2015-06-04 | 2015-09-09 | 宁波时代全芯科技有限公司 | Phase change memory element and manufacturing method thereof |
| CN105098072A (en) * | 2015-07-30 | 2015-11-25 | 宁波时代全芯科技有限公司 | Manufacturing method of phase change storage apparatus |
| CN105261701A (en) * | 2015-09-09 | 2016-01-20 | 宁波时代全芯科技有限公司 | Method for manufacturing phase change memory |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6750079B2 (en) * | 1999-03-25 | 2004-06-15 | Ovonyx, Inc. | Method for making programmable resistance memory element |
| US7220983B2 (en) * | 2004-12-09 | 2007-05-22 | Macronix International Co., Ltd. | Self-aligned small contact phase-change memory method and device |
| KR100682937B1 (en) * | 2005-02-17 | 2007-02-15 | 삼성전자주식회사 | Phase change memory device and fabricating method of the same |
| KR100682948B1 (en) * | 2005-07-08 | 2007-02-15 | 삼성전자주식회사 | Phase change memory device and methof of fabricating the same |
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2007
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104900806A (en) * | 2015-06-04 | 2015-09-09 | 宁波时代全芯科技有限公司 | Phase change memory element and manufacturing method thereof |
| CN104900806B (en) * | 2015-06-04 | 2018-06-05 | 江苏时代全芯存储科技有限公司 | The manufacturing method of phase-change memory cell |
| CN105098072A (en) * | 2015-07-30 | 2015-11-25 | 宁波时代全芯科技有限公司 | Manufacturing method of phase change storage apparatus |
| CN105098072B (en) * | 2015-07-30 | 2017-08-08 | 江苏时代全芯存储科技有限公司 | The manufacture method of phase-change memory |
| CN105261701A (en) * | 2015-09-09 | 2016-01-20 | 宁波时代全芯科技有限公司 | Method for manufacturing phase change memory |
| CN105261701B (en) * | 2015-09-09 | 2017-12-08 | 江苏时代全芯存储科技有限公司 | The method for manufacturing phase-change memory |
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| CN101399314B (en) | 2010-06-09 |
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