CN111769195B - Phase change memory unit and preparation method thereof - Google Patents
Phase change memory unit and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title abstract description 10
- 239000012782 phase change material Substances 0.000 claims abstract description 340
- 230000000087 stabilizing effect Effects 0.000 claims abstract description 138
- 238000000034 method Methods 0.000 claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 claims abstract description 17
- 238000000926 separation method Methods 0.000 claims abstract description 12
- 230000006641 stabilisation Effects 0.000 claims description 77
- 238000011105 stabilization Methods 0.000 claims description 77
- 239000000758 substrate Substances 0.000 claims description 29
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 11
- 229910052723 transition metal Inorganic materials 0.000 claims description 10
- 150000003624 transition metals Chemical class 0.000 claims description 10
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 9
- 229910021332 silicide Inorganic materials 0.000 claims description 8
- 229910004200 TaSiN Inorganic materials 0.000 claims description 5
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 claims description 5
- 230000008569 process Effects 0.000 abstract description 14
- 230000010354 integration Effects 0.000 abstract description 7
- 239000000463 material Substances 0.000 description 23
- 239000000126 substance Substances 0.000 description 9
- 238000005530 etching Methods 0.000 description 8
- 238000000206 photolithography Methods 0.000 description 8
- 229910052787 antimony Inorganic materials 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- 238000005498 polishing Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
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- 239000010703 silicon Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
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- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910004491 TaAlN Inorganic materials 0.000 description 2
- 229910008484 TiSi Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
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- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910005881 NiSi 2 Inorganic materials 0.000 description 1
- 229910005913 NiTe Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
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- 239000010409 thin film Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/021—Formation of switching materials, e.g. deposition of layers
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- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/861—Thermal details
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
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Abstract
The invention discloses a phase change memory unit which comprises a bottom electrode, a phase change material stabilizing layer, a phase change material layer and a top electrode which are sequentially connected; the phase change material stabilizing layer has conductivity, and the phase change material stabilizing layer and the phase change material layer react at the interface at a certain temperature to avoid the failure of the phase change unit caused by the separation of elements in the phase change material layer. Meanwhile, the phase change material stabilizing layer divides the phase change material layer into left and right 2 areas, a 2R structure is formed, and the integration density of the phase change unit can be improved. The invention also discloses a preparation method of the phase-change memory unit, which has simple process, can be compatible with the existing standard CMOS process and is easy for mass production.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit manufacturing technology, and more particularly, to a phase change memory cell with high reliability and high integration density and a method for manufacturing the same.
Background
With the advent of a series of novel information technologies such as big data, internet of things, cloud computing and artificial intelligence, requirements such as high read-write speed, low power consumption, high storage density, long service life and high reliability are provided for a memory.
At present, the memory storage modes mainly comprise DRAM and Flash. Wherein NAND FLASH has high integration level, low cost, but slow speed and short service life; the DRAM is fast and has long service life, but loses data after power failure and has higher cost. Therefore, a new memory technology is developed, which is a research hot spot in recent years in the industry, and the new memory technology has the advantages of DRAM and NAND FLASH at the same time, that is, the read-write speed can be comparable to that of DRAM, and the cost and the nonvolatile are similar to NAND FLASH, and the phase change memory is one member of the new memory technology. In recent years, the phase change memory unit has wide application prospect in an artificial intelligence and memory integrated chip.
Please refer to fig. 1. The existing phase change memory unit consists of a bottom electrode, a phase change material and a top electrode which are arranged on a substrate from bottom to top. Wherein the mushroom shaped dashed area in the phase change material illustrated near the bottom electrode represents a reversible phase change area in which the phase change material is capable of reversible switching between amorphous and crystalline states under operation of an electrical pulse.
As shown in fig. 2, the phase change material of the alloy undergoes element separation (aggregation of elements such as antimony and tellurium toward the cathode) during repeated operation, particularly when the phase change material is changed from a crystalline state to an amorphous state (the temperature is about 500-800 ℃). In this way, loss of antimony near the anode can form mobile nanovoids and eventually accumulate at the interface with the anode, causing a break in the interface between the phase change material layer and the upper electrode, resulting in device failure.
Therefore, how to prevent the phase change unit from being invalid due to the separation of the elements in the phase change material layer, and to prepare the phase change memory unit with high reliability is a technical problem to be solved urgently in the industry.
Disclosure of Invention
The present invention is directed to overcoming the above-mentioned drawbacks of the prior art and providing a phase change memory cell and a method for fabricating the same.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
A phase change memory cell comprises a bottom electrode, a phase change material stabilizing layer, a phase change material layer and a top electrode which are sequentially connected; the phase change material stabilizing layer has conductivity, and the phase change material stabilizing layer and the phase change material layer react at an interface at a certain temperature, so that the phase change material stabilizing layer and the phase change material layer are prevented from being invalid due to separation of elements in the phase change material layer.
Further, the bottom electrode is arranged on the lower layer of the phase change material stabilizing layer, and the two phase change material layers are respectively arranged on two sides of the phase change material stabilizing layer and are respectively connected with one top electrode arranged on the upper layer of the phase change material stabilizing layer.
Further, the phase change material stabilizing layers are two phase change material stabilizing layers which are separated in the horizontal direction, and the two phase change material stabilizing layers are respectively connected with one phase change material layer on the corresponding side.
Further, each phase change material stabilizing layer comprises a first phase change material stabilizing layer and a second phase change material stabilizing layer which are connected from outside to inside, and the bottom electrode is connected with the first phase change material stabilizing layer and the second phase change material stabilizing layer at the same time.
Further, the phase change material stabilization layer includes at least one of a transition metal carbide and a metal silicide.
Further, the phase change material stabilization layer includes at least one of SiC, WN, tiAlN, taAlN, tiSiN and TaSiN.
A method of fabricating a phase change memory cell, comprising the steps of:
step S01: forming a bottom electrode and first dielectric layers positioned on two sides of the bottom electrode on a semiconductor substrate;
Step S02: sequentially forming a phase change material stabilizing layer and a second dielectric layer on the surface of the bottom electrode;
step S03: sequentially forming a phase change material layer and a third medium layer on the two side surfaces of the phase change material stabilizing layer and the second medium layer;
step S04: and forming a top electrode on the surfaces of the phase change material layers at two sides respectively.
Further, in step S02, the phase change material stabilization layer covers the bottom electrode therein in a vertical projection direction; in step S03, the upper surface of the phase change material layer is flush with the upper surface of the second dielectric layer and the upper surface of the third dielectric layer.
A method of fabricating a phase change memory cell, comprising the steps of:
step S11: forming a bottom electrode and first dielectric layers positioned on two sides of the bottom electrode on a semiconductor substrate;
Step S12: covering a phase change material stabilizing layer on the bottom electrode and the first dielectric layer;
step S13: forming a second dielectric layer in the phase change material stabilizing layer corresponding to the bottom electrode, so as to form one phase change material stabilizing layer on two sides of the second dielectric layer respectively;
Step S14: forming a third dielectric layer on the phase change material stabilizing layer and the second dielectric layer;
Step S15: sequentially forming a phase change material layer and a fourth medium layer on the surfaces of the two sides of the phase change material stabilizing layer and the third medium layer;
step S16: and forming a top electrode on the surfaces of the phase change material layers at two sides respectively.
Further, in step S13, the upper surface of the second dielectric layer is flush with the upper surface of the phase change material stabilizing layer, the lower surface of the second dielectric layer is connected with the upper surface of the bottom electrode, and the second dielectric layer falls within the bottom electrode in the vertical projection direction; in step S14, the side surface of the third dielectric layer is flush with the side surface of the phase change material stabilizing layer, and the bottom electrode is covered in the outside of the phase change material stabilizing layer in the vertical projection direction; in step S15, the upper surface of the phase change material layer is flush with the upper surfaces of the third dielectric layer and the fourth dielectric layer.
A method of fabricating a phase change memory cell, comprising the steps of:
Step S21: forming a bottom electrode and first dielectric layers positioned on two sides of the bottom electrode on a semiconductor substrate;
step S22: covering a first phase change material stabilizing layer on the bottom electrode and the first dielectric layer;
Step S23: forming a second dielectric layer in the first phase change material stabilizing layer corresponding to the bottom electrode, and forming second phase change material stabilizing layers between two sides of the second dielectric layer and the first phase change material stabilizing layer respectively, so that one second phase change material stabilizing layer and one first phase change material stabilizing layer are formed on two sides of the second dielectric layer respectively;
step S24: forming a third dielectric layer on the first phase change material stabilizing layer, the second phase change material stabilizing layer and the second dielectric layer;
Step S25: sequentially forming a phase change material layer and a fourth medium layer on the surfaces of the two sides of the first phase change material stabilizing layer and the third medium layer;
step S26: and forming a top electrode on the surfaces of the phase change material layers at two sides respectively.
Further, in step S23, the upper surface of the second dielectric layer is flush with the upper surface of the second phase change material stabilizing layer and the upper surface of the first phase change material stabilizing layer, the lower surface of the second dielectric layer is connected with the upper surface of the bottom electrode, and the second dielectric layer falls within the bottom electrode in the vertical projection direction; in step S24, the side surface of the third dielectric layer is flush with the side surface of the first phase change material stabilizing layer, and the bottom electrode is covered in the outside of the first phase change material stabilizing layer in the vertical projection direction; in step S25, the upper surface of the phase change material layer is flush with the upper surfaces of the third dielectric layer and the fourth dielectric layer.
Further, the second phase change material stabilization layer has a higher thermal conductivity, a smaller electrical resistivity, and a more stable chemistry at a temperature than the first phase change stabilization layer.
Further, the temperature range includes 600-800 ℃.
According to the technical scheme, the phase change material stabilizing layer is arranged between the bottom electrode and the phase change material layer, so that the phase change unit failure caused by element separation in the phase change material can be avoided by utilizing the mechanism that the phase change material stabilizing layer can react with the phase change material layer at an interface (for example, elements in the phase change material stabilizing layer can chemically bond with elements in the phase change material layer such as Sb, te and the like, or the elements in the phase change material stabilizing layer can be coated at a grain boundary in the phase change material layer and the like), and normal phase change conversion of the phase change material layer can not be influenced, so that the reliability of the phase change memory unit is improved. The invention has the following advantages:
(1) The phase change material stabilizing layer is adopted to divide the phase change material layer into left and right 2 areas, a 2R structure is formed, and the integration density of the phase change unit can be improved.
(2) By adding the medium layer in the middle of the phase-change material stabilizing layer, better thermal isolation can be performed, and thermal crosstalk of the phase-change units at the left side and the right side caused by heating of the phase-change material stabilizing layer is avoided; and moreover, due to the reduction of the volume of the phase-change material stabilizing layer, the heat requirement can be effectively reduced, and the power consumption of the device is reduced.
(3) In order to improve the heating efficiency of the phase change material, the phase change material stabilization layer may be further divided into 2 materials (a first phase change material stabilization layer and a second phase change material stabilization layer); the first phase change material stabilizing layer connected with the phase change material layer can react with the phase change material, and compared with the second phase change material stabilizing layer connected with the bottom electrode, the first phase change material stabilizing layer has higher thermal conductivity and smaller resistivity, has more stable chemical property at high temperature, can effectively improve the heating efficiency of the phase change material, and reduces the power consumption of the phase change unit.
(4) The preparation method and the process are simpler, can be compatible with the existing standard CMOS process, and are easy for mass production.
Drawings
FIG. 1 is a schematic diagram of a conventional phase change memory cell.
Fig. 2 is a schematic diagram illustrating element separation of a phase change material layer in a conventional phase change cell.
Fig. 3-6 are schematic views illustrating the process steps of preparing a phase change memory cell according to a first embodiment of the present invention.
Fig. 7-12 are schematic views illustrating a process step of fabricating a phase change memory cell according to a second embodiment of the present invention.
Fig. 13-18 are schematic views illustrating a process step of fabricating a phase change memory cell according to a third embodiment of the present invention.
Detailed Description
The core idea of the invention is that the invention provides a phase change memory cell and a preparation method thereof. The phase change memory unit comprises a bottom electrode, a phase change material stabilizing layer, a phase change material layer and a top electrode which are sequentially connected; the phase change material stabilizing layer has conductivity, and the phase change material stabilizing layer reacts with the phase change material layer at the interface at a certain temperature, so that the problem of phase change unit failure caused by element separation in the phase change material layer can be avoided, and the phase change memory unit with high reliability and high integration density can be prepared by a simple method compatible with the conventional standard CMOS process.
The following describes the embodiments of the present invention in further detail with reference to the accompanying drawings.
In the following detailed description of the embodiments of the present invention, the structures of the present invention are not drawn to a general scale, and the structures in the drawings are partially enlarged, deformed, and simplified, so that the present invention should not be construed as being limited thereto.
Example 1
In the following detailed description, please refer to fig. 6, fig. 6 is a schematic diagram illustrating a phase change memory cell structure according to the present invention. As shown in fig. 6, the phase change memory cell is provided on one substrate 101. The substrate 101 may comprise a semiconductor material such as a silicon substrate, gallium arsenide substrate, germanium substrate, silicon germanium substrate, or Fully Depleted Silicon On Insulator (FDSOI) substrate, or the like. The substrate may also be an integrated circuit including an integrated circuit with gates such as transistors, diodes, etc. The substrate may also be an interconnect layer, such as a copper interconnect layer, a graphene interconnect layer, and the like.
Please refer to fig. 6. In this embodiment, a first dielectric layer 102 is disposed on a substrate 101, and a bottom electrode 103 is disposed in the first dielectric layer 102; and, the lower surface of the bottom electrode 103 is connected to the upper surface of the substrate 101. The bottom electrode 103 is disposed below the phase change material stabilization layer 104, and the upper surface of the bottom electrode 103 is connected to the lower surface of the phase change material stabilization layer 104. Meanwhile, the lateral dimension of the phase change material stabilization layer 104 is greater than the lateral dimension of the bottom electrode 103, i.e., the region of the bottom electrode 103 that is within the lateral dimension boundary of the phase change material stabilization layer 104.
The two phase change material layers 106 are respectively arranged at two sides of the phase change material stabilizing layer 104, the inner sides of the two phase change material layers 106 are respectively connected with the two side surfaces of the phase change material stabilizing layer 104, and the upper surfaces of the two phase change material layers 106 are respectively connected with the lower surface of one top electrode 108 positioned at the upper layer.
The phase change material stabilization layer 104 includes at least one of a transition metal carbide and a metal silicide.
Further, the phase change material stabilization layer 104 includes at least one of SiC, WN, tiAlN, taAlN, tiSiN and TaSiN.
The phase change material stabilization layer 104 may react with the phase change material layer 106 at an interface at a temperature, preferably in a temperature range of 600-800 ℃, so as to avoid the problem of phase change unit failure caused by separation of elements in the phase change material layer 106.
The chemical bonds of the transition metal carbide comprise metal bonds, covalent bonds and ionic bonds at the same time. Thus, at high temperatures (600-800 ℃), chemical bonds in the transition metal carbide may be partially broken, and metal elements therein may react with the phase change material. The metal silicide forms a high-resistance intermediate phase at about 600 ℃, and when the temperature is further increased, phase transformation occurs to form a low-resistance final phase. Therefore, at 600-800 ℃, the metal silicide can react with the phase change material at the same time of phase change. Accordingly, the phase change material stabilization layer 104 includes at least one of a transition metal carbide and a metal silicide. In addition, in order to prevent contamination risk caused by the introduction of new elements, the phase change material stabilizing layer material contains elements which are existing in the existing CMOS process.
SiC, WN, tiAlN, taAlN, tiSiN and TaSiN, etc. also have good conductivity and lower resistivity. Can react with the phase change material at a certain temperature. The SiC and the WN have the characteristics of excellent heat conductivity and high voltage resistance, and are suitable for preparing the phase change memory unit facing high voltage application. TiAlN, taAlN, tiSiN and TaSiN materials react with the phase change material to diffuse metal elements into the phase change material layer, and are coated at the grain boundary of the phase change material to refine the phase change material grains, thereby achieving the purposes of fixing elements such as Sb, te in the phase change material, avoiding the phase change unit failure caused by element separation in the phase change material, but not influencing the normal phase change conversion of the phase change material layer, and improving the reliability of the phase change memory unit.
A method for manufacturing a phase change memory cell according to the first embodiment of the present invention will be described in detail with reference to the accompanying drawings.
Please refer to fig. 3-6. The preparation method of the phase change memory unit according to the first embodiment of the invention comprises the following steps:
step S01: on a semiconductor substrate 101, a bottom electrode and a first dielectric layer 102 are formed.
As shown in fig. 3, in this embodiment, a silicon substrate 101 may be used, a first dielectric layer 102 is deposited on the silicon substrate 101, and a bottom electrode 103 is formed in the first dielectric layer 102. The bottom electrode 103 may be, for example, a tungsten electrode.
Step S02: a phase change material stabilization layer 104 and a second dielectric layer 105 are formed on the bottom electrode 103.
As shown in fig. 4, a phase change material stabilizing layer and a second dielectric layer material are sequentially deposited on the bottom electrode and the surface of the first dielectric layer, and then the phase change material stabilizing layer 104 and the second dielectric layer 105 are patterned by photolithography and etching processes.
Wherein the lateral dimension of the phase change material stabilization layer 104 is larger than the lateral dimension of the bottom electrode 103. In this embodiment, the phase change material stabilization layer 104 may be TaAlN.
When the temperature is 600-800 ℃, al in TaAlN can diffuse into the phase-change material layer and is coated at the grain boundary of the phase-change material to refine the phase-change material grains, thereby fixing elements such as Sb, te in the phase-change material, avoiding the phase-change unit failure caused by element separation in the phase-change material, but not influencing the normal phase-change conversion of the phase-change material layer, and improving the reliability of the phase-change memory unit.
Step S03: a phase change material layer 106 and a third dielectric layer 107 are formed on both sides of the phase change material stabilization layer 104 and the second dielectric layer 105.
As shown in fig. 5, materials of the phase change material layer 106 and the third dielectric layer 107 are deposited on the second dielectric layer 105, then the materials of the phase change material layer 106 and the third dielectric layer 107 on the surface of the second dielectric layer 105 are removed by chemical mechanical polishing, and a part of the materials of the second dielectric layer 105 are removed, and the phase change material layer 106 and the third dielectric layer 107 are formed only on two sides of the phase change material stabilizing layer 104 and the second dielectric layer 105.
The upper surface of the phase change material layer 106 is flush with the upper surfaces of the second dielectric layer 105 and the third dielectric layer 107.
In this embodiment, the phase change material layer 106 may be Ge2Sb2Te5.
Step S04: a top electrode 108 is formed on the phase change material layer 106.
As shown in fig. 6, a thin film of top electrode 108 is deposited on the surface of the device structure formed as described above, and two top electrodes 108 are formed by photolithography and etching processes, and the top electrodes 108 are respectively connected to the upper surfaces of the phase change material layer 106 on both sides of the phase change material stabilization layer 104, thereby forming a 2R structure.
In the first embodiment, the phase change material stabilization layer 104 and the phase change material layer 106 can react at the interface. The phase change material stabilization layer 104 is located between the bottom electrode 103 and the phase change material layer 106, and reacts with the phase change material layer 106 at the interface, including chemical reactions: the elements in the phase change material stabilization layer 104 can chemically bond with elements in the phase change material layer 106, such as Sb, te, etc.; or elements in phase change material stabilization layer 104 may be coated at grain boundaries in phase change material layer 106, etc. The reactions can avoid the phase change unit failure caused by element separation in the phase change material, but can not influence the normal phase change conversion of the phase change material layer, thereby improving the reliability of the phase change memory unit. Meanwhile, the phase change material stabilization layer 104 divides the phase change material layer 106 into left and right 2 areas, a 2R structure is formed, and the integration density of the phase change unit can be improved.
Example two
Please refer to fig. 12. In this embodiment, a first dielectric layer 202 is disposed on a substrate 201, and a bottom electrode 203 is disposed in the first dielectric layer 202; and, the lower surface of the bottom electrode 203 is connected to the upper surface of the substrate 201. The bottom electrode 203 is disposed below the phase change material stabilizing layer 204, and the upper surface of the bottom electrode 203 is connected to the lower surface of the phase change material stabilizing layer 204.
The two phase change material layers 207 are respectively arranged at two sides of the phase change material stabilizing layer 204, the inner sides of the two phase change material layers 207 are respectively connected with the two side surfaces of the phase change material stabilizing layer 204, and the upper surfaces of the two phase change material layers 207 are respectively connected with the lower surface of a top electrode 209 positioned at the upper layer.
The difference from the first embodiment is that in this embodiment, the phase change material stabilizing layer 204 is divided into two phase change material stabilizing layers 204 separated from each other in the horizontal direction by the second dielectric layer 205, and the two phase change material stabilizing layers 204 are each connected to one phase change material layer 207 located on the corresponding side.
Meanwhile, the lateral dimension that the two phase change material stabilizing layers 204 together occupy is larger than the lateral dimension of the bottom electrode 203, i.e., the region where the bottom electrode 203 is located within the outer boundaries of the two phase change material stabilizing layers 204 at the same time. Other aspects of the present embodiments regarding phase change memory cells may be understood and utilized with reference to embodiment one.
A method for manufacturing a phase change memory cell according to the second embodiment of the present invention will be described in detail with reference to the accompanying drawings.
Please refer to fig. 7-12. The preparation method of the phase change memory unit of the second embodiment of the invention comprises the following steps:
Step S11: on a semiconductor substrate 201, a bottom electrode 203 and a first dielectric layer 202 are formed as shown in fig. 7. In this embodiment, the substrate 201 with PMOS transistors may be used, and the bottom electrode 203 may be a tungsten electrode.
Step S12: a phase change material stabilization layer 204 is formed on the bottom electrode 203.
As shown in fig. 8, a phase change material stabilization layer 204 is deposited over the bottom electrode 203 and the first dielectric layer 202, such that the phase change material stabilization layer 204 is in communication with the bottom electrode 203. In this embodiment, the phase-change material stabilizing layer 204 may be TiSi, where Ti in TiSi diffuses into the phase-change material at 600-800 ℃ and combines with Te in the phase-change material to form TiTe 2, which can fix Te element in the phase-change material, and TiTe 2 has low thermal conductivity, which is very helpful for reducing power consumption of the phase-change unit.
Step S13: a second dielectric layer 205 is formed in the middle of the phase change material stabilization layer 204.
As shown in fig. 9, the phase change material stabilizing layer 204 is subjected to photolithography and etching, a contact hole is formed above the bottom electrode 203, a second dielectric layer 205 is filled in the contact hole, and the second dielectric layer 205 on the surface of the phase change material stabilizing layer 204 is removed by chemical mechanical polishing, so that the upper surface of the second dielectric layer 205 is flush with the upper surface of the phase change material stabilizing layer 204. The lower surface of the second dielectric layer 205 is connected to the bottom electrode 203, and the lateral dimension of the second dielectric layer 205 is smaller than the lateral dimension of the bottom electrode 203.
Step S14: a third dielectric layer 206 is formed over phase change material stabilization layer 204.
As shown in fig. 10, the material of the third dielectric layer 206 is deposited first, and then the phase change material stabilizing layer 204 and the third dielectric layer 206 are patterned by photolithography and etching processes, so that the lateral dimension of the third dielectric layer 206 is equal to the lateral dimension of the outer side of the phase change material stabilizing layer 204, and the lateral dimension of the outer side of the phase change material stabilizing layer 204 is larger than the lateral dimension of the bottom electrode 203.
Step S15: a phase change material layer 207 and a fourth dielectric layer 208 are formed on both sides of the phase change material stabilization layer 204 and the third dielectric layer 206.
As shown in fig. 11, materials of the phase change material layer 207 and the fourth medium layer 208 are deposited on the third medium layer 206, and then the materials of the phase change material layer 207 and the fourth medium layer 208 on the third medium layer 206 and part of the surface materials of the third medium layer 206 are removed by chemical mechanical polishing, and the phase change material layer 207 and the fourth medium layer 208 are formed only on two sides of the two phase change material stabilizing layers 204 and the third medium layer 206, so that the upper surface of the phase change material layer 207 is flush with the upper surfaces of the third medium layer 206 and the fourth medium layer 207. In this embodiment, the phase change material may be TaSbTe.
Step S16: a top electrode 209 is formed on the phase change material layer 207.
As shown in fig. 12, the metal of the top electrode 209 is deposited first, and two top electrodes 209 are formed by photolithography and etching processes, so that the two top electrodes 209 are respectively connected with the two phase change material layers 207 on two sides of the phase change material stabilizing layer 204, thereby forming a 2R structure.
In this embodiment, the phase change material stabilizing layer 204 divides the phase change material layer 207 into left and right 2 regions to form a 2R structure, which effectively reduces the size of a single phase change cell and improves the integration density of the phase change cell. In order to avoid the problem of thermal crosstalk of the phase change units on the left and right sides caused by the heat generation of the phase change material stabilizing layer 204, a second dielectric layer 205 is added in the middle of the phase change material stabilizing layer 204, so that better thermal isolation is performed. In addition, due to the reduction of the overall volume of the phase change material stabilization layer 204, the heat requirement can be effectively reduced, and the power consumption of the device can be reduced.
Example III
Please refer to fig. 18. In this embodiment, a first dielectric layer 302 is disposed on a substrate 301, and a bottom electrode 303 is disposed in the first dielectric layer 302; and, the lower surface of the bottom electrode 303 is connected to the upper surface of the substrate 301. The bottom electrode 303 is disposed below the phase change material stabilizing layers 304 and 305, and the upper surface of the bottom electrode 303 is connected to the lower surfaces of the phase change material stabilizing layers 304 and 305.
The phase change material stabilization layer 304, 305 is divided in the horizontal direction by a second dielectric layer 306 into two phase change material stabilization layers 304, 305 that are separated, the two phase change material stabilization layers 304, 305 each being connected to one phase change material layer 308 located on the corresponding side.
The difference from the second embodiment is that in this embodiment, each phase change material stabilization layer 304, 305 includes a first phase change material stabilization layer 304 and a second phase change material stabilization layer 305; the first phase change material stabilization layer 304 and the second phase change material stabilization layer 305 are disposed from outside to inside, and the sides of the first phase change material stabilization layer 304 and the second phase change material stabilization layer 305 are connected. The upper surface of the bottom electrode 303 is connected to the lower surfaces of the first phase change material stabilization layer 304 and the second phase change material stabilization layer 305 at the same time.
The two phase change material layers 308 are disposed on two sides of the two first phase change material stabilizing layers 304, inner sides of the two phase change material layers 308 are respectively connected to outer side surfaces of the two first phase change material stabilizing layers 304, and upper surfaces of the two phase change material layers 308 are respectively connected to a lower surface of a top electrode 310 disposed on an upper layer thereof.
Meanwhile, the lateral dimensions occupied by the two first phase change material stabilizing layers 304 and the second phase change material stabilizing layer 305 are larger than the lateral dimensions of the bottom electrode 303, that is, the bottom electrode 303 is located at a region within the outer boundaries of the two first phase change material stabilizing layers 304 at the same time, and is located at a region outside the outer boundaries of the two second phase change material stabilizing layers 305. Other aspects of this embodiment regarding the phase change memory cell may be understood and utilized with reference to embodiment one and embodiment two.
A method for manufacturing a phase change memory cell according to the third embodiment of the present invention will be described in detail with reference to the accompanying drawings.
Please refer to fig. 13-18. The preparation method of the phase change memory unit in the third embodiment of the invention comprises the following steps:
Step S21: on a semiconductor substrate 301, a bottom electrode 303 and a first dielectric layer 302 are formed as shown in fig. 13. In this embodiment, the substrate 301 of the copper interconnect layer may be used, the first dielectric layer 302 may be a second generation Black diamond (bd2) material, and the bottom electrode 303 may be a copper electrode.
Step S22: a first phase change material stabilization layer 304 is formed on the bottom electrode 303.
As shown in fig. 14, a first phase change material stabilization layer 304 material is deposited on bottom electrode 303. The first phase change material stabilization layer 304 is in communication with the bottom electrode 303. In this embodiment, the first phase change material stabilization layer 304 may be NiSi. NiSi has thermal instability, and when the temperature is higher than 400 ℃, a stable compound NiSi 2 is formed, and in the process, ni can diffuse into the phase change material layer to react with Te to form NiTe, so that the Te element in the phase change material layer can be fixed.
Step S23: a second phase change material stabilization layer 305 and a second dielectric layer 306 are formed in-between the first phase change material stabilization layer 304.
As shown in fig. 15, the first phase change material stabilizing layer 304 is subjected to photolithography and etching, a contact hole is formed above the bottom electrode 303, materials of the second phase change material stabilizing layer 305 and the second dielectric layer 306 are sequentially filled in the contact hole, and the materials of the second phase change material stabilizing layer 305 and the second dielectric layer 306 on the surface of the first phase change material stabilizing layer 304 are removed by chemical mechanical polishing, so that the upper surfaces of the second phase change material stabilizing layer 305 and the second dielectric layer 306 are flush with the upper surface of the first phase change material stabilizing layer 304, the lower surface of the second dielectric layer 306 is connected with the upper surface of the bottom electrode 303, and the lateral dimension of the second dielectric layer 306 is smaller than the lateral dimension of the bottom electrode 303.
The second phase change material stabilization layer 305 is selected from materials that have a higher thermal conductivity and a lower electrical resistivity than the first phase change material stabilization layer 304, and are chemically more stable at high temperatures. In this embodiment, the second phase change material stabilization layer 305 material may be a transition metal carbide tungsten carbide (WC) that has higher thermal conductivity and lower resistivity than the first phase change material stabilization layer 304 material NiSi and is chemically more stable at high temperatures.
Step S24: a third dielectric layer 307 is formed over the first phase change material stabilization layer 304.
As shown in fig. 16, a third dielectric layer 307 is deposited, and then a first phase change material stabilizing layer 304, a second phase change material stabilizing layer 305 and a third dielectric layer 307 are patterned by photolithography and etching processes, so that the lateral dimension of the third dielectric layer 307 is equal to the lateral dimension between the outer sides of the first phase change material stabilizing layer 304, and the lateral dimension between the outer sides of the first phase change material stabilizing layer 304 is larger than the lateral dimension of the bottom electrode 303.
Step S25: a phase change material layer 308 and a fourth dielectric layer 309 are formed on both sides of the first phase change material stabilization layer 304 and the third dielectric layer 307.
As shown in fig. 17, materials of the phase change material layer 308 and the fourth dielectric layer 309 are deposited on the third dielectric layer 307, and then the materials of the phase change material layer 308 and the fourth dielectric layer 309 on the third dielectric layer 307 and part of the surface materials of the third dielectric layer 307 are removed by chemical mechanical polishing, and the phase change material layer 308 and the fourth dielectric layer 309 are formed only on two sides of the first phase change material stabilizing layer 304 and the third dielectric layer 307, so that the upper surfaces of the phase change material layer 308 and the fourth dielectric layer 309 are flush with the upper surface of the third dielectric layer 307. In this embodiment, the phase change material may be TiSbTe.
Step S26: a top electrode 310 is formed on the phase change material layer 308.
As shown in fig. 18, the top electrode 310 is deposited with metal, and two top electrodes 310 are formed by photolithography and etching processes, so that the two top electrodes 310 are respectively connected to the two phase change material layers 308 on both sides of the two first phase change material stabilization layers 304, and a 2R structure is formed.
In this embodiment, in order to further improve the heating efficiency of the phase change material, the phase change material stabilizing layers 304 and 305 are divided into 2 materials, wherein the first phase change material stabilizing layer 304 connected to the phase change material layer 308 can react with the phase change material, and the second phase change material stabilizing layer 305 connected to the bottom electrode 303 has higher thermal conductivity and smaller electrical resistivity than the first phase change material stabilizing layer 304, and has more stable chemical properties at high temperature, which can effectively improve the heating efficiency of the phase change material, and reduce the power consumption of the phase change unit.
The preparation method and the preparation process are simpler, are compatible with the existing standard CMOS process, and are easy for mass production.
The foregoing description is only of the preferred embodiments of the present invention, and the embodiments are not intended to limit the scope of the invention, so that all changes made in the equivalent structures of the description and drawings of the invention are included in the scope of the invention.
Claims (13)
1. The phase change memory cell is characterized by comprising a bottom electrode, a phase change material stabilizing layer, a phase change material layer and a top electrode which are connected in sequence; the phase change material stabilizing layer has conductivity, and the phase change material stabilizing layer and the phase change material layer react at an interface at a certain temperature so as to avoid failure caused by separation of elements in the phase change material layer; the bottom electrode is arranged on the lower layer of the phase change material stabilizing layer, and the two phase change material layers are respectively arranged on two sides of the phase change material stabilizing layer and are respectively connected with one top electrode arranged on the upper layer of the phase change material stabilizing layer; the phase change material stabilizing layers are two phase change material stabilizing layers which are isolated in the horizontal direction, and the two phase change material stabilizing layers are respectively connected with one phase change material layer positioned on the corresponding side; the phase change material stabilization layer includes at least one of a transition metal carbide and a metal silicide; the boundary of the phase change material stabilization layer exceeds the boundary of the bottom electrode.
2. The phase change memory cell of claim 1, wherein each of the phase change material stabilization layers comprises a first phase change material stabilization layer and a second phase change material stabilization layer connected from the outside in, the bottom electrode being connected to both the first phase change material stabilization layer and the second phase change material stabilization layer.
3. The phase change memory cell of claim 2, wherein the second phase change material stabilization layer has a higher thermal conductivity, a lower resistivity, and a chemistry that is more stable at the temperature than the first phase change material stabilization layer.
4. The phase change memory cell of claim 1, wherein the phase change material stabilization layer comprises at least one of SiC, WN, tiAlN, taAlN, tiSiN and TaSiN.
5. The phase change memory cell of claim 1, wherein the temperature range comprises 600-800 ℃.
6. A method of fabricating a phase change memory cell, comprising the steps of:
step S01: forming a bottom electrode and first dielectric layers positioned on two sides of the bottom electrode on a semiconductor substrate;
step S02: sequentially forming a phase change material stabilizing layer and a second dielectric layer on the surface of the bottom electrode; the phase change material stabilization layer includes at least one of a transition metal carbide and a metal silicide; the boundary of the phase change material stabilizing layer exceeds the boundary of the bottom electrode;
step S03: sequentially forming a phase change material layer and a third medium layer on the two side surfaces of the phase change material stabilizing layer and the second medium layer;
step S04: and forming a top electrode on the surfaces of the phase change material layers at two sides respectively.
7. The method of fabricating a phase change memory cell according to claim 6, wherein in step S02, the phase change material stabilization layer covers the bottom electrode therein in a vertical projection direction; in step S03, the upper surface of the phase change material layer is flush with the upper surface of the second dielectric layer and the upper surface of the third dielectric layer.
8. A method of fabricating a phase change memory cell, comprising the steps of:
step S11: forming a bottom electrode and first dielectric layers positioned on two sides of the bottom electrode on a semiconductor substrate;
Step S12: covering a phase change material stabilizing layer on the bottom electrode and the first dielectric layer; the phase change material stabilization layer includes at least one of a transition metal carbide and a metal silicide; the boundary of the phase change material stabilizing layer exceeds the boundary of the bottom electrode;
step S13: forming a second dielectric layer in the phase change material stabilizing layer corresponding to the bottom electrode, so as to form one phase change material stabilizing layer on two sides of the second dielectric layer respectively;
Step S14: forming a third dielectric layer on the phase change material stabilizing layer and the second dielectric layer;
Step S15: sequentially forming a phase change material layer and a fourth medium layer on the surfaces of the two sides of the phase change material stabilizing layer and the third medium layer;
step S16: and forming a top electrode on the surfaces of the phase change material layers at two sides respectively.
9. The method of manufacturing a phase change memory cell according to claim 8, wherein in step S13, an upper surface of the second dielectric layer is flush with an upper surface of the phase change material stabilization layer, a lower surface of the second dielectric layer is connected to an upper surface of the bottom electrode, and the second dielectric layer falls within the bottom electrode in a vertical projection direction; in step S14, the side surface of the third dielectric layer is flush with the side surface of the phase change material stabilizing layer, and the bottom electrode is covered in the outside of the phase change material stabilizing layer in the vertical projection direction; in step S15, the upper surface of the phase change material layer is flush with the upper surfaces of the third dielectric layer and the fourth dielectric layer.
10. A method of fabricating a phase change memory cell, comprising the steps of:
Step S21: forming a bottom electrode and first dielectric layers positioned on two sides of the bottom electrode on a semiconductor substrate;
Step S22: covering a first phase change material stabilizing layer on the bottom electrode and the first dielectric layer; the phase change material stabilization layer includes at least one of a transition metal carbide and a metal silicide; the boundary of the phase change material stabilizing layer exceeds the boundary of the bottom electrode;
Step S23: forming a second dielectric layer in the first phase change material stabilizing layer corresponding to the bottom electrode, and forming second phase change material stabilizing layers between two sides of the second dielectric layer and the first phase change material stabilizing layer respectively, so that one second phase change material stabilizing layer and one first phase change material stabilizing layer are formed on two sides of the second dielectric layer respectively;
step S24: forming a third dielectric layer on the first phase change material stabilizing layer, the second phase change material stabilizing layer and the second dielectric layer;
Step S25: sequentially forming a phase change material layer and a fourth medium layer on the surfaces of the two sides of the first phase change material stabilizing layer and the third medium layer;
step S26: and forming a top electrode on the surfaces of the phase change material layers at two sides respectively.
11. The method of fabricating a phase change memory cell according to claim 10, wherein in step S23, the upper surface of the second dielectric layer is flush with the upper surfaces of the second phase change material stabilization layer and the first phase change material stabilization layer, the lower surface of the second dielectric layer is connected to the upper surface of the bottom electrode, and the second dielectric layer falls within the bottom electrode in a vertical projection direction; in step S24, the side surface of the third dielectric layer is flush with the side surface of the first phase change material stabilizing layer, and the bottom electrode is covered in the outside of the first phase change material stabilizing layer in the vertical projection direction; in step S25, the upper surface of the phase change material layer is flush with the upper surfaces of the third dielectric layer and the fourth dielectric layer.
12. The method of claim 11, wherein the second phase change material stabilization layer has a higher thermal conductivity, a lower resistivity, and a more stable chemistry at a temperature than the first phase change material stabilization layer.
13. The method of claim 12, wherein the temperature range comprises 600-800 ℃.
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| EP1923928A2 (en) * | 2006-11-17 | 2008-05-21 | Qimonda North America Corp. | Phase change memory cell having a sidewall contact |
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