CN111769195A - Phase change memory unit and preparation method thereof - Google Patents
Phase change memory unit and preparation method thereof Download PDFInfo
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- 230000008859 change Effects 0.000 title claims abstract description 73
- 238000002360 preparation method Methods 0.000 title abstract description 7
- 239000012782 phase change material Substances 0.000 claims abstract description 325
- 230000000087 stabilizing effect Effects 0.000 claims abstract description 80
- 238000000034 method Methods 0.000 claims abstract description 37
- 238000000926 separation method Methods 0.000 claims abstract description 10
- 230000006641 stabilisation Effects 0.000 claims description 102
- 238000011105 stabilization Methods 0.000 claims description 102
- 239000000758 substrate Substances 0.000 claims description 29
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 8
- 229910004491 TaAlN Inorganic materials 0.000 claims description 7
- 229910021332 silicide Inorganic materials 0.000 claims description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 6
- 229910052723 transition metal Inorganic materials 0.000 claims description 6
- 150000003624 transition metals Chemical class 0.000 claims description 6
- 229910004200 TaSiN Inorganic materials 0.000 claims description 5
- 229910010037 TiAlN Inorganic materials 0.000 claims description 5
- 229910008482 TiSiN Inorganic materials 0.000 claims description 5
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 claims description 5
- 230000008569 process Effects 0.000 abstract description 15
- 230000010354 integration Effects 0.000 abstract description 7
- 238000011031 large-scale manufacturing process Methods 0.000 abstract description 2
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- 239000000126 substance Substances 0.000 description 7
- 238000006243 chemical reaction Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000003860 storage Methods 0.000 description 6
- 229910052787 antimony Inorganic materials 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
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- 238000005516 engineering process Methods 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
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- 239000010949 copper Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
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- 229910005913 NiTe Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
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- 229910052782 aluminium Inorganic materials 0.000 description 1
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
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Abstract
The invention discloses a phase change memory unit, which comprises a bottom electrode, a phase change material stabilizing layer, a phase change material layer and a top electrode which are connected in sequence; the phase change material stabilizing layer has conductivity, and the phase change material stabilizing layer and the phase change material layer react at an interface at a certain temperature to avoid phase change unit failure caused by separation of elements in the phase change material layer. Meanwhile, the phase change material stabilizing layer divides the phase change material layer into a left area and a right area, a 2R structure is formed, and the integration density of the phase change unit can be improved. The invention also discloses a preparation method of the phase change memory unit, which has simpler process, can be compatible with the existing standard CMOS process and is easy for large-scale production.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuit manufacturing processes, in particular to a phase change memory unit with high reliability and high integration density and a preparation method thereof.
Background
With the emergence of a series of novel information technologies such as big data, internet of things, cloud computing and artificial intelligence, the requirements of high read-write speed, low power consumption, high storage density, long service life, high reliability and the like are provided for the memory.
At present, the storage modes of the memory are mainly DRAM and Flash. The NAND Flash has high integration level and low cost, but has slow speed and short service life; although DRAM is fast and has a long lifetime, it loses data after power is lost, and it is costly. Therefore, a new storage technology has been developed and is a research focus in recent years in the industry, and the new storage technology needs to have the advantages of both DRAM and NAND Flash, i.e., the read/write speed is comparable to that of DRAM, and the cost and the non-volatility are similar to that of NAND Flash, while the phase change memory is one of the new storage technologies. In recent years, the phase change memory unit has a wide prospect in the application of an artificial intelligence and storage and computation integrated chip.
Please refer to fig. 1. A conventional phase change memory cell is composed of, from bottom to top, a bottom electrode, a phase change material, and a top electrode disposed on a substrate. Wherein the mushroom-shaped dashed area in the phase change material shown near the bottom electrode represents a reversible phase change region in which the phase change material can be reversibly switched between the amorphous and crystalline states under operation of an electrical pulse.
As shown in fig. 2, during the repeated operation of the phase-change region, especially when the phase-change region is transformed from the crystalline state to the amorphous state (at a temperature of about 500-. Thus, the loss of antimony near the anode can form mobile nanovoids that eventually accumulate at the interface with the anode, causing a break at the interface between the phase change material layer and the upper electrode, resulting in device failure.
Therefore, how to prevent the phase change cell from failing due to the separation of elements in the phase change material layer and to prepare a phase change memory cell with high reliability is a technical problem to be solved urgently in the industry.
Disclosure of Invention
The present invention is directed to overcoming the above-mentioned drawbacks of the prior art and providing a phase change memory cell and a method for fabricating the same.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a phase change memory unit comprises a bottom electrode, a phase change material stabilizing layer, a phase change material layer and a top electrode which are connected in sequence; the phase-change material stable layer has conductivity, and the phase-change material stable layer and the phase-change material layer react at an interface at a certain temperature to avoid failure caused by separation of elements in the phase-change material layer.
Furthermore, the bottom electrode is arranged on the lower layer of the phase change material stable layer, and the two phase change material layers are respectively arranged on two sides of the phase change material stable layer and are respectively connected with the top electrode on the upper layer.
Furthermore, the phase change material stabilizing layers are two phase change material stabilizing layers which are separated in the horizontal direction, and the two phase change material stabilizing layers are respectively connected with one phase change material layer positioned on the corresponding side.
Furthermore, each phase change material stabilizing layer comprises a first phase change material stabilizing layer and a second phase change material stabilizing layer which are connected from outside to inside, and the bottom electrode is connected with the first phase change material stabilizing layer and the second phase change material stabilizing layer simultaneously.
Further, the phase change material stabilization layer includes at least one of a transition metal carbide and a metal silicide.
Further, the phase change material stable layer comprises at least one of SiC, WN, TiAlN, TaAlN, TiSiN and TaSiN.
A method for preparing a phase change memory cell, comprising the steps of:
step S01: forming a bottom electrode and first dielectric layers positioned on two sides of the bottom electrode on a semiconductor substrate;
step S02: sequentially forming a phase change material stabilizing layer and a second dielectric layer on the surface of the bottom electrode;
step S03: sequentially forming a phase change material layer and a third dielectric layer on the surfaces of the two sides of the phase change material stabilizing layer and the second dielectric layer;
step S04: and respectively forming a top electrode on the surfaces of the phase change material layers on the two sides.
Further, in step S02, the phase change material stable layer covers the bottom electrode in the vertical projection direction; in step S03, the upper surface of the phase change material layer is flush with the upper surfaces of the second dielectric layer and the third dielectric layer.
A method for preparing a phase change memory cell, comprising the steps of:
step S11: forming a bottom electrode and first dielectric layers positioned on two sides of the bottom electrode on a semiconductor substrate;
step S12: covering a phase change material stabilizing layer on the bottom electrode and the first dielectric layer;
step S13: forming a second dielectric layer in the phase change material stabilizing layer corresponding to the inner part of the bottom electrode, so that the phase change material stabilizing layers are respectively formed on two sides of the second dielectric layer;
step S14: forming a third dielectric layer on the phase-change material stabilizing layer and the second dielectric layer;
step S15: sequentially forming a phase change material layer and a fourth medium layer on the surfaces of the two sides of the phase change material stabilizing layer and the third medium layer;
step S16: and respectively forming a top electrode on the surfaces of the phase change material layers on the two sides.
Further, in step S13, the upper surface of the second dielectric layer is flush with the upper surface of the phase change material stabilization layer, the lower surface of the second dielectric layer is connected to the upper surface of the bottom electrode, and the second dielectric layer falls within the bottom electrode in the vertical projection direction; in step S14, a side surface of the third dielectric layer is flush with a side surface of the phase-change material stabilizing layer, and the bottom electrode is covered by an outer side of the phase-change material stabilizing layer in a vertical projection direction; in step S15, the upper surface of the phase change material layer is flush with the upper surfaces of the third dielectric layer and the fourth dielectric layer.
A method for preparing a phase change memory cell, comprising the steps of:
step S21: forming a bottom electrode and first dielectric layers positioned on two sides of the bottom electrode on a semiconductor substrate;
step S22: covering a first phase change material stabilizing layer on the bottom electrode and the first dielectric layer;
step S23: forming a second medium layer in the first phase-change material stabilizing layer corresponding to the inner part of the bottom electrode, and forming second phase-change material stabilizing layers between two sides of the second medium layer and the first phase-change material stabilizing layer respectively, so as to form the second phase-change material stabilizing layer and the first phase-change material stabilizing layer on two sides of the second medium layer respectively;
step S24: forming a third dielectric layer on the first phase change material stabilization layer, the second phase change material stabilization layer and the second dielectric layer;
step S25: sequentially forming a phase change material layer and a fourth medium layer on the surfaces of the two sides of the first phase change material stabilizing layer and the third medium layer;
step S26: and respectively forming a top electrode on the surfaces of the phase change material layers on the two sides.
Further, in step S23, the upper surface of the second dielectric layer is flush with the upper surfaces of the second phase-change material stabilizing layer and the first phase-change material stabilizing layer, the lower surface of the second dielectric layer is connected to the upper surface of the bottom electrode, and the second dielectric layer falls within the bottom electrode in the vertical projection direction; in step S24, a side surface of the third dielectric layer is flush with a side surface of the first phase change material stabilization layer, and the bottom electrode is covered by an outer side of the first phase change material stabilization layer in a vertical projection direction; in step S25, the upper surface of the phase change material layer is flush with the upper surfaces of the third dielectric layer and the fourth dielectric layer.
Further, the second phase change material stabilization layer has a higher thermal conductivity, a lower electrical resistivity, and a more stable chemistry at a temperature than the first phase change stabilization layer.
Further, the temperature range includes 600-.
According to the technical scheme, the phase change memory unit is provided with the phase change material stabilizing layer between the bottom electrode and the phase change material layer, and the phase change memory unit can be prevented from losing efficacy caused by element separation in the phase change material by utilizing the mechanism that the phase change material stabilizing layer can react with the phase change material layer at an interface (for example, elements in the phase change material stabilizing layer can chemically bond with elements in the phase change material layer such as Sb and Te, or elements in the phase change material stabilizing layer can cover the grain interface in the phase change material layer, and the like), so that the normal phase change conversion of the phase change material layer can not be influenced, and the reliability of the phase change memory unit is improved. The invention has the following advantages:
(1) the phase change material stabilizing layer is adopted to divide the phase change material layer into a left area and a right area, so that a 2R structure is formed, and the integration density of the phase change unit can be improved.
(2) By adding the dielectric layer in the middle of the phase-change material stabilizing layer, better thermal isolation can be performed, and thermal crosstalk of the phase-change units on the left side and the right side caused by heating of the phase-change material stabilizing layer is avoided; and due to the reduction of the volume of the phase-change material stabilizing layer, the heat requirement can be effectively reduced, and the power consumption of the device is reduced.
(3) In order to improve the heating efficiency of the phase change material, the phase change material stable layer can be further divided into 2 materials (a first phase change material stable layer and a second phase change material stable layer); the first phase-change material stable layer connected with the phase-change material layer can react with the phase-change material, and the second phase-change material stable layer connected with the bottom electrode has higher heat conductivity and smaller resistivity than the first phase-change material stable layer, so that the chemical property is more stable at high temperature, the heating efficiency of the phase-change material can be effectively improved, and the power consumption of the phase-change unit is reduced.
(4) The preparation method and the process of the invention are simpler, can be compatible with the existing standard CMOS process, and are easy for mass production.
Drawings
Fig. 1 is a schematic diagram of a conventional phase change memory cell structure.
FIG. 2 is a schematic diagram illustrating element separation of a phase change material layer in a conventional phase change cell.
Fig. 3-6 are schematic diagrams of process steps for fabricating a phase change memory cell according to a first embodiment of the invention.
Fig. 7-12 are schematic diagrams of process steps for fabricating a phase change memory cell according to a second embodiment of the present invention.
Fig. 13-18 are schematic diagrams of process steps for fabricating a phase change memory cell according to a third embodiment of the present invention.
Detailed Description
The core idea of the invention is that the invention provides a phase change memory unit and a preparation method thereof. The invention relates to a phase change memory unit, which comprises a bottom electrode, a phase change material stabilizing layer, a phase change material layer and a top electrode which are connected in sequence; the phase change material stable layer has conductivity, and the phase change material stable layer and the phase change material layer react at an interface at a certain temperature, so that the problem of phase change unit failure caused by separation of elements in the phase change material layer can be avoided, and a phase change memory unit with high reliability and high integration density can be prepared by a simple method which is compatible with the existing standard CMOS process.
The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.
In the following detailed description of the embodiments of the present invention, in order to clearly illustrate the structure of the present invention and to facilitate explanation, the structure shown in the drawings is not drawn to a general scale and is partially enlarged, deformed and simplified, so that the present invention should not be construed as limited thereto.
Example one
In the following description of the present invention, please refer to fig. 6, fig. 6 is a schematic diagram of a phase change memory cell structure according to the present invention. As shown in fig. 6, the phase change memory cell is provided on a substrate 101. The substrate 101 may include a semiconductor material such as a silicon substrate, a gallium arsenide substrate, a germanium substrate, a silicon germanium substrate, or a fully depleted silicon-on-insulator (FDSOI) substrate, etc. The substrate may also be an integrated circuit, including an integrated circuit with gate transistors such as transistors, diodes, etc. The substrate may also be an interconnect layer, such as a copper interconnect layer, a graphene interconnect layer, or the like.
Please refer to fig. 6. In this embodiment, a first dielectric layer 102 is disposed on a substrate 101, and a bottom electrode 103 is disposed in the first dielectric layer 102; and, the lower surface of the bottom electrode 103 is connected to the upper surface of the substrate 101. The bottom electrode 103 is disposed below the phase change material stabilization layer 104, and an upper surface of the bottom electrode 103 is connected to a lower surface of the phase change material stabilization layer 104. Meanwhile, the lateral dimension of the phase change material stabilization layer 104 is larger than the lateral dimension of the bottom electrode 103, i.e. the bottom electrode 103 is located in a region within the lateral dimension boundary of the phase change material stabilization layer 104.
The number of the phase change material layers 106 is two, and the two phase change material layers are respectively disposed on two sides of the phase change material stabilizing layer 104, inner sides of the two phase change material layers 106 are respectively connected to two side surfaces of the phase change material stabilizing layer 104, and upper surfaces of the two phase change material layers 106 are respectively connected to a lower surface of a top electrode 108 disposed thereon.
The phase change material stabilization layer 104 includes at least one of a transition metal carbide and a metal silicide.
Further, the phase change material stabilization layer 104 includes at least one of SiC, WN, TiAlN, TaAlN, TiSiN, and TaSiN.
The phase change material stabilization layer 104 can react with the phase change material layer 106 at an interface at a certain temperature, preferably, within a temperature range of 600-.
The chemical bonds of the transition metal carbide include metallic, covalent and ionic bonds. Thus, at high temperature (600-. The metal silicide can form a high-resistance intermediate phase at about 600 ℃, and when the temperature is further increased, phase transformation occurs to form a final phase of a low-resistance state. Therefore, at 600-800 ℃, the metal silicide can react with the phase change material while the phase change occurs. Thus, the phase change material stabilization layer 104 includes at least one of a transition metal carbide and a metal silicide. In addition, in order to prevent the contamination risk caused by introducing new elements, the phase-change material stable layer material comprises the elements existing in the existing CMOS process.
Materials such as SiC, WN, TiAlN, TaAlN, TiSiN and TaSiN also have good conductivity and lower resistivity. Can react with the phase-change material at a certain temperature. The SiC and WN have the characteristics of excellent heat conductivity and high pressure resistance, and are suitable for preparing phase change memory units for high pressure application. The TiAlN, TaAlN, TiSiN and TaSiN materials react with the phase change material, so that metal elements are diffused into the phase change material layer and coated on the grain interface of the phase change material, and grains of the phase change material are refined, so that elements such as Sb and Te in the phase change material are fixed, phase change unit failure caused by element separation in the phase change material is avoided, normal phase change conversion of the phase change material layer is not influenced, and the reliability of the phase change memory unit is improved.
The following describes a method for manufacturing a phase change memory cell according to the above embodiment of the present invention in detail with reference to the accompanying drawings.
Please refer to fig. 3-6. The method for manufacturing a phase change memory cell according to the above embodiment of the present invention includes the following steps:
step S01: on a semiconductor substrate 101, a bottom electrode and a first dielectric layer 102 are formed.
In the present embodiment, as shown in fig. 3, a silicon substrate 101 may be used, a first dielectric layer 102 is deposited on the silicon substrate 101, and a bottom electrode 103 is formed in the first dielectric layer 102. The bottom electrode 103 may be, for example, a tungsten electrode.
Step S02: a phase change material stabilization layer 104 and a second dielectric layer 105 are formed on the bottom electrode 103.
As shown in fig. 4, a phase change material stabilization layer and a second dielectric layer material are sequentially deposited on the surfaces of the bottom electrode and the first dielectric layer, and then patterns of the phase change material stabilization layer 104 and the second dielectric layer 105 are formed by photolithography and etching processes.
Wherein the lateral dimension of the phase change material stabilization layer 104 is larger than the lateral dimension of the bottom electrode 103. In the present embodiment, the phase change material stabilization layer 104 may be TaAlN.
When the temperature is 600-800 ℃, Al in the TaAlN diffuses into the phase change material layer and is coated at the grain interface of the phase change material to refine the grains of the phase change material, so that elements such as Sb and Te in the phase change material are fixed, the phase change unit failure caused by element separation in the phase change material is avoided, the normal phase change conversion of the phase change material layer is not influenced, and the reliability of the phase change memory unit is improved.
Step S03: a phase change material layer 106 and a third dielectric layer 107 are formed on both sides of the phase change material stabilization layer 104 and the second dielectric layer 105.
As shown in fig. 5, the phase change material layer 106 and the third dielectric layer 107 are deposited on the second dielectric layer 105, and then the phase change material layer 106 and the third dielectric layer 107 on the surface of the second dielectric layer 105 are removed and a portion of the material of the second dielectric layer 105 is removed, so that the phase change material layer 106 and the third dielectric layer 107 are formed only on two sides of the phase change material stabilization layer 104 and the second dielectric layer 105.
The upper surface of the phase change material layer 106 is flush with the upper surfaces of the second dielectric layer 105 and the third dielectric layer 107.
In the present embodiment, the phase change material layer 106 may be Ge2Sb2Te 5.
Step S04: a top electrode 108 is formed on the phase change material layer 106.
As shown in fig. 6, a top electrode 108 film is deposited on the surface of the device structure formed as above, and two top electrodes 108 are formed through photolithography and etching processes, and the top electrodes 108 are respectively connected with the upper surfaces of the phase change material layers 106 on both sides of the phase change material stable layer 104, so as to form a 2R structure.
In the first embodiment, the phase change material stabilization layer 104 can react with the phase change material layer 106 at the interface. The phase change material stabilization layer 104 is located between the bottom electrode 103 and the phase change material layer 106, and reacts with the phase change material layer 106 at the interface, including a chemical reaction: the elements in the phase-change material stable layer 104 can chemically bond with the elements in the phase-change material layer 106, such as Sb, Te, etc.; alternatively, the elements in the phase change material stabilization layer 104 may be wrapped at grain boundaries in the phase change material layer 106, and so on. These reactions can avoid phase change unit failure caused by element separation in the phase change material, but will not affect normal phase change conversion of the phase change material layer, thereby improving the reliability of the phase change memory unit. Meanwhile, the phase change material stabilizing layer 104 divides the phase change material layer 106 into a left area and a right area, so that a 2R structure is formed, and the integration density of the phase change unit can be improved.
Example two
Please refer to fig. 12. In this embodiment, a first dielectric layer 202 is disposed on a substrate 201, and a bottom electrode 203 is disposed in the first dielectric layer 202; and, the lower surface of the bottom electrode 203 is connected to the upper surface of the substrate 201. The bottom electrode 203 is disposed below the phase change material stabilization layer 204, and an upper surface of the bottom electrode 203 is connected to a lower surface of the phase change material stabilization layer 204.
The number of the phase change material layers 207 is two, and the two phase change material layers are respectively disposed on two sides of the phase change material stabilizing layer 204, inner sides of the two phase change material layers 207 are respectively connected to two side surfaces of the phase change material stabilizing layer 204, and upper surfaces of the two phase change material layers 207 are respectively connected to a lower surface of a top electrode 209 disposed thereon.
The difference from the first embodiment is that in this embodiment, the phase change material stabilization layer 204 is divided into two phase change material stabilization layers 204 separated by the second dielectric layer 205 in the horizontal direction, and each of the two phase change material stabilization layers 204 is connected to one phase change material layer 207 on the corresponding side.
Meanwhile, the two phase change material stabilization layers 204 together occupy a lateral dimension that is larger than the lateral dimension of the bottom electrode 203, i.e., the bottom electrode 203 is located in a region within the outer boundaries of the two phase change material stabilization layers 204 at the same time. Other aspects of the present invention, as to the phase change memory cell, can be understood and appreciated with reference to the first embodiment.
A method for manufacturing a phase change memory cell according to the second embodiment of the present invention is described in detail below with reference to the accompanying drawings.
Please refer to fig. 7-12. The method for manufacturing a phase change memory cell according to the second embodiment of the present invention includes the following steps:
step S11: on a semiconductor substrate 201, a bottom electrode 203 and a first dielectric layer 202 are formed as shown in fig. 7. In this embodiment, a substrate 201 with a PMOS transistor may be used, and the bottom electrode 203 may be a tungsten electrode.
Step S12: a phase change material stabilization layer 204 is formed on the bottom electrode 203.
As shown in fig. 8, a phase change material stabilization layer 204 material is deposited on the bottom electrode 203 and the first dielectric layer 202, such that the phase change material stabilization layer 204 is in communication with the bottom electrode 203. In this embodiment, the phase-change material stabilization layer 204 can be TiSi, and at a high temperature of 600-800 ℃, Ti in the TiSi diffuses into the phase-change material and combines with Te in the phase-change material to form TiTe2Te element in the phase change material can be fixed, and, TiTe2The phase change material has low thermal conductivity and is very helpful for reducing the power consumption of the phase change unit.
Step S13: a second dielectric layer 205 is formed in between the phase change material stabilization layer 204.
As shown in fig. 9, the phase change material stabilizing layer 204 is subjected to photolithography and etching, a contact hole is formed above the bottom electrode 203, a second dielectric layer 205 is filled in the contact hole, and the second dielectric layer 205 on the surface of the phase change material stabilizing layer 204 is removed by chemical mechanical polishing, so that the upper surface of the second dielectric layer 205 is flush with the upper surface of the phase change material stabilizing layer 204. The lower surface of the second dielectric layer 205 is connected to the bottom electrode 203, and the lateral dimension of the second dielectric layer 205 is smaller than the lateral dimension of the bottom electrode 203.
Step S14: a third dielectric layer 206 is formed over the phase change material stabilization layer 204.
As shown in fig. 10, the third dielectric layer 206 is deposited, and then the phase change material stabilization layer 204 and the third dielectric layer 206 are patterned by photolithography and etching processes, so that the lateral dimension of the third dielectric layer 206 is equal to the lateral dimension of the outer side of the phase change material stabilization layer 204, and the lateral dimension of the outer side of the phase change material stabilization layer 204 is larger than the lateral dimension of the bottom electrode 203.
Step S15: a phase change material layer 207 and a fourth dielectric layer 208 are formed on both sides of the phase change material stabilization layer 204 and the third dielectric layer 206.
As shown in fig. 11, phase-change material layer 207 and fourth dielectric layer 208 are deposited on third dielectric layer 206, and then chemical mechanical polishing is performed to remove the materials of phase-change material layer 207 and fourth dielectric layer 208 on third dielectric layer 206 and a portion of the surface material of third dielectric layer 206, and phase-change material layer 207 and fourth dielectric layer 208 are formed only on two sides of two phase-change material stabilizing layers 204 and third dielectric layer 206, so that the upper surface of phase-change material layer 207 is flush with the upper surface of third dielectric layer 206 and the upper surface of fourth dielectric layer 207. In this embodiment, the phase change material may be TaSbTe.
Step S16: a top electrode 209 is formed on the phase change material layer 207.
As shown in fig. 12, a top electrode 209 metal is deposited, and two top electrodes 209 are formed by photolithography and etching processes, so that the two top electrodes 209 are respectively connected to the two phase change material layers 207 on two sides of the phase change material stabilizing layer 204, thereby forming a 2R structure.
In this embodiment, the phase change material stabilizing layer 204 divides the phase change material layer 207 into 2 regions on the left and right to form a 2R structure, which effectively reduces the size of a single phase change unit and improves the integration density of the phase change unit. In addition, in order to avoid the problem of thermal crosstalk between the phase change cells on the left and right sides due to heat generation of the phase change material stabilizing layer 204, a second dielectric layer 205 is added in the middle of the phase change material stabilizing layer 204 for better thermal isolation. In addition, due to the reduction of the total volume of the phase change material stabilization layer 204, the heat requirement can be effectively reduced, and the power consumption of the device can be reduced.
EXAMPLE III
Please refer to fig. 18. In this embodiment, a first dielectric layer 302 is disposed on a substrate 301, and a bottom electrode 303 is disposed in the first dielectric layer 302; and, the lower surface of the bottom electrode 303 is connected to the upper surface of the substrate 301. The bottom electrode 303 is disposed below the phase change material stabilization layers 304, 305, and the upper surface of the bottom electrode 303 is connected to the lower surfaces of the phase change material stabilization layers 304, 305.
The phase change material stabilization layers 304, 305 are horizontally divided by a second dielectric layer 306 into two phase change material stabilization layers 304, 305 that are separated, each phase change material stabilization layer 304, 305 connecting one phase change material layer 308 on the corresponding side.
The difference from the second embodiment is that, in the present embodiment, each phase change material stabilization layer 304, 305 includes a first phase change material stabilization layer 304 and a second phase change material stabilization layer 305; the first phase change material stabilization layer 304 and the second phase change material stabilization layer 305 are disposed from the outside to the inside, and the side surfaces of the first phase change material stabilization layer 304 and the second phase change material stabilization layer 305 are connected. The top surface of the bottom electrode 303 is simultaneously connected to the bottom surfaces of the first phase change material stabilization layer 304 and the second phase change material stabilization layer 305.
The two phase change material layers 308 are respectively disposed on two sides of the two first phase change material stabilization layers 304, inner sides of the two phase change material layers 308 are respectively connected to outer side surfaces of the two first phase change material stabilization layers 304, and upper surfaces of the two phase change material layers 308 are respectively connected to a lower surface of a top electrode 310 located on an upper layer thereof.
Meanwhile, the two first phase change material stabilization layers 304 and the second phase change material stabilization layer 305 jointly occupy a lateral dimension larger than that of the bottom electrode 303, i.e., the bottom electrode 303 is located in a region both within the outer boundaries of the two first phase change material stabilization layers 304 and outside the outer boundaries of the two second phase change material stabilization layers 305. Other aspects of the phase change memory cell of the present embodiment can be understood and utilized with reference to the first embodiment and the second embodiment.
A method for manufacturing a phase change memory cell according to the third embodiment of the present invention is described in detail below with reference to the accompanying drawings.
Please refer to fig. 13-18. The method for manufacturing a phase change memory cell according to the third embodiment of the present invention includes the following steps:
step S21: on a semiconductor substrate 301, a bottom electrode 303 and a first dielectric layer 302 are formed as shown in fig. 13. In this embodiment, a substrate 301 with a copper interconnection layer may be used, the first dielectric layer 302 may be a second generation black diamond (BD 2), and the bottom electrode 303 may be a copper electrode.
Step S22: a first stable layer 304 of phase change material is formed on the bottom electrode 303.
As shown in fig. 14, a first stable layer 304 of phase change material is deposited on the bottom electrode 303. The first phase change material stabilization layer 304 is in communication with the bottom electrode 303. In the present embodiment, the first phase change material stabilization layer 304 may be NiSi. NiSi has thermal instability, and when the temperature is higher than 400 ℃, a stable compound NiSi is formed2In the process, Ni can diffuse into the phase-change material layer to react with Te to form NiTe, which can fix Te in the phase-change material layer.
Step S23: a second phase change material stabilization layer 305 and a second dielectric layer 306 are formed in between the first phase change material stabilization layer 304.
As shown in fig. 15, the first phase change material stabilizing layer 304 is subjected to photolithography and etching, a contact hole is formed above the bottom electrode 303, the second phase change material stabilizing layer 305 and the second dielectric layer 306 are sequentially filled in the contact hole, and the materials of the second phase change material stabilizing layer 305 and the second dielectric layer 306 on the surface of the first phase change material stabilizing layer 304 are removed through chemical mechanical polishing, so that the upper surfaces of the second phase change material stabilizing layer 305 and the second dielectric layer 306 are flush with the upper surface of the first phase change material stabilizing layer 304, the lower surface of the second dielectric layer 306 is connected with the upper surface of the bottom electrode 303, and the transverse dimension of the second dielectric layer 306 is smaller than the transverse dimension of the bottom electrode 303.
The second phase change material stabilization layer 305 is selected from a material that has a higher thermal conductivity and a lower electrical resistivity than the first phase change material stabilization layer 304, and is chemically more stable at high temperatures. In this embodiment, the second phase change material stabilization layer 305 material may be a transition metal carbide tungsten carbide (WC) that has a higher thermal conductivity and a lower electrical resistivity than NiSi, which is the first phase change material stabilization layer 304 material, and is chemically more stable at high temperatures.
Step S24: a third dielectric layer 307 is formed over the first phase change material stabilization layer 304.
As shown in fig. 16, the third dielectric layer 307 is deposited, and then the patterns of the first phase change material stabilization layer 304, the second phase change material stabilization layer 305, and the third dielectric layer 307 are formed by photolithography and etching processes, such that the lateral dimension of the third dielectric layer 307 is equal to the lateral dimension between the outer sides of the first phase change material stabilization layer 304, and the lateral dimension between the outer sides of the first phase change material stabilization layer 304 is greater than the lateral dimension of the bottom electrode 303.
Step S25: a phase change material layer 308 and a fourth dielectric layer 309 are formed on both sides of the first phase change material stabilization layer 304 and the third dielectric layer 307.
As shown in fig. 17, phase change material layers 308 and fourth dielectric layers 309 are deposited on the third dielectric layer 307, and then the materials of the phase change material layers 308 and the fourth dielectric layers 309 on the third dielectric layer 307 and part of the surface material of the third dielectric layer 307 are removed by chemical mechanical polishing, so that the phase change material layers 308 and the fourth dielectric layers 309 are formed only on two sides of the first phase change material stabilization layer 304 and the third dielectric layer 307, and the upper surfaces of the phase change material layers 308 and the fourth dielectric layers 309 are flush with the upper surface of the third dielectric layer 307. In this embodiment, the phase change material may be TiSbTe.
Step S26: a top electrode 310 is formed on the phase change material layer 308.
As shown in fig. 18, a top electrode 310 metal is deposited, and two top electrodes 310 are formed through photolithography and etching processes, so that the two top electrodes 310 are respectively connected to the two phase change material layers 308 on two sides of the two first phase change material stable layers 304, and a 2R structure is formed.
In this embodiment, in order to further improve the heating efficiency of the phase change material, the phase change material stabilizing layers 304 and 305 are divided into 2 types of materials, wherein the first phase change material stabilizing layer 304 connected to the phase change material layer 308 can react with the phase change material, and the second phase change material stabilizing layer 305 connected to the bottom electrode 303 has higher thermal conductivity and smaller resistivity than the first phase change material stabilizing layer 304, and the chemical property is more stable at high temperature, so that the heating efficiency of the phase change material can be effectively improved, and the power consumption of the phase change unit is reduced.
The preparation method and the process of the invention are simpler, compatible with the existing standard CMOS process and easy for large-scale production.
The above description is only for the preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all the equivalent structural changes made by using the contents of the description and the drawings of the present invention should be included in the scope of the present invention.
Claims (16)
1. The phase change memory unit is characterized by comprising a bottom electrode, a phase change material stabilizing layer, a phase change material layer and a top electrode which are sequentially connected; the phase-change material stable layer has conductivity, and the phase-change material stable layer and the phase-change material layer react at an interface at a certain temperature to avoid failure caused by separation of elements in the phase-change material layer.
2. The phase change memory cell of claim 1, wherein the bottom electrode is disposed below the phase change material stabilization layer, and two of the phase change material layers are disposed on opposite sides of the phase change material stabilization layer and respectively connected to one of the top electrodes disposed above the phase change material stabilization layer.
3. The phase change memory cell of claim 2, wherein the phase change material stabilization layers are two separated in a horizontal direction, each connecting one of the phase change material layers on a corresponding side.
4. The phase change memory cell of claim 3, wherein each of the phase change material stabilization layers comprises a first phase change material stabilization layer and a second phase change material stabilization layer connected from outside to inside, and wherein the bottom electrode is connected to both the first phase change material stabilization layer and the second phase change material stabilization layer.
5. The phase change memory cell of claim 4, wherein the second phase change material stabilization layer has a higher thermal conductivity, a lower electrical resistivity, and a more stable chemistry at the temperature than the first phase change stabilization layer.
6. The phase change memory cell of claim 1, wherein the phase change material stabilization layer comprises at least one of a transition metal carbide and a metal silicide.
7. The phase change memory cell of claim 1, wherein the phase change material stabilization layer comprises at least one of SiC, WN, TiAlN, TaAlN, TiSiN, and TaSiN.
8. The phase change memory cell of claim 1, wherein the temperature range comprises 600 ℃ and 800 ℃.
9. A method for manufacturing a phase change memory cell, comprising the steps of:
step S01: forming a bottom electrode and first dielectric layers positioned on two sides of the bottom electrode on a semiconductor substrate;
step S02: sequentially forming a phase change material stabilizing layer and a second dielectric layer on the surface of the bottom electrode;
step S03: sequentially forming a phase change material layer and a third dielectric layer on the surfaces of the two sides of the phase change material stabilizing layer and the second dielectric layer;
step S04: and respectively forming a top electrode on the surfaces of the phase change material layers on the two sides.
10. The method of claim 9, wherein in step S02, the phase-change material stabilization layer covers the bottom electrode in a vertical projection direction; in step S03, the upper surface of the phase change material layer is flush with the upper surfaces of the second dielectric layer and the third dielectric layer.
11. A method for manufacturing a phase change memory cell, comprising the steps of:
step S11: forming a bottom electrode and first dielectric layers positioned on two sides of the bottom electrode on a semiconductor substrate;
step S12: covering a phase change material stabilizing layer on the bottom electrode and the first dielectric layer;
step S13: forming a second dielectric layer in the phase change material stabilizing layer corresponding to the inner part of the bottom electrode, so that the phase change material stabilizing layers are respectively formed on two sides of the second dielectric layer;
step S14: forming a third dielectric layer on the phase-change material stabilizing layer and the second dielectric layer;
step S15: sequentially forming a phase change material layer and a fourth medium layer on the surfaces of the two sides of the phase change material stabilizing layer and the third medium layer;
step S16: and respectively forming a top electrode on the surfaces of the phase change material layers on the two sides.
12. The method of claim 11, wherein in step S13, the upper surface of the second dielectric layer is flush with the upper surface of the phase-change material stabilization layer, the lower surface of the second dielectric layer is connected to the upper surface of the bottom electrode, and the second dielectric layer falls within the bottom electrode in the vertical projection direction; in step S14, a side surface of the third dielectric layer is flush with a side surface of the phase-change material stabilizing layer, and the bottom electrode is covered by an outer side of the phase-change material stabilizing layer in a vertical projection direction; in step S15, the upper surface of the phase change material layer is flush with the upper surfaces of the third dielectric layer and the fourth dielectric layer.
13. A method for manufacturing a phase change memory cell, comprising the steps of:
step S21: forming a bottom electrode and first dielectric layers positioned on two sides of the bottom electrode on a semiconductor substrate;
step S22: covering a first phase change material stabilizing layer on the bottom electrode and the first dielectric layer;
step S23: forming a second medium layer in the first phase-change material stabilizing layer corresponding to the inner part of the bottom electrode, and forming second phase-change material stabilizing layers between two sides of the second medium layer and the first phase-change material stabilizing layer respectively, so as to form the second phase-change material stabilizing layer and the first phase-change material stabilizing layer on two sides of the second medium layer respectively;
step S24: forming a third dielectric layer on the first phase change material stabilization layer, the second phase change material stabilization layer and the second dielectric layer;
step S25: sequentially forming a phase change material layer and a fourth medium layer on the surfaces of the two sides of the first phase change material stabilizing layer and the third medium layer;
step S26: and respectively forming a top electrode on the surfaces of the phase change material layers on the two sides.
14. The method of claim 13, wherein in step S23, the upper surface of the second dielectric layer is flush with the upper surfaces of the second phase-change material stabilization layer and the first phase-change material stabilization layer, the lower surface of the second dielectric layer is connected to the upper surface of the bottom electrode, and the second dielectric layer falls within the bottom electrode in a vertical projection direction; in step S24, a side surface of the third dielectric layer is flush with a side surface of the first phase change material stabilization layer, and the bottom electrode is covered by an outer side of the first phase change material stabilization layer in a vertical projection direction; in step S25, the upper surface of the phase change material layer is flush with the upper surfaces of the third dielectric layer and the fourth dielectric layer.
15. The method of claim 14, wherein the second phase change material stabilization layer has a higher thermal conductivity, a lower electrical resistivity, and a more stable chemistry at temperature than the first phase change stabilization layer.
16. The method as claimed in claim 15, wherein the temperature range comprises 600-800 ℃.
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