CN114864812A

CN114864812A - Phase change memory unit and preparation method thereof

Info

Publication number: CN114864812A
Application number: CN202210325245.6A
Authority: CN
Inventors: 钟旻; 冯高明; 李铭
Original assignee: Shanghai IC R&D Center Co Ltd; Shanghai IC Equipment Material Industry Innovation Center Co Ltd
Current assignee: Shanghai IC R&D Center Co Ltd; Shanghai IC Equipment Material Industry Innovation Center Co Ltd
Priority date: 2022-03-30
Filing date: 2022-03-30
Publication date: 2022-08-05

Abstract

The invention discloses a phase change memory unit and a preparation method thereof, wherein the phase change memory unit comprises the following components from bottom to top: the phase change unit is a longitudinally arranged cylindrical structure, and the cylindrical structure comprises a selection device layer, a barrier layer and a phase change material layer which are sequentially connected from inside to outside; the first electrodes are connected with the phase change material layer respectively, the selection device layer is connected with the second electrode, and the selection device layer comprises a two-dimensional transistor diode layer which is longitudinally arranged. The invention realizes storage by forming a structure that a plurality of phase change resistors share one selection device, and the selection device is formed by adopting the two-dimensional transistor, thereby effectively reducing the power consumption of the device, being compatible with a standard CMOS process line and reducing the production cost.

Description

Phase change memory unit and preparation method thereof

Technical Field

The invention relates to the technical field of semiconductor integrated circuit manufacturing processes, in particular to a phase change memory unit and a preparation method thereof.

Background

Small memory cell size, high performance, and low power consumption have been the continuing goals of memory devices. However, as the process nodes are continuously reduced, the transistors cannot be compatible with some existing embedded memory devices due to the adoption of three-dimensional devices, such as fin field effect transistors. In addition, with the emergence of a series of novel information technologies such as big data, internet of things, cloud computing and artificial intelligence, high computing capacity requirements are also provided for storage devices, but the existing storage devices such as DRAM and NAND flash memory cannot meet the requirements. Therefore, new memory technologies, represented by phase change memories, are increasingly sought after.

Refer to fig. 1. A conventional phase change memory cell, for example, based on the intel 3DX-point technology, is composed of a bottom electrode 01, a selection device layer 02, a barrier layer 03, a phase change material layer 04, and a top electrode 05 from bottom to top. The phase change unit is composed of a selection device S and a phase change resistor R, namely, the structure form of 1S1R is formed.

The 3DX-point technology of fig. 1 uses a vertical stacking technology of two layers of phase change cells to form a memory cell. However, this structure has two problems: firstly, because the phase change material layer 04 in the first layer of phase change unit is very sensitive to temperature, the thermal budget of the process is very limited when the second layer of phase change unit is prepared, and needs to be less than 350 ℃, which puts high requirements on the material screening and preparation processes of the selective device layer 02 and the phase change material layer 04, and can affect the performance and yield of the device. Secondly, the threshold voltage of the bidirectional threshold switch adopted by the 3DX-point is higher, generally 3-5V, which causes the power consumption of the phase change unit to be larger. Moreover, most of the materials used for the bidirectional threshold switch contain toxic substances such As As or Se, so that a special protection device needs to be additionally equipped for equipment for depositing the thin film, thereby increasing the cost of mass production and increasing the difficulty of compatibility with a CMOS (complementary metal oxide semiconductor) production line.

Therefore, it is desirable to design a new phase change memory cell and a method for fabricating the same to solve the above problems caused by insufficient processes.

Disclosure of Invention

The present invention is directed to overcome the above-mentioned defects in the prior art, and provides a phase change memory cell and a method for fabricating the same, so as to increase the storage density of the phase change memory cell and improve the device performance.

In order to achieve the purpose, the technical scheme of the invention is as follows:

the invention provides a phase change memory unit, comprising from bottom to top: the phase change unit is a longitudinally arranged cylindrical structure, and the cylindrical structure comprises a selection device layer, a barrier layer and a phase change material layer which are sequentially connected from inside to outside; the first electrodes are connected with the phase change material layer respectively, the selection device layer is connected with the second electrode, and the selection device layer comprises a two-dimensional transistor diode layer which is longitudinally arranged.

Further, the two-dimensional transistor diode layer comprises a two-dimensional transistor PN diode layer which is configured to be connected with a two-dimensional transistor material layer with N-type semiconductor property and a two-dimensional transistor material layer with P-type semiconductor property, and the second electrode is connected with the two-dimensional transistor material layer with P-type semiconductor property.

Further, the two-dimensional transistor diode layer includes a two-dimensional transistor schottky diode layer configured as a connected two-dimensional transistor material layer having a semiconductor property and a two-dimensional transistor material layer having a metal property, and the second electrode is connected to the two-dimensional transistor material layer having a metal property.

Furthermore, the selection device layer further comprises a conductor material layer connected and arranged on the inner side of the two-dimensional transistor layer, and the second electrode is connected with the conductor material layer.

Further, the first electrode comprises a bottom electrode and a heating electrode correspondingly connected with the bottom electrode, the lower end of the heating electrode is connected with the upper end of the bottom electrode, and the upper end of the heating electrode is connected with the lower end of the phase change material layer.

The invention also provides a preparation method of the phase change memory unit, which comprises the following steps:

s01: providing a substrate, depositing a first medium layer on the substrate, and forming a plurality of first electrodes in the substrate and the first medium layer;

s02: depositing a second dielectric layer on the first dielectric layer, and forming a through first groove structure in the second dielectric layer corresponding to each first electrode position;

s03: sequentially forming a phase change material layer and a barrier layer on the surface of the side wall of the first groove, so that a second groove is formed in the first groove in the barrier layer, and the phase change material layer is connected with each first electrode;

s04: forming a selective device layer in the second groove, and filling the second groove with the selective device layer; wherein the formed selection device layer comprises a two-dimensional transistor diode layer;

s05: removing the redundant phase change material layer, the barrier layer and the selective device layer material outside the first groove to form a phase change unit with a cylindrical structure in the first groove;

s06: and depositing a third dielectric layer on the second dielectric layer, and forming a second electrode connected with the selection device layer in the third dielectric layer.

Further, in step S04, when forming the two-dimensional transistor diode layer, the forming includes sequentially forming a two-dimensional transistor material layer having an N-type semiconductor property and a two-dimensional transistor material layer having a P-type semiconductor property on a sidewall surface of the second groove, so as to form a two-dimensional transistor PN diode layer; in step S06, the second electrode is formed to be connected to the two-dimensional crystal material layer having P-type semiconductor properties.

Further, in step S04, when forming the two-dimensional transistor diode layer, the forming includes sequentially forming a two-dimensional transistor material layer having a semiconductor property and a two-dimensional transistor material layer having a metal property on a sidewall surface of the second groove, so as to form a two-dimensional transistor schottky diode layer; in step S06, the second electrode is formed to be connected to the two-dimensional crystal material layer having a metal property.

Further, in step S04, when forming the selection device layer, the forming includes forming the two-dimensional transistor diode layer on the surface of the sidewall of the second groove, and then forming a conductor material layer on the inner side of the two-dimensional transistor diode layer; in step S06, the second electrode is formed to be connected only to the conductor material layer.

Further, in step S01, forming a plurality of first electrodes in the substrate and the first dielectric layer includes: forming a plurality of bottom electrodes in the substrate and the first dielectric layer, and continuously forming a plurality of first heating electrodes which are correspondingly connected with the bottom electrodes on the bottom electrodes; in step S03, the phase change material layer is connected to each of the first heating electrodes.

According to the technical scheme, the columnar phase change units and the first electrodes are combined together to form a structure that a plurality of phase change resistors R share one selection device S, namely a 1SnR structure, wherein n is the number. The top ends of the first electrodes are connected with the outermost phase change material layer of the same cylindrical phase change unit, and the first electrodes can be connected with different metal interconnection layers. Compared with the traditional 1S1R structure, the 1SnR structure of the invention omits n-1 selectors, and different phase change resistors can be connected with different metal interconnection layers through the corresponding first electrodes, so that the area of the chip in the horizontal direction is not increased, and the storage is realized. And secondly, the two-dimensional transistor diode is adopted as the selection device, the threshold voltage is low, and the power consumption of the device can be effectively reduced. And the material used by the two-dimensional transistor secondary layer does not contain toxic elements, has the characteristics of environmental friendliness and compatibility with a standard CMOS (complementary metal oxide semiconductor) process line, thereby overcoming the problems existing in the prior use of a bidirectional threshold switch and reducing the production cost. In addition, the phase change unit is prepared into a cylindrical annular nested structure by adopting groove filling and chemical mechanical polishing modes, and as the phase change material layers are all crystalline, only the phase change region in contact with the first electrode is subjected to phase change in the operation process of the device, and the thickness of the phase change material positioned on the outer side of the cylindrical structure is very thin, the volume of the phase change operation region can be greatly reduced, and the power consumption of the device is reduced; and the first electrode can comprise a heating electrode with a side wall structure, the heating electrode is connected with the phase-change material layer, and higher current density can be generated by utilizing the very thin thickness of the heating electrode, so that the heating efficiency can be improved, and the power consumption of the device is further reduced. In conclusion, the invention can effectively reduce the power consumption of the device and realize storage.

Drawings

FIG. 1 is a schematic diagram of a conventional phase change memory cell.

Fig. 2 is a schematic structural diagram of a phase change memory cell according to a first embodiment of the invention.

FIG. 3 is a corresponding schematic illustration of a cross-sectional view and a top view of the resulting structure after deposition of a first dielectric layer and a bottom electrode on a substrate in the fabrication of the structure shown in FIG. 2;

FIG. 4 is a corresponding schematic illustration of a cross-sectional view and a top view of the structure resulting from the deposition of a fourth dielectric layer and a recess over the structure shown in FIG. 3;

FIG. 5 is a corresponding schematic illustration of a cross-sectional view and a top view of the resulting structure after deposition of a heater electrode on the structure shown in FIG. 4;

FIG. 6 is a corresponding schematic illustration of a cross-sectional view and a top view of the structure resulting from the deposition of a second dielectric layer and a first recess over the structure shown in FIG. 5;

FIG. 7 is a corresponding schematic illustration in cross-section and top view of the structure resulting from the deposition of a phase change material layer and a barrier layer on the structure shown in FIG. 6;

FIG. 8 is a corresponding schematic illustration of a cross-sectional view and a top view of the structure resulting from the deposition of select device layers on the structure shown in FIG. 7;

FIG. 9 is a corresponding schematic illustration in cross-section and top view of the resulting structure after chemical mechanical polishing processing to form a phase change cell on the structure shown in FIG. 8;

fig. 10 is a schematic view of a phase change operation region of a phase change material layer.

FIG. 11 is a diagram illustrating a phase change memory cell according to a second embodiment of the present invention.

FIG. 12 is a top view of the resulting structure after deposition of a first dielectric layer and a bottom electrode on a substrate in the fabrication of the structure shown in FIG. 11;

FIG. 13 is a cross-sectional view of the structure shown in FIG. 12 taken along line X;

FIG. 14 is a cross-sectional view of the structure shown in FIG. 12 taken along line Y;

FIG. 15 is a top view of the structure shown in FIG. 12 after depositing a fourth dielectric layer and recess;

FIG. 16 is a cross-sectional view of the structure shown in FIG. 15 taken along line X;

FIG. 17 is a top view of the structure shown in FIG. 15 after deposition of heater electrodes thereon;

FIG. 18 is a cross-sectional view of the structure shown in FIG. 17 taken along line X;

FIG. 19 is a top view of the structure shown in FIG. 17 after depositing a second dielectric layer and first recess;

FIG. 20 is a cross-sectional view of the structure shown in FIG. 19 taken along line X;

FIG. 21 is a top view of the structure shown in FIG. 19 after deposition of a phase change material layer and a barrier layer thereon;

FIG. 22 is a cross-sectional view of the structure shown in FIG. 21 taken along line X;

FIG. 23 is a top view of the structure shown in FIG. 21 after deposition of select device layers thereon;

FIG. 24 is a cross-sectional view of the structure shown in FIG. 23 taken along line X;

FIG. 25 is a top view of the structure shown in FIG. 23 after chemical mechanical polishing to form phase change cells;

FIG. 26 is a cross-sectional view of the structure shown in FIG. 25 taken along line X;

FIG. 27 is a top view of the structure shown in FIG. 25 after deposition of a third dielectric layer and a second electrode;

FIG. 28 is a cross-sectional view of the structure of FIG. 27 taken along line X;

FIG. 29 is a diagram illustrating a phase change memory cell according to a third embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are a part of the embodiments of the present invention, but not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.

The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.

A phase change memory cell of the present invention, referring to fig. 2, comprises from bottom to top: a first electrode 103, a phase change cell 114, and a second electrode 116. Phase change cells 114 are longitudinally arranged columnar structures; the pillar structure includes a selection device layer 111, a barrier layer 110, and a phase change material layer 109, which are sequentially connected from the inside to the outside. The number of the first electrodes 103 is multiple, and the first electrodes are respectively connected with the phase change material layer 109; the selection device layer 111 is correspondingly connected to the second electrode 116. Select device layer 111 includes a longitudinally disposed two-dimensional transistor diode layer.

The phase change memory cell may be built on one substrate 101. One to many dielectric layers may be disposed on the substrate 101, for example, a first dielectric layer 102, a second dielectric layer 107, and a third dielectric layer 115 may be disposed thereon; a fourth dielectric layer 104 may also be provided between the first dielectric layer 102 and the second dielectric layer 107 and a fifth dielectric layer may be provided on the third dielectric layer 115. The fourth dielectric layer 104 can be regarded as an extension layer of the first dielectric layer 102, and the fifth dielectric layer can be regarded as an extension layer of the third dielectric layer 115. The phase change memory unit can be embedded in each medium layer.

Substrate 101 may comprise a semiconductor material such as a silicon substrate, gallium arsenide substrate, germanium substrate, silicon germanium substrate, or fully depleted silicon-on-insulator substrate. Substrate 101 may also be an integrated circuit, including an integrated circuit with gate transistors such as transistors, diodes, etc.

In an alternative embodiment, the first electrode 103 may comprise a bottom electrode 103a and a heater electrode 103 b; the top of the bottom electrode 103a is connected to the bottom of the heater electrode 103 b.

The bottom electrode 103a may be located in both the substrate 101 and the first dielectric layer 102. For example, the lower portion of the bottom electrode 103a may be located in the substrate 101, and the upper portion is exposed out of the surface of the substrate 101 and located in the first dielectric layer 102.

The bottom electrode 103a may have a structure with a plurality of through holes, such as the structure with two through holes shown, which may be symmetrically distributed on two sides of the phase change memory cell. The material of the bottom electrode 103a may be a tungsten electrode, but is not limited thereto.

Phase change cell 114 may be located in second dielectric layer 107, which includes from inside to outside: a column-shaped selection device layer 111, an annular barrier layer 110 and an annular phase change material layer 109. Preferably, the phase change cell 114 may include, from inside to outside, a cylindrical selection device layer 111, a circular ring-shaped barrier layer 110, and a circular ring-shaped phase change material layer 109.

The two heating electrodes 103b are arranged on the bottom electrode 103a and correspond to the bottom electrode 103 a; the heating electrode 103b may be disposed in the fourth dielectric layer 104. The heater electrode 103b may have a fan-shaped (three-dimensional fan-ring-shaped) structure, a cubic structure, an L-shaped structure, or a through hole structure provided longitudinally on the upper surface of the bottom electrode 103 a. When an L-shaped structure is adopted, the horizontal bottom edge of the L-shaped structure is connected to the upper surface of the bottom electrode 103a, and the upper end of the vertical sidewall of the L-shaped structure is correspondingly connected to the annular lower end of the phase change material layer 109.

Thus, the heating electrode 103b having a smaller thickness can be used to generate a higher current density, so that the heating efficiency can be significantly improved, thereby further reducing the power consumption of the device.

In this embodiment, two heating electrodes 103b in the form of a sector structure are used (see fig. 5 for understanding). Wherein, the cambered surfaces of the two heating electrodes 103b are oppositely arranged; both the inner and outer sidewalls of the scalloped bottom surface of heater electrode 103b are preferably located within the upper surface area of bottom electrode 103 a. The sector-shaped top surface of each heating electrode 103b is correspondingly connected to the annular lower end surface of the annular phase change material layer 109 and is located within the annular lower end surface of the phase change material layer 109.

The second electrode 116 may include an upper top electrode 118 and a lower contact hole 117 connected, and the contact hole 117 connects the selection device layer 111. The top electrode 118 may be a metal layer.

Wherein, the lower end of the heating electrode 103b is connected to only the bottom electrode 103a, and the upper end of the heating electrode 103b is connected to only the phase change material layer 109 located at the outermost portion of the columnar phase change cell 114; contact hole 117 of second electrode 116 is connected only to select device layer 111 located at the innermost layer of columnar phase change cell 114.

Select device layer 111 employs a two-dimensional transistor diode layer. The two-dimensional diode is adopted to replace an OTS switch, so that the threshold voltage is low, and the power consumption of the device can be effectively reduced; and the used material does not contain toxic elements such As As and the like, is environment-friendly, is compatible with a standard CMOS process line, and can reduce the production cost. Meanwhile, the material of the selection device layer 111 having the two-dimensional transistor diode layer does not undergo phase change during the operation of the phase change memory device.

In an alternative embodiment, select device layer 111 may be a two-dimensional crystalline PN diode layer that includes a contiguous two-dimensional crystalline material layer 112 having N-type semiconductor properties and a two-dimensional crystalline material layer 113 having P-type semiconductor properties. Wherein, the material of the two-dimensional crystal material layer 112 having N-type semiconductor properties may be at least one of silylene, germanene, black phosphorus, stannene, triazine-based graphite-phase carbon nitride, a transition metal disulfide such as molybdenum disulfide, tungsten disulfide, molybdenum diselenide; the material of the two-dimensional crystal material layer 113 having the P-type semiconductor property may be at least one of silylene, germanene, black phosphorus, stannene, and triazine-based graphite-phase carbon nitride.

In an alternative embodiment, selection device layer 111 may also be a two-dimensional crystalline schottky diode layer that includes a contiguous two-dimensional crystalline material layer 112 having semiconductor properties and a two-dimensional crystalline material layer 113 having metallic properties. Wherein, the material of the two-dimensional crystal material layer 112 with semiconductor property may be tungsten disulfide and at least one of molybdenum disulfide, molybdenum ditelluride, tantalum disulfide, tantalum ditelluride, niobium disulfide, niobium ditelluride; the material of the two-dimensional crystal material layer 113 having a metallic property may be at least one of titanium disulfide, molybdenum disulfide, and tungsten ditelluride.

In the above-described embodiment, the contact hole 117 of the second electrode 116 is connected to only the upper end of the two-dimensional crystal material layer 113 having a P-type semiconductor property or the two-dimensional crystal material layer 113 having a metal property in the selection device layer 111 correspondingly.

The barrier layer 110 is made of a conductive material, has high thermal and electrical conductivity and is chemically stable, does not chemically react with the material of the selective device layer 111 and the material of the phase change material layer 109 or undergo element diffusion, prevents mutual reaction and element diffusion between the material of the selective device layer 111 and the material of the phase change material layer 109, and facilitates the growth of a two-dimensional crystal material. The barrier layer 110 may be graphene, a carbon-containing compound, a two-dimensional material, or a material containing at least one of Ti, Pt, W, Ta, Cu, WCN, WN, and TaN.

The phase change material layer 109 is initially crystalline. The phase change material layer 109 may be GeTe-Sb ₂ Te ₃ System, GeTe-SnTe system, Sb ₂ Te System, In ₃ SbTe ₂ System, Sb doping system, and GeTe-Sb doped with Sc, Ag, In, Al, In, C, S, Se, N, Cu, W elements ₂ Te ₃ System, GeTe-SnTe system doped with Sc, Ag, In, Al, In, C, S, Se, N, Cu and W elements, and Sb doped with Sc, Ag, In, Al, In, C, S, Se, N, Cu and W elements ₂ Te system, and In doped with Sc, Ag, In, Al, In, C, S, Se, N, Cu, W elements ₃ SbTe ₂ System and Sb doping system doped with Sc, Ag, In, Al, In, C, S, Se, N, Cu and W elements.

A method of making a phase change memory cell, such as the one in fig. 2, according to the present invention is further described with reference to the following detailed description and accompanying drawings.

As shown in fig. 3 to 9, a method for fabricating a phase change memory cell according to the present invention may include the following steps:

s11: as shown in fig. 3, in order to clearly reflect the structure of the present invention, the upper drawing shows a cross-sectional view, and the lower drawing shows a top view (the same applies below), a first dielectric layer 102 is deposited on the substrate 101, and two via-type bottom electrodes 103a are formed in the substrate 101 and the first dielectric layer 102.

Wherein, the lower half of the bottom electrode 103a is located in the substrate 101, and the upper half is located in the first dielectric layer 102. In this embodiment, the bottom electrode 103a may be a tungsten electrode via with a diameter of 30-100 nm, in this embodiment 40 nm.

As shown in fig. 4, a fourth dielectric layer 104 is deposited on the first dielectric layer 102 and the bottom electrode 103a, and a through groove 105 structure is formed in the fourth dielectric layer 104 at a position corresponding to the bottom electrode 103 a. The groove 105 may take one of a circular shape, an elliptical shape, a rectangular shape, and a polygonal shape in a plan view. In this embodiment, a circular groove 105 is formed in the fourth dielectric layer 104. Wherein the diameter of the recess 105 is slightly smaller than the sum of the diameter of the two bottom electrodes 103a and the pitch of the two bottom electrodes 103 a.

As shown in fig. 5, the heating electrode 103b is formed on the inner wall surface of the groove 105, and the heating electrode 103b is connected to the bottom electrode 103 a.

The heating electrode 103b may be at least one of a sector, a through hole, and a three-dimensional L-shaped sidewall structure. The heating electrode 103b film can be deposited by atomic layer deposition, chemical vapor deposition or plasma chemical vapor deposition.

In this embodiment, a plasma chemical vapor deposition method is adopted to deposit the heating electrode 103b thin film on the sidewall of the groove 105, and the plasma chemical vapor deposition method is a deposition-etching-deposition-etching method, so that the heating electrode 103b thin film can be deposited only on the sidewall of the groove 105, and no thin film is deposited at the bottom of the groove 105, so that the deposited heating electrode 103b is in a three-dimensional annular shape. Then, the annular heating electrode 103b is divided into two fan-shaped heating electrodes 103b by photolithography and etching processes, and then two three-dimensional fan-shaped heating electrodes 103b are finally formed by depositing a dielectric layer material in the groove 105 and polishing processes.

The material of the heating electrode 103b may be TaN, and the thickness of the heating electrode 103b, i.e., the difference between the radius of the outer ring and the radius of the inner ring of the sector shape, may be 3 to 10nm, in this embodiment, 6 nm.

S12: as shown in fig. 6, a second dielectric layer 107 is deposited on the fourth dielectric layer 104 and the heating electrode 103b, and a through first groove 108 structure is formed in the second dielectric layer 107 at a position corresponding to the upper portions of the two bottom electrodes 103 a; wherein, the number of the first grooves 108 is one; the first groove 108 may be one of an elliptic cylinder, a rectangular parallelepiped, and a prism. In the present embodiment, the first groove 108 is a cylindrical groove, and the diameter of the cylindrical groove should match with the diameter of the groove 105, so as to ensure effective contact between the subsequently formed phase change material layer 109 and the heating electrode 103 b.

S13: as shown in fig. 7, a phase change material layer 109 and a barrier layer 110 in a three-dimensional ring shape are sequentially formed on the sidewall surface of the first groove 108, and the phase change material layer 109 is connected to the heating electrode 103 b.

In the present embodiment, the phase change material layer 109 and the barrier layer 110 are formed in a circular ring shape.

The phase change material layer 109 can be deposited by plasma chemical vapor deposition, that is, a three-dimensional annular film is deposited only on the side wall of the first groove 108, the deposition temperature is 200-500 ℃, and the deposited phase change material is in a crystalline state.

The barrier layer 110 may be deposited by plasma chemical vapor deposition and may be deposited in the same apparatus as the phase change material layer 109.

The tip of the heater electrode 103b in the first electrode 103 is connected only to the outermost phase change material layer 109 of the columnar phase change cells 114.

In the present embodiment, the phase change material layer 109 is, for example, C-doped GeSbTe, and the thickness thereof may be 10-100nm, for example, 25 nm. The material of the barrier layer 110 is, for example, graphene, and the thickness may be 3-15nm, for example, 5 nm. And depositing the phase change material layer 109 material and the barrier layer 110 material in the same equipment by adopting plasma chemical vapor deposition to form the annular phase change material layer 109 and the barrier layer 110.

The plasma chemical vapor deposition mode is a deposition-etching-deposition-etching mode, so that the barrier layer 110 and the phase change material layer 109 can be ensured to be deposited only on the side wall of the first groove 108, and the phase change material layer 109 and the barrier layer 110 are in a three-dimensional annular shape.

Wherein the deposition temperature of the phase-change material is 300 ℃, and the C-doped GeSbTe film is crystalline after deposition. The graphene used as the barrier layer 110 has stable chemical properties, and is excellent in electrical conductivity and thermal conductivity, thereby being beneficial to improving the performance of the phase change memory device.

In the present embodiment, the inner diameter of the sector heating electrode 103b is larger than the inner diameter of the annular phase-change material layer 109, and the outer diameter of the sector heating electrode 103b is smaller than the inner diameter of the annular phase-change material layer 109. Therefore, the contact area between both is the fan-shaped surface area of the fan-shaped heating electrode 103 b. In this way, with a smaller fan-shaped surface area of the fan-shaped heating electrode 103b, the contact area with the annular phase-change material layer 109 can be reduced to increase the heating efficiency and reduce the power consumption.

Since the barrier layer 110 is formed only on the sidewalls of the first recess 108, a second recess is formed in the first recess 108 inside the barrier layer 110.

S14: as shown in fig. 8, the selective device layer 111 material is deposited in the second recess within the barrier layer 110 and fills the second recess. Wherein select device layer 111 comprises a two-dimensional transistor diode layer.

Select device layer 111 may be a two-dimensional transistor PN diode layer or a two-dimensional transistor schottky diode layer.

The selective device layer 111 deposition may be by a chemical vapor deposition or atomic layer deposition process. The deposition process is required to ensure that there are no gaps and holes in the middle of the three-dimensional pillar-shaped selection device layer 111.

In this embodiment, the material of the selective device layer 111 is deposited by chemical vapor deposition. Select device layer 111 is a two-dimensional crystalline Schottky diode layer wherein two-dimensional crystalline material layer 112 having semiconductor properties is MoS ₂ The two-dimensional crystal material layer 113 with metal property is WTE ₂ . Is composed ofThe selection device layer 111, which is composed of the two-dimensional crystal material layer 112 of a semiconductor property and the two-dimensional crystal material layer 113 of a metal property, does not change in the operation of the phase change cell 114.

S15: as shown in fig. 9, the material of the selection device layer 111, the barrier layer 110 and the phase change material layer 109 which are redundant outside the first recess 108 may be removed by chemical mechanical polishing, and a pillar-shaped phase change cell 114 may be formed in the first recess 108.

The formed pillar-shaped phase change cell 114 includes, from inside to outside: device layer 111, barrier layer 110, phase change material layer 109 are selected. The cylindrical phase change cell 114 may be one of an elliptic cylinder, a rectangular parallelepiped, and a prism. The top end of the heater electrode 103b is connected to only the outermost phase change material layer 109 of the pillar-shaped phase change cell 114, and the bottom end of the heater electrode 103b is connected to only the bottom electrode 103 a. The top ends of the two heating electrodes 103b are connected to the outermost phase change material layer 109 of the same columnar phase change cell 114, and the bottom ends of the heating electrodes 103b are connected to different bottom electrodes 103a in a one-to-one correspondence. Different bottom electrodes 103a may connect different metal interconnect layers in the substrate 101. In the present embodiment, the phase change unit 114 is cylindrical and is formed by a WTe with metal property from inside to outside ₂ Layer and MoS with semiconducting properties ₂ Selection device layer 111, graphene barrier layer 110 and C-doped Ge ₂ Sb ₂ Te ₅ A phase change material layer 109. One phase change unit 114 is connected with the top ends of the two solid fan-shaped annular heating electrodes 103b, so that the structure of 1S2R is formed, namely, two phase change resistors share one selection device.

S16: a third dielectric layer 115 is deposited on second dielectric layer 107 and phase change cell 114, a second electrode 116 connected to selection device layer 111 is formed in third dielectric layer 115, and a 1S2R phase change memory cell having a solid fan-ring shaped heater electrode 103b and a cylindrical phase change cell 114 as shown in FIG. 2 is formed.

Second electrode 116 is formed to be connected only to the innermost selection device layer 111 of columnar phase change cells 114. In the present embodiment, the second electrode 116 is a connection structure of a contact hole 117 and a top electrode 118, the contact hole 117 is made of tungsten, and the top electrode 118 is made of copper. Tungsten jointContact hole 117 only contacts WTe of metal nature with the innermost layer of select device layer 111 in columnar phase change cell 114 ₂ Are connected.

The phase change memory cell disclosed in the above embodiments includes, from bottom to top, two through hole bottom electrodes 103a, two solid fan-ring heating electrodes 103b, a cylindrical phase change cell 114 and a second electrode 116. The phase change cell 114 includes, from inside to outside, a selection device layer 111, a barrier layer 110, and a phase change material layer 109. The selection device layer 111 is a two-dimensional crystal schottky diode layer, and is composed of a two-dimensional crystal material layer 113 with a metal property and a two-dimensional crystal material layer 112 with a semiconductor property from inside to outside. The top ends of the two heating electrodes 103b are connected to the outermost phase change material layer 109 of the same column-shaped phase change cell 114, and the bottom ends of the two heating electrodes 103b are connected to different bottom electrodes 103a in a one-to-one correspondence manner, so as to form a structure in which two phase change resistors R1 and R2 share one selection device S, that is, a 1S2R structure is formed. Compared with the existing 1S1R structure, the 1S2R structure omits 1 selector, different phase change resistors can be connected with bottom electrodes positioned on different metal interconnection layers through respective heating electrodes, so that the area of a chip in the horizontal direction is not increased, and the storage is realized.

In addition, as shown in fig. 10, since the phase change region is only a portion of the phase change material above the heater electrode 103b during the operation of the phase change device, that is, the initial state of the phase change material layer 109 is a crystalline state, after the writing operation, the phase change operation region 109a in the phase change material layer 109 is changed from the crystalline state to an amorphous state, and the other region 109b in the phase change material layer 109 is still a crystalline state.

Since the film thickness of the phase change material layer 109 can be only 10-100nm, the volume of the phase change operation region 109a and the required heat energy are greatly reduced, thereby reducing the power consumption of the device.

Furthermore, the thickness of the heating electrode 103b deposited by the three-dimensional fan-shaped side wall is only 3-10nm, the current density generated by the heating electrode is higher, the heating efficiency is improved, and the power consumption of the device is further reduced. Therefore, the phase change memory unit not only can realize storage, but also can effectively reduce the power consumption of the device.

In this embodiment, all the dielectric layers are stacked outside the phase change memory cell 114, and the material of each dielectric layer may be the same or different, and the specific material may be a material of a dielectric layer in the prior art.

It is worth to be noted that compared with the prior art that a bidirectional threshold switch containing toxic elements such As As and the like is used As a selection device, the two-dimensional transistor diode is used for forming the selection device, and the two-dimensional transistor diode does not contain toxic elements, so that the two-dimensional transistor diode has the advantages of being safer and environment-friendly. In addition, the performance of the two-dimensional transistor diode is far superior to that of the existing silicon transistor, and the two-dimensional transistor diode becomes a novel transistor with the most prospect below an advanced process node. The two-dimensional crystal diode is adopted as a selection device, and the phase change memory is more suitable for advanced process nodes and the phase change memory with the following process nodes. In addition, the two-dimensional crystal diode and the barrier layer (generally adopting graphene) have similar properties, the contact resistance of the interface is very small, the performance of the device can be improved, and the process compatibility is also good.

Meanwhile, the conductive material is adopted as the barrier layer material, and the conductor material layer is arranged, so that the growth of the two-dimensional crystal is facilitated, and the contact resistance between the conductive material and the second electrode can be further reduced. In addition, the invention also adopts the process of growing the phase change material, the barrier layer material and the two-dimensional crystal material in the same vacuum equipment, thereby effectively avoiding the contact of the two-dimensional crystal film and air and improving the stability of the performance of the selected device. In addition, the invention also adopts some phase-change materials with the same elements as the two-dimensional crystal materials, thereby realizing the sharing of process equipment.

In another embodiment of the present invention, referring to fig. 11, a phase change memory cell of the present invention can also be built on a substrate 201. One to many dielectric layers, such as a first dielectric layer 202, a second dielectric layer 207, a third dielectric layer 215 and a fourth dielectric layer 204, may also be disposed on the substrate 201; the phase change memory cell may also be embedded in the dielectric layer.

The substrate 201 may comprise a semiconductor material such as a silicon substrate, gallium arsenide substrate, germanium substrate, silicon germanium substrate, or fully depleted silicon-on-insulator. The substrate 201 may also be an integrated circuit including an integrated circuit having gate transistors such as transistors, diodes, etc. In the present embodiment, the substrate 201 is a substrate having two Metal interconnection layers Metal1 and Metal 2. The first electrode 203 may be composed of a bottom electrode 203a and a heating electrode 203 b.

The bottom electrode 203a may be located in both the substrate 201 and the first dielectric layer 202. For example, the lower portion of the bottom electrode 203a is located in the substrate 201, and the upper portion is exposed out of the surface of the substrate 201 and located in the first dielectric layer 202. The bottom electrode 203a may have a structure of a plurality of through holes, for example, a structure of six through holes (see the through holes Via 1-Via 6 in the top view of fig. 12); the six through holes may form a symmetrical hexagonal shape and are located below the phase change memory cell. The bottom electrode 203a may be a TiN electrode, but is not limited thereto.

Among them, the vias Via1, Via3 and Via5 among the six bottom electrodes 203a can be connected to the first-layer Metal interconnection layer Metal1 through the second-layer Metal interconnection layer Metal2, while the vias Via2, Via4 and Via6 are connected only to the second-layer Metal interconnection layer. Fig. 12 shows cross-sectional views in the X and Y directions from the top view, respectively, to more clearly illustrate the relationship between the bottom electrodes Via 1-Via 6.

In the present embodiment, the phase change cell 214 includes, from inside to outside: a cubic pillar shaped select device layer 211, a rectangular ring barrier layer 210 and a rectangular ring phase change material layer 209 surrounding select device layer 211.

The heater electrode 203b is correspondingly formed in a cubic structure having six vertical bars respectively formed on the upper surface of the corresponding bottom electrode 203 a. The bottom edges of the strip structures of the heating electrode 203b are connected to the surface of the bottom electrode 203a, and the upper edges of the six strip structures are correspondingly connected to the lower ends of the four sides of the rectangular loop phase change material layer 209 and correspond to the directions of the sides of the phase change material layer 209 (see the top view of fig. 19).

Second electrode 216 may include top and bottom metal layer contact holes that connect select device layer 211.

Wherein the lower end of each heating electrode 203b is connected to only one corresponding bottom electrode 203a, the upper end of each heating electrode 203b is connected to only one corresponding side of the phase change material layer 209 located at the outermost portion of the phase change cell 214, and the second electrode 216 is connected to only the selection device layer 211 located at the innermost portion of the phase change cell 214.

As another optional mode, the heating electrode may also adopt six conductive through hole structures disposed on the bottom electrode, and the through hole structures are filled with the heating electrode material, so that the upper and lower ends of the through hole structures are respectively and correspondingly connected to the annular lower end of the phase change material layer and the upper surface of the bottom electrode. Or the heating electrode can also adopt an L-shaped structure which is arranged on the bottom electrode; the horizontal bottom edge of the L-shaped structure is connected to the surface of the bottom electrode, and the upper end of the vertical side wall of the L-shaped structure is correspondingly connected to the corresponding side edge of the annular lower end of the phase change material layer.

Select device layer 211 is a two-dimensional transistor diode layer. The material of the select device layer 111 does not undergo a phase change during operation of the phase change memory device.

Select device layer 211 may be a two-dimensional crystalline PN diode layer having a two-dimensional crystalline material layer 212 having N-type semiconductor properties and a two-dimensional crystalline material layer 213 having P-type semiconductor properties.

Alternatively, the selection device layer 211 may also be a two-dimensional crystal schottky diode having a two-dimensional crystal material layer 212 having a semiconductor property and a two-dimensional crystal material layer 213 having a metallic property.

Other aspects of the phase change memory cell can be understood with reference to the structure in the first embodiment shown in fig. 2, and will not be described again.

A method of making a phase change memory cell, such as the one in fig. 11, according to the present invention is further described with reference to the following detailed description and accompanying drawings.

As shown in fig. 12 to fig. 28, a method for fabricating a phase change memory cell according to the present invention may include the following steps:

s21: as shown in fig. 12 to 14, a first dielectric layer 202 is deposited on the substrate 201, and a bottom electrode 203a is formed in the substrate 201 and the first dielectric layer 202.

In this embodiment, the substrate 201 is a substrate 201 with two Metal interconnect layers Metal2 and Metal 1. A first dielectric layer 202 is deposited on the substrate 201, a bottom electrode 203a is formed in the first dielectric layer 202, and the lower half of the bottom electrode 203a is located in the substrate 201 and connected to a second Metal interconnection layer Metal2 in the substrate 201. In a plan view, the bottom electrode 203a has six through holes Via1 to Via6, and the bottom electrode 203a is made of TiN. Wherein vias Via1, Via3, and Via5 are connected to first level Metal interconnect layer Metal1 through second level Metal interconnect layer Metal2, and vias Via2, Via4, and Via6 are connected only to second level Metal interconnect layer Metal 2. The relationship between the bottom electrodes Via1 to Via6 is more clearly shown in the cross-sectional views in the X and Y directions.

As shown in fig. 15 and 16, a fourth dielectric layer 204 is deposited on the first dielectric layer 202 and the bottom electrode 203a, and a recess 205 is formed in the fourth dielectric layer 204.

The groove 205 may be one of circular, oval, rectangular, and polygonal in plan view. In this embodiment, a rectangular recess 205 is formed in the dielectric layer, and the peripheral boundary of the rectangular recess 205 is positioned to intersect with the upper end surface of one or two bottom electrodes 203a on the corresponding side in the vertical direction. For example, the upper and lower sides of the rectangular groove 205 are intersected with the Via1 and the Via4, respectively, the left side is intersected with the Via2 and the Via3, and the right side is intersected with the Via5 and the Via 6.

As shown in fig. 17 and 18, six heating electrodes 203b having a bar shape, for example, a rectangular parallelepiped shape, are formed in the fourth dielectric layer 204 such that the lower end of each heating electrode 203b communicates with a corresponding one of the bottom electrodes 203 a. The heating electrode 203b film can be deposited by atomic layer deposition, chemical vapor deposition or plasma chemical vapor deposition. In this embodiment, a film is deposited on the sidewall of the rectangular groove 205 by plasma chemical vapor deposition, so that the film of the heating electrode 203b can be deposited only on the sidewall of the rectangular groove 205, and no film is deposited on the bottom of the groove 205, so that the formed heating electrode 203b has a three-dimensional rectangular ring shape. And then dividing the annular heating electrode 203b into six rectangular heating electrodes 203b by photoetching and etching processes, and finally forming six three-dimensional rectangular heating electrodes 203b by depositing a fourth dielectric layer 204 material and polishing processes, wherein the heating electrodes 203b can be made of TiN, and the thickness of TiN, namely the difference value between the outer side and the inner side of TiN, is 2-8 nm.

S22: as shown in fig. 19 and 20, a second dielectric layer 207 is deposited on the fourth dielectric layer 204 and the heating electrode 203b, and a first recess 208 is formed in the second dielectric layer 204. The first groove 208 may be one of an elliptic cylinder, a rectangular parallelepiped, and a prism. In the present embodiment, the first groove 208 is a rectangular groove, and the length of the rectangular groove 205 in each direction should match with that of the rectangular groove to ensure effective contact between the subsequently formed phase-change material layer 209 and the heating electrode 203 b.

S23: as shown in fig. 21 and 22, a phase change material layer 209 and a barrier layer 210 are sequentially formed in a rectangular ring shape in the first groove 208. And connects the phase-change material layer 209 to the heating electrode 203 b.

The phase-change material layer 209 can be deposited with a film by plasma chemical vapor deposition, that is, a three-dimensional annular film is deposited only on the sidewall of the first groove 208, the deposition temperature is 200-500 ℃, and the deposited phase-change material is in a crystalline state.

The barrier layer 210 may also be deposited by plasma chemical vapor deposition, which may be in the same apparatus as the phase change material layer 209.

The tip of the heating electrode 203b is connected only to the outermost phase change material layer 209 of the pillar-shaped phase change cell 214.

In the present embodiment, the phase change material layer 209 is made of Sc _0.2 Sb ₂ Te ₃ The thickness is 10-100nm, for example 15 nm. The material of barrier layer 210 is WCN and has a thickness of 3-15nm, which may be, for example, 10 nm.

The phase change material and the barrier layer material are deposited in the same equipment by adopting plasma chemical vapor deposition to form the rectangular annular phase change material layer 209 and the barrier layer 210, so that the barrier layer 210 and the phase change material layer 209 can be only deposited on the side wall of the first groove 208, no thin film is deposited at the bottom, and the phase change material layer 209 and the barrier layer 210 are in a three-dimensional rectangular annular shape. Wherein the deposition temperature of the phase-change material is 300 ℃, and Sc is obtained after deposition _0.2 Sb ₂ Te ₃ The film is crystalline. WCN film as barrierThe layer has stable chemical properties and can effectively prevent the mutual diffusion between the phase change material and the material of the selective device layer.

S24: as shown in fig. 23 and 24, the deposition of select device layer 211 material continues in the void of first recess 208 within barrier layer 210 and fills first recess 208.

Select device layer 211 is a two-dimensional transistor diode layer, which may be a two-dimensional transistor PN diode layer or a two-dimensional transistor schottky diode layer, and the material of select device layer 111 does not undergo a phase change during operation of the phase change memory device.

Select device layer 211 deposition may be by a chemical vapor deposition or atomic layer deposition process. The deposition process is required to ensure that there are no gaps or holes in the middle of the three-dimensional pillar-shaped selection device layer 211.

In this embodiment, the material of the selective device layer 211 is deposited by chemical vapor deposition. Select device layer 211 is a two-dimensional crystalline PN diode layer where two-dimensional crystalline material layer 212 having N-type semiconductor properties is WS ₂ The two-dimensional crystal material layer 213 with P-type semiconductor property is TiS ₂ . The select device layer 211, which is comprised of WS2 and TiS2, does not change in the operation of phase change cell 214.

S25: as shown in fig. 25 and 26, the excess material outside the first groove 208 is removed by chemical mechanical polishing to form a rectangular parallelepiped phase change cell 214. The rectangular solid phase change cell 214 is formed to include, from inside to outside: device layer 211, barrier layer 210, phase change material layer 209 are selected.

In the present embodiment, the phase change cell 214 has a cubic column shape, and TiS having P-type semiconductor property is arranged from the inside to the outside ₂ WS having N-type semiconductor properties ₂ Device layer 211, WCN barrier layer 210, and sc0.2sb2te3 phase change material layer 209.

S26: as shown in FIGS. 27 and 28, a third dielectric layer 215 is deposited over second dielectric layer 207 and phase change cell 214, and a second electrode 216 is formed in third dielectric layer 215. Second electrode 216 is connected to only the innermost select device layer 211 of the rectangular parallelepiped phase change cell 214. The top ends of the heating electrodes 203b are connected to the outermost phase change material layer 209 of the same columnar phase change cell 214, and the bottom ends of the heating electrodes 203b are connected to the corresponding bottom electrodes 203a in a one-to-one correspondence. Different bottom electrodes 203a may connect different metal interconnect layers.

In the present embodiment, the second electrode 216 is a trench of a dual damascene structure, and the metal of the second electrode 216 is copper. Contact holes in dual damascene structure only contact TiS with P-type semiconductor properties with the innermost layer of select device layer 211 in columnar phase change cells 214 ₂ Are connected. Finally, a 1S6R phase change memory cell having six stripe-shaped heater electrodes 203b and a cubic pillar-shaped phase change cell 214 as shown in FIG. 29 was formed.

The phase change memory cell disclosed in the above embodiment includes, from bottom to top, six through-hole type bottom electrodes 203a, six corresponding stripe-shaped heating electrodes 203b, a columnar phase change cell 214, and a second electrode 216. The phase change cell 214 is a cuboid and includes, from inside to outside, a selection device layer 211, a barrier layer 210, and a phase change material layer 209. The top ends of the six heating electrodes 203b are connected to the outermost phase change material layer 209 of the same column-shaped phase change cell 214, and the bottom ends of the six heating electrodes 203b are connected to different bottom electrodes 203a in a one-to-one correspondence manner, so that a 1S6R structure in which six phase change resistors R share one selection device S is formed. Compared with the prior 1S1R structure, the 1S6R structure omits 5 selectors, vias Via1, Via3 and Via5 in the bottom electrode 203a are connected with a first layer Metal interconnection layer Metal1 through a second layer Metal interconnection layer Metal2, and vias Via2, Via4 and Via6 are connected with only a second layer Metal interconnection layer Metal 2. Although a metal layer is added, the area of the chip in the horizontal direction is not increased, and therefore storage is achieved.

As another alternative, a through hole structure penetrating through the fourth dielectric layer may be formed in the fourth dielectric layer corresponding to the bottom electrode, and the heating electrode material may be filled in the through hole to form a heating electrode with a solid structure, so that the upper end and the lower end of the heating electrode with the through hole structure are respectively and correspondingly connected to the annular lower end of the phase change material layer and the upper surface of the bottom electrode. Alternatively, the heating electrode with an L-shaped structure may be formed in the fourth dielectric layer corresponding to the bottom electrode, and may include: depositing a heating electrode material on the surface of the inner wall of the groove, patterning the heating electrode material, removing the redundant heating electrode material on the side wall and the bottom surface of the groove, depositing a dielectric layer material in the groove again, filling the groove, and flattening to form a heating electrode.

As a further alternative, referring to fig. 29, select device layer 311 may be a layer of graphene or chemically stable conductor material 314 at the very center and an annular two-dimensional transistor layer on the outside. The phase change cell 315 includes, from inside to outside, a selection device layer 311 composed of a conductor material layer 314 and annular two-dimensional transistor layers 313, 312, a barrier layer 310, and a phase change material layer 309. The second electrode 317 is connected to only the innermost conductive material layer 314 of the rectangular parallelepiped phase change cell 315. The contact resistance of the two-dimensional transistor diode layers 313, 312 and the second electrode 317 can be further reduced. The top ends of the six heating electrodes 303b are connected to the outermost phase change material layer 309 of the same column-shaped phase change cell 315, the bottom ends of the six heating electrodes 303b are connected to different bottom electrodes 303a in a one-to-one correspondence manner, each pair of heating electrodes 303b and bottom electrodes 303a forms a first electrode 303, and finally a 1S6R structure in which six phase change resistors R share one selection device S is formed. The 1S6R structure is built on the substrate 301 and may be embedded in the multi-layer

dielectric layers

302, 304, 307, and 316.

The conductive material layer 314 is disposed inside the two-dimensional transistor diode layers 313 and 312, which is beneficial to the growth of two-dimensional crystals, and the conductive material layer 314 has the characteristics of high thermal and electrical conductivity and stable chemical properties at high temperature, so that the contact resistance between the conductive material layer and the second electrode 317 can be further reduced.

Other aspects of the phase change memory cell and the method for fabricating the same can be understood with reference to the structure of the second embodiment shown in fig. 11 and the embodiments of the fabrication methods shown in fig. 12 to 28, and will not be described again.

Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.

Claims

1. A phase change memory cell comprising, from bottom to top: the phase change unit is a longitudinally arranged cylindrical structure, and the cylindrical structure comprises a selection device layer, a barrier layer and a phase change material layer which are sequentially connected from inside to outside; the first electrodes are connected with the phase change material layer respectively, the selection device layer is connected with the second electrode, and the selection device layer comprises a two-dimensional transistor diode layer which is longitudinally arranged.

2. The phase-change memory cell of claim 1, wherein the two-dimensional transistor diode layer comprises a two-dimensional transistor PN diode layer configured as a contiguous two-dimensional layer of transistor material having N-type semiconductor properties and a contiguous two-dimensional layer of transistor material having P-type semiconductor properties, the second electrode being connected to the two-dimensional layer of transistor material having P-type semiconductor properties.

3. The phase-change memory cell of claim 1, wherein the two-dimensional transistor diode layer comprises a two-dimensional transistor schottky diode layer configured as a contiguous two-dimensional transistor material layer having a semiconducting property and a two-dimensional transistor material layer having a metallic property, the second electrode being connected to the two-dimensional transistor material layer having a metallic property.

4. The phase change memory cell of claim 1, wherein the select device layer further comprises a layer of conductor material coupled to the inside of the two-dimensional transistor layer, the second electrode coupled to the layer of conductor material.

5. The phase change memory cell of claim 1, wherein the first electrode comprises a bottom electrode and a heater electrode correspondingly connected to the bottom electrode, a lower end of the heater electrode is connected to an upper end of the bottom electrode, and an upper end of the heater electrode is connected to a lower end of the phase change material layer.

6. A method for manufacturing a phase change memory cell, comprising the steps of:

7. The method for manufacturing a phase-change memory cell according to claim 6, wherein the step S04 includes forming a two-dimensional crystal material layer having N-type semiconductor properties and a two-dimensional crystal material layer having P-type semiconductor properties on the sidewall surface of the second groove in sequence to form a two-dimensional crystal PN diode layer; in step S06, the second electrode is formed to be connected to the two-dimensional crystal material layer having P-type semiconductor properties.

8. The method for manufacturing a phase-change memory cell according to claim 6, wherein the step S04 includes forming a two-dimensional transistor material layer having a semiconductor property and a two-dimensional transistor material layer having a metal property on the sidewall surface of the second groove in sequence to form a two-dimensional transistor schottky diode layer; in step S06, the second electrode is formed to be connected to the two-dimensional crystal material layer having a metal property.

9. The method for manufacturing a phase-change memory cell according to claim 6, wherein in step S04, the forming of the selection device layer includes forming the two-dimensional transistor layer on the sidewall surface of the second recess, and forming a conductor material layer on the inner side of the two-dimensional transistor layer; in step S06, the second electrode is formed to be connected only to the conductor material layer.

10. The method for manufacturing a phase-change memory cell according to claim 6, wherein the step S01 of forming a plurality of first electrodes in the substrate and the first dielectric layer comprises: forming a plurality of bottom electrodes in the substrate and the first dielectric layer, and continuously forming a plurality of first heating electrodes which are correspondingly connected with the bottom electrodes on the bottom electrodes; in step S03, the phase change material layer is connected to each of the first heating electrodes.