CN110176535A - A kind of three-dimensional storage and preparation method thereof in self-positioning resistive region - Google Patents
A kind of three-dimensional storage and preparation method thereof in self-positioning resistive region Download PDFInfo
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- CN110176535A CN110176535A CN201910277683.8A CN201910277683A CN110176535A CN 110176535 A CN110176535 A CN 110176535A CN 201910277683 A CN201910277683 A CN 201910277683A CN 110176535 A CN110176535 A CN 110176535A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/021—Formation of the switching material, e.g. layer deposition
- H10N70/023—Formation of the switching material, e.g. layer deposition by chemical vapor deposition, e.g. MOCVD, ALD
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Patterning of the switching material
- H10N70/063—Patterning of the switching material by etching of pre-deposited switching material layers, e.g. lithography
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
Abstract
The invention belongs to technical field of semiconductors, specially a kind of three-dimensional storage and preparation method thereof in self-positioning resistive region.Preparation method disclosed by the invention, comprising the following steps: substrate is provided；Separation layer is grown over the substrate, and a plurality of equally distributed side-wall electrode is then grown on the separation layer；The step is repeated, obtains multilayer lamination structure, and form passivation layer in the multilayer lamination structure；Passivation layer described in chemical wet etching and each layer separation layer, formed between the side-wall electrode multiple separation and equally distributed duct；It anneals under oxygen atmosphere, the side-wall electrode partial oxidation for being distributed in the duct two sides is made to form resistive functional layer；And the sputtering electrode material in the duct, form duct electrode.The present invention solves the problems, such as the reduction of large area continuous function layer bring stability, improves the homogeneity of cubical array device, while simplifying production technology, reduces production cost.
Description
Technical field
The invention belongs to technical field of semiconductors, and in particular to a kind of three-dimensional storage and its system in self-positioning resistive region
Preparation Method.
Background technique
Currently, the research of three-dimensional (3D) resistance-variable storing device is concentrated mainly on the contracting of scalability, size vertically and horizontally
It is small, avoid sneak-out current, improve storage density etc., lack the method for improving device reliability.For 3D memory can
By property problem, part research concentrates on influence of the side-wall electrode to device stability, but flood resistive functional layer bring is reliable
Property and stability problem are ignored.
So far, the 3D resistance-variable storing device based on transition metal oxide, it is usually continuous with being formed along side wall
Metal oxide layer the problem of may bringing Lacking oxygen horizontal proliferation, leads to device reliability when stack size constantly reduces
It reduces.Currently, part work avoids Lacking oxygen horizontal proliferation from drawing by the way of etching functional layer, introducing encapsulation unit structure
The device stability problem risen, but is difficult to selective etch along the metal oxide of side wall and patterns, complex process, cost and
Technical requirements are higher.
Summary of the invention
To solve the above-mentioned problems, the present invention disclose a kind of novel self-positioning resistive region three-dimensional memory structure and
Preparation method avoids large area continuous function layer bring reliable using the oxide layer of fixed electrode as resistive functional layer
Property reduce problem, guarantee that being realized with a low cost high density stablizes three-dimensional storage in the case where not influencing original technique.
The three-dimensional storage preparation method in self-positioning resistive region provided by the invention, comprising the following steps:
Substrate is provided；
Separation layer is grown over the substrate, and a plurality of equally distributed side-wall electrode is then grown on the separation layer；It repeats
The step obtains multilayer lamination structure, and forms passivation layer in the multilayer lamination structure；
Passivation layer described in chemical wet etching and each layer separation layer, formed between the side-wall electrode multiple separation and uniform
The duct of distribution；
It anneals under oxygen atmosphere, the side-wall electrode partial oxidation for being distributed in the duct two sides is made to form resistive functional layer；With
And
The sputtering electrode material in the duct forms duct electrode.
In the three-dimensional storage preparation method in self-positioning resistive region of the invention, it is preferable that the material of the side-wall electrode
Material is Ta, Ti, Ni or W.
In the three-dimensional storage preparation method in self-positioning resistive region of the invention, it is preferable that the material of the duct electrode
Material is Pt, Au, Al, TaN or TiN.
In the three-dimensional storage preparation method in self-positioning resistive region of the invention, it is preferable that in the duct electrode material
The thickness of material is more than or equal to the duct depth.
In the three-dimensional storage preparation method in self-positioning resistive region of the invention, it is preferable that the separation layer and described
The material of passivation layer is Si3N4。
In the three-dimensional storage preparation method in self-positioning resistive region of the invention, it is preferable that the thickness of the separation layer
For 50nm ~ 200nm, the side-wall electrode with a thickness of 50 ~ 200nm.
In the three-dimensional storage preparation method in self-positioning resistive region of the invention, it is preferable that anneal under oxygen atmosphere
Temperature be 300 DEG C -600 DEG C, time 10min-1h.
Invention additionally discloses a kind of three-dimensional storages in self-positioning resistive region, comprising:
Substrate；
Multilayer lamination structure is alternately stacked by multi-layer isolation layer and multilayer sidewall electrode layer, the side-wall electrode layer packet
Include a plurality of equally distributed side-wall electrode；
Passivation layer is formed in the multilayer lamination structure；
Multiple duct electrodes are separated from each other and are evenly distributed between the side-wall electrode；And
Oxide resistive functional layer is only located between the side-wall electrode and the duct electrode.
In the three-dimensional storage in self-positioning resistive region of the invention, it is preferable that the material of the side-wall electrode is Ta,
Ti, Ni or W.
In the three-dimensional storage in self-positioning resistive region of the invention, it is preferable that the material of the duct electrode is Pt,
Au, Al, TaN or TiN.
The present invention forms functional layer using a step thermal oxide, instead of atomic layer deposition, magnetron sputtering functional layer, has
Conducive to simplified technique and reduce cost.In addition, being avoided by the way of thermal oxide in the self-positioning formation change resistance layer of electrode zone
Etching and other complex processes are positioned, solve the problems, such as the reduction of large area continuous function layer bring stability.In addition, using thermal oxide
Mode, help to obtain thermal oxide functional layer in homogeneous thickness, improve the homogeneity of 3D array device.
Detailed description of the invention
Fig. 1 is the flow chart of the three-dimensional storage preparation method in self-positioning resistive region.
Fig. 2 is the top view of the device architecture after forming side-wall electrode.
Fig. 3 is cross-sectional view of the device architecture along A-A ' line of Fig. 2.
Fig. 4 is the device architecture schematic diagram after forming multilayer lamination structure.
Fig. 5 is the top view of the device architecture after forming duct.
Fig. 6 is cross-sectional view of the device architecture along A-A ' line of Fig. 5.
Fig. 7 is the device architecture schematic diagram after forming resistive functional layer.
Fig. 8 is the top view to form the device architecture after the electrode of duct.
Fig. 9 is cross-sectional view of the device architecture along A-A ' line of Fig. 8.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it should be understood that described herein
Specific examples are only used to explain the present invention, is not intended to limit the present invention.Described embodiment is only the present invention one
Divide embodiment, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art are not making
All other embodiment obtained, shall fall within the protection scope of the present invention under the premise of creative work.
In the description of the present invention, it should be noted that the orientation of the instructions such as term " on ", "lower", " vertical " "horizontal"
Or positional relationship is to be based on the orientation or positional relationship shown in the drawings, and is merely for convenience of description of the present invention and simplification of the description, and
It is not that the device of indication or suggestion meaning or element must have a particular orientation, be constructed and operated in a specific orientation, therefore
It is not considered as limiting the invention.In addition, term " first ", " second " are used for description purposes only, and should not be understood as referring to
Show or imply relative importance.
In addition, many specific details of the invention, such as the structure of device, material, size, place are described hereinafter
Science and engineering skill and technology, to be more clearly understood that the present invention.But it just as the skilled person will understand, can be with
The present invention is not realized according to these specific details.Unless hereinafter particularly point out, the various pieces in device can be by
Material well known to those skilled in the art is constituted, or can be using the material with similar functions of exploitation in the future.
Fig. 1 is the flow chart of the three-dimensional storage preparation method in self-positioning resistive region.As shown in Figure 1, specific steps are as follows:
Step S1 prepares one 4 inches of silicon wafer 100；
Step S2, using the Si of plasma reinforced chemical vapour deposition (PECVD) method growth thickness 50nm ~ 200nm3N4As
Separation layer 101, preferably 100nm.Using the Ta of physical gas-phase deposite method (PVD) growth 50nm thickness as side-wall electrode 102,
Resulting structures are as shown in Figures 2 and 3.Above only as a preferred embodiment, but the present invention is not limited thereto, such as can also adopt
It is easy to thermal oxide with Ti, Al, Ni, W etc. and forms the metal of oxide layer as side-wall electrode.In addition, the thickness of side-wall electrode can be with
Between 50nm ~ 200nm.The step is repeated, multilayer lamination structure is obtained, and forms passivation layer 103 in multilayer lamination structure,
Such as Si3N4.In the present embodiment, as shown in figure 4, the number of plies of multilayer lamination structure is 4 layers.But the present invention is not limited thereto,
Any number of plies that can make 2 layers or more preferably can be any number of plies between 2 layers ~ 10 layers；
Step S3, chemical wet etching passivation layer 103 and each layer separation layer 101, formed between side-wall electrode multiple separation and equal
The duct 104 of even distribution, resulting structures are as shown in Figure 5 and Figure 6.Specifically, using photoresist as exposure mask, using SF6To carve
Gas, flow 80sccm are lost, radio-frequency power is 100 W, dry etching Si3N4, obtain duct, then removing photoresist.This
Outside, CF can also be used in etching gas4、SiCl4、NF3Deng；
Step S4 anneals under oxygen atmosphere, and a part oxidation for the side-wall electrode for being distributed in duct two sides is made to form resistive function
Ergosphere 105, even if also side-wall electrode is exposed to the partial oxidation of oxygen atmosphere, as shown in Figure 7.It is special in order to obtain excellent resistive
Property, it is preferable that the oxidation width range of the side-wall electrode of duct two sides controls between 10nm ~ 20nm.It is further preferred that moving back
Fiery temperature is between 300 DEG C -600 DEG C, and annealing time is between 10min-1h.In specific an example, anneal at 400 DEG C
30min；
Step S5, the sputtering electrode material in duct 104 form duct electrode 106, and resulting structures are as shown in Figure 8 and Figure 9.Tool
For body, Pt is sputtered in duct using PVD method as duct electrode, thickness is more than or equal to the depth in duct.In this implementation
In example, with a thickness of 700nm.In addition, the optional range of electrode material is Pt, Au, Al, TaN, TiN etc..
More than, it is carried out for the specific embodiment of the three-dimensional storage preparation method in self-positioning resistive region of the invention
It is described in detail, but the present invention is not limited thereto.The specific embodiment of each step according to circumstances can be different.In addition, portion
Sequence step by step can exchange, and part steps can be omitted.
The three-dimensional storage in self-positioning resistive region provided by the invention, comprising:
Substrate 100；
Multilayer lamination structure is alternately stacked by multi-layer isolation layer 101 and multilayer sidewall electrode layer, and side-wall electrode layer includes
A plurality of equally distributed side-wall electrode 102；
Passivation layer 103, is formed in multilayer lamination structure；
Multiple duct electrodes 106 are separated from each other and are evenly distributed between the side-wall electrode；
Oxide resistive functional layer 105, between side-wall electrode 102 and duct electrode 106.
Preferably, the material of side-wall electrode is Ta, Ti, Ni, W etc..
Preferably, the thickness of side-wall electrode can be between 50nm ~ 200nm.
Preferably, the material of duct electrode is Pt, Au, Al, TaN, TiN etc..
Preferably, the oxidation width range of the side-wall electrode of duct two sides controls between 10nm ~ 20nm.Insolated layer materials
E.g. Si3N4, thickness is preferably 50nm ~ 200nm.
The present invention forms functional layer using a step thermal oxide, instead of atomic layer deposition, magnetron sputtering functional layer, has
Conducive to simplified technique and reduce cost.In addition, being avoided by the way of thermal oxide in the self-positioning formation change resistance layer of electrode zone
Etching and other complex processes are positioned, solve the problems, such as the reduction of large area continuous function layer bring stability.In addition, using thermal oxide
Mode, help to obtain thermal oxide functional layer in homogeneous thickness, improve the homogeneity of 3D array device.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by those familiar with the art, all answers
It is included within the scope of the present invention.
Claims (10)
1. a kind of preparation method of the three-dimensional storage in self-positioning resistive region, which is characterized in that specific steps are as follows:
Substrate is provided；
Separation layer is grown over the substrate, and a plurality of equally distributed side-wall electrode is then grown on the separation layer；It repeats
The step obtains multilayer lamination structure, and forms passivation layer in the multilayer lamination structure；
Passivation layer described in chemical wet etching and each layer separation layer, formed between the side-wall electrode multiple separation and uniform
The duct of distribution；
It anneals under oxygen atmosphere, the side-wall electrode partial oxidation for being distributed in the duct two sides is made to form resistive functional layer；
The sputtering electrode material in the duct forms duct electrode.
2. the three-dimensional storage preparation method in self-positioning resistive region according to claim 1, which is characterized in that the side
The material of wall electrode is Ta, Ti, Ni or W.
3. the three-dimensional storage preparation method in self-positioning resistive region according to claim 1, which is characterized in that the hole
The material of road electrode is Pt, Au, Al, TaN or TiN.
4. the three-dimensional storage preparation method in self-positioning resistive region according to claim 1, which is characterized in that the hole
The thickness of road electrode is more than or equal to the depth in the duct.
5. the three-dimensional storage preparation method in self-positioning resistive region according to claim 1, which is characterized in that it is described every
The material of absciss layer and the passivation layer is Si3N4。
6. the three-dimensional storage preparation method in self-positioning resistive region according to claim 1, which is characterized in that it is described every
Absciss layer with a thickness of 50nm ~ 200nm, the side-wall electrode with a thickness of 50 ~ 200nm.
7. the three-dimensional storage preparation method in self-positioning resistive region according to claim 1, which is characterized in that in oxygen
The temperature annealed under atmosphere is 300 DEG C ~ 600 DEG C, time 10min-1h.
8. a kind of three-dimensional storage in self-positioning resistive region characterized by comprising
Substrate；
Multilayer lamination structure is alternately stacked by multi-layer isolation layer and multilayer sidewall electrode layer, the side-wall electrode layer packet
Include a plurality of equally distributed side-wall electrode；
Passivation layer is formed in the multilayer lamination structure；
Multiple duct electrodes are separated from each other and are evenly distributed between the side-wall electrode；
Oxide resistive functional layer is only located between the side-wall electrode and the duct electrode.
9. the three-dimensional storage in self-positioning resistive region according to claim 8, which is characterized in that the side-wall electrode
Material is Ta, Ti, Ni or W.
10. the three-dimensional storage in self-positioning resistive region according to claim 8, which is characterized in that the duct electrode
Material be Pt, Au, Al, TaN or TiN.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022032550A1 (en) * | 2020-08-13 | 2022-02-17 | Yangtze Advanced Memory Industrial Innovation Center Co., Ltd | Novel integration scheme to form vertical 3d x-point memory with lower cost |
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| CN102097387A (en) * | 2009-12-15 | 2011-06-15 | 三星电子株式会社 | Methods of forming nonvolatile memory devices |
| CN105826468A (en) * | 2016-04-29 | 2016-08-03 | 中国科学院微电子研究所 | Self-gating Resistive Random-Access Memory device and preparation method thereof |
| US20170170393A1 (en) * | 2015-07-14 | 2017-06-15 | Applied Materials, Inc. | Methods for forming structures with desired crystallinity for mram applications |
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2019
- 2019-04-08 CN CN201910277683.8A patent/CN110176535A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050146927A1 (en) * | 2002-10-01 | 2005-07-07 | Gregory Costrini | Spacer integration scheme in MRAM technology |
| CN102097387A (en) * | 2009-12-15 | 2011-06-15 | 三星电子株式会社 | Methods of forming nonvolatile memory devices |
| US20170170393A1 (en) * | 2015-07-14 | 2017-06-15 | Applied Materials, Inc. | Methods for forming structures with desired crystallinity for mram applications |
| CN105826468A (en) * | 2016-04-29 | 2016-08-03 | 中国科学院微电子研究所 | Self-gating Resistive Random-Access Memory device and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2022032550A1 (en) * | 2020-08-13 | 2022-02-17 | Yangtze Advanced Memory Industrial Innovation Center Co., Ltd | Novel integration scheme to form vertical 3d x-point memory with lower cost |
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Application publication date: 20190827 |