CN101920932A - Method for manufacturing nano-size-spacing electrode - Google Patents
Method for manufacturing nano-size-spacing electrode Download PDFInfo
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- CN101920932A CN101920932A CN2009100871285A CN200910087128A CN101920932A CN 101920932 A CN101920932 A CN 101920932A CN 2009100871285 A CN2009100871285 A CN 2009100871285A CN 200910087128 A CN200910087128 A CN 200910087128A CN 101920932 A CN101920932 A CN 101920932A
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Abstract
The invention relates to a method for manufacturing a nano-size-spacing electrode, comprising the following steps: developing an erosion-resisting electric heating insulating material layer on a substrate; depositing a substrate material layer on the electric heating insulating material layer and using photoetching and dry etching methods to remove the four sides of the substrate material layer and form a graph which serves as the substrate for manufacturing a side wall; depositing the side wall material layers on the electric heating insulating material layer, on the substrate material layer and at the side wall of the substrate material layer; employing the dry method for return etching, removing the side wall material layer at the upper surface of the substrate material layer and the side wall material layer on the surface of the electric heating insulating material layer and forming the side wall with height and width both being nano-size; using constant-temperature TMAH solution to remove the substrate material layer, thus only retaining the nano-size side wall; finally, using photoetching plus stripping process or photoetching plus dry etching process to erect a metal layer for manufacturing the nano-size-spacing electrode at the two opposite sides of the side wall material layer; using the wet process corrosion method to remove the side wall and at the same time stripping the metal layer attached to the side wall material wall to form the nano-size-spacing electrode.
Description
Technical field
The present invention relates to microelectronics technology, particularly a kind of method of making the electrode of nano-size-spacing.The present invention proposes the method that a kind of method that adopts side wall technology and constant temperature TMAH solution wet etching polysilicon prepares the electrode of nano-size-spacing.This method has avoided using cost height, the long deficiency of cycle of electron beam exposure, has an enormous advantage in restriction of breakthrough photoetching resolution and aspect tools such as raising device and CMOS compatibility.
Background technology
Along with developing rapidly of microelectronic technique, the integrated level of device is increased sharply, and the microminiaturization of device cell even nanometer make that preparation has excellent conducting performance, technology is reliable and the electrode spacing dimension nanometer becomes more and more important.Nano-electrode micro element as: all there is important use in fields such as molecular device, quantum device, integrated circuit, microsensor.Along with the integration density of microelectronic component along with Moore's Law improves, seek out better integration density, the electrode of the undersized especially nano-size-spacing of preparation spacing becomes the important content of current research.
At present, the preparation method of the electrode of nano-size-spacing mainly contains: photoetching, electron beam lithography, focused-ion-beam lithography, micro-contact printing, electrochemical method and electromigration method etc.But optical lithography method is subjected to the optical wavelength restriction, and the electrode of etching is difficult to reach nanometer scale in micron dimension; The method cycle of micro-contact printing, electron beam lithography and focused-ion-beam lithography grows up to this height; Electrochemistry and electromigration method reliability of technology are lower, may cause incompatible with CMOS technology.In order to break through the compatibility of photoetching resolution restriction and raising device and CMOS technology, seek the method for the electrode that simply and cheaply prepares nano-size-spacing, we propose the present invention's design.
Summary of the invention
The technical problem that solves
Main purpose of the present invention is to provide a kind of method of making the electrode of nano-size-spacing, preparation method with the electrode that searches out a kind of nano-size-spacing, and the preparation method is simple and with low cost, can break through the photoetching resolution restriction, and the compatibility of raising and COMS device.
The present invention improves a kind of method of making the electrode of nano-size-spacing, and this method comprises:
Step 1: the erosion-resisting electric insulating material layer of growth one deck on substrate;
Step 2: deposit one deck substrate material layer is also removed four limits of substrate material layer with the method for photoetching and dry etching on this electric insulating material layer, forms the substrate of figure as the preparation side wall;
Step 3: this above electric insulating material layer and remove substrate material layer above and sidewall deposit spacer material layer;
Step 4: adopt dry back to carve, remove the spacer material layer of substrate material layer upper surface and the spacer material layer of electric insulating material laminar surface, will form height and width and be nano-sized side wall;
Step 6: adopt photoetching+stripping technology or photoetching+dry etch process on the relative dual-side of this spacer material layer, to cost a metal layer of electrodes of making nano-size-spacing at last;
Wherein said electric insulating material layer is silicon nitride or SiO
2Described substrate material layer is a polysilicon; Described spacer material layer is SiO
2Or silicon nitride; Described metal level is a kind of in tungsten, aluminium, copper, gold or the silver.
Wherein said substrate is semiconductive material substrate or insulative material substrate.
Wherein said semiconductive material substrate is silicon chip or SOI sheet.
Wherein said insulative material substrate is SiO
2Or glass.
The corrosive liquid that wherein said removal substrate material layer adopts is a constant temperature TMAH solution, and temperature constant is between 50-90 ℃.
The corrosive liquid that wherein said removal spacer material layer adopts is a kind of in hydrofluoric acid or the hot SPA.
The thickness of wherein said substrate material layer is 20-2000nm.
The width of the side wall that wherein said spacer material layer forms is 5-200nm.
The spacing width of the electrode of the nano-size-spacing that wherein said metal level forms is 5-200nm, and length is 100nm-millimeter magnitude.
From technique scheme as can be seen, the present invention has following beneficial effect:
The method of the electrode of this making nano-size-spacing provided by the invention adopts thin-film technique, lithography stripping technology, wet-etching technology and side wall technology to prepare the metal electrode of nano-size-spacing.Kind electrode preparation method's characteristics are: simple in structure, easy to prepare, electrode size is little, avoided use electron beam exposure (EBL), FIB exposure technology such as (FIB), greatly reduce cost, integrated level significantly improves, and breaks through photoetching resolution restriction simultaneously and has improved with the compatibility of CMOS technology etc.
Description of drawings
For further describing concrete technology contents of the present invention, below in conjunction with embodiment and accompanying drawing describes in detail as after, wherein:
Fig. 1 is the method flow diagram of the electrode of making nano-size-spacing provided by the invention;
Fig. 2-Fig. 7 is a structural representation of making the electrode of nano-size-spacing.
The specific embodiment
See also Fig. 1, Fig. 2-Fig. 7, a kind of method of making nanotubes of the present invention is characterized in that this method comprises:
Step 1: the erosion-resisting electric insulating material layer 102 of growth one deck on substrate 101; Described electric insulating material 102 can be oxide, nitride, sulfide or by at least two kinds in oxide, nitride, the sulfide mixtures that constitute any; The described one deck electric insulating material 102 of growing on substrate can be a kind of realization of adopting in sputtering method, evaporation, plasma assisted deposition method, CVD method, metallo-organic decomposition process, laser assisted deposition method and the thermal oxidation process; Described electric insulating material 102 is removed the equal tool corrosion resistance of using when wet method is removed spacer material layer 104 in substrate material layer 103 and the step 6 of corrosive liquid (Fig. 2) for wet method in the step 4; Wherein said electric insulating material layer 102 is silicon nitride or SiO
2Described substrate 101 is semiconductive material substrate or insulative material substrate; Described semiconductive material substrate 101 is silicon chip or SOI sheet, and described insulative material substrate is SiO
2Or glass;
Step 2: deposit one deck substrate material layer 103 is also removed four limits of substrate material layer 103 with the method for photoetching and dry etching on this electric insulating material layer 102, forms the substrate of figure as the preparation side wall; Wherein said substrate material layer 103 is polysilicons; Described substrate material layer 103 is (Fig. 2) that adopt the preparation of low-pressure chemical vapor phase deposition method; Described substrate material layer 103 is polysilicons; The thickness of described substrate material layer 103 is 20-2000nm;
Step 3: this above electric insulating material layer 102 and remove substrate material layer 103 above and sidewall deposit spacer material layer 104; The employing dry back is carved, and removes the spacer material layer 104 of substrate material layer 103 upper surfaces and the spacer material layer 104 on electric insulating material layer 102 surface, will form height and width and be nano-sized side wall; The width of the side wall that described spacer material layer 104 forms is 5-200nm; Wherein said spacer material layer 104 can be oxide, nitride, sulfide or by any (in hydrofluoric acid or hot SPA a kind of) at least two kinds in oxide, nitride, the sulfide mixtures that constitute; Described deposit one deck spacer material layer 104 can be a kind of realization of adopting in sputtering method, evaporation, plasma assisted deposition method, CVD method, metallo-organic decomposition process, laser assisted deposition method and the thermal oxidation process; Described spacer material layer 104, the corrosive liquid that uses when removing substrate material layer 103 in the step 4 has corrosion resistance (Fig. 3, Fig. 4); Described spacer material layer 104 is SiO
2Or silicon nitride;
Step 4, usefulness constant temperature TMAH solution removal substrate material layer 103, thus only retain nano-sized side wall; The temperature of constant temperature TMAH solution can constant a certain value (Fig. 5) in 50-90 ℃;
Step 5: adopt photoetching+stripping technology or photoetching+dry etch process on the relative dual-side of this spacer material layer 104, to cost a metal layer of electrodes 105 of making nano-size-spacing at last; Described metal level 105, the corrosive liquid that uses when removing spacer material layer 104 in the step 6 has corrosion resistance; Described metal level 105 can be a kind of in tungsten, aluminium, copper, the gold, silver etc.; Described metal level 105 can be a kind of preparation in deposited by electron beam evaporation, thermal evaporation or the magnetron sputtering etc. (Fig. 6); Described metal level 105 is a kind of in tungsten, aluminium, copper, gold or the silver; The spacing width of the electrode of the nano-size-spacing that described metal level 105 forms is 5-200nm, and length is 100nm-millimeter magnitude;
The method of the electrode of making nano-size-spacing provided by the invention based on side wall method and constant temperature TMAH wet etching method, thereby breaks through photoetching resolution restriction and raising and COMS processing compatibility.It below is specific embodiment.
Embodiment 1
1, adopt semiconductor such as monocrystalline silicon piece, SOI sheet or insulating materials as substrate 101;
2, adopt thin film preparation process, preparation electric heating insulating barrier silicon nitride 102 on substrate;
3, LPCVD deposit polysilicon forms the sidewall substrate figure by optical lithography and dry etching, as shown in Figure 2 then as making sidewall substrate 103 on electric heating insulating barrier silicon nitride.
4, spacer material silica 1 04 is sacrificed in the PECVD deposit, as shown in Figure 3; Dry back is carved to form and is sacrificed side wall then, as shown in Figure 4.
5, float sidewall substrate (constant temperature TMAH solution is very high to the etching selection ratio of underlayer nitriding silicon and side wall silica) with constant temperature TMAH solution, as shown in Figure 5.
6, adopt the metal level 105 of optical lithography and stripping technology formation tungsten on the relative dual-side of sacrificing side wall, as shown in Figure 6.And then with hydrofluoric acid side wall is floated, meanwhile, also floated, thereby formed metal electrode, as shown in Figure 7 attached to the metal on the side wall.
Concrete steps and condition are with embodiment 1, and difference is to adopt SiO
2As electric insulating material, silicon nitride adopts the corrosive liquid of hot SPA as the corrosion side wall as spacer material.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. method of making the electrode of nano-size-spacing, this method comprises:
Step 1: the erosion-resisting electric insulating material layer of growth one deck on substrate;
Step 2: deposit one deck substrate material layer is also removed four limits of substrate material layer with the method for photoetching and dry etching on this electric insulating material layer, forms the substrate of figure as the preparation side wall;
Step 3: this above electric insulating material layer and remove substrate material layer above and sidewall deposit spacer material layer;
Step 4: adopt dry back to carve, remove the spacer material layer of substrate material layer upper surface and the spacer material layer of electric insulating material laminar surface, will form height and width and be nano-sized side wall;
Step 5, usefulness constant temperature TMAH solution removal substrate material layer, thus only retain nano-sized side wall;
Step 6: adopt photoetching+stripping technology or photoetching+dry etch process on the relative dual-side of this spacer material layer, to cost a metal layer of electrodes of making nano-size-spacing at last;
Step 7, remove side wall with wet etching method and peel off simultaneously, form the electrode of nano-size-spacing attached to the metal level on the spacer material layer.
2. the method for the electrode of making nano-size-spacing according to claim 1, wherein said electric insulating material layer is silicon nitride or SiO
2Described substrate material layer is a polysilicon; Described spacer material layer is SiO
2Or silicon nitride; Described metal level is a kind of in tungsten, aluminium, copper, gold or the silver.
3. the method for the electrode of making nano-size-spacing according to claim 1, wherein said substrate are semiconductive material substrate or insulative material substrate.
4. the method for the electrode of making nano-size-spacing according to claim 3, wherein said semiconductive material substrate are silicon chip or SOI sheet.
5. the method for the electrode of making nano-size-spacing according to claim 3, wherein said insulative material substrate is SiO
2Or glass.
6. the method for the electrode of making nano-size-spacing according to claim 1, the corrosive liquid that wherein said removal substrate material layer adopts is a constant temperature TMAH solution, temperature constant is between 50-90 ℃.
7. the method for the electrode of making nano-size-spacing according to claim 1, the corrosive liquid that wherein said removal spacer material layer adopts are a kind of in hydrofluoric acid or the hot SPA.
8. the method for the electrode of making nano-size-spacing according to claim 1, the thickness of wherein said substrate material layer are 20-2000nm.
9. the method for the electrode of making nano-size-spacing according to claim 1, the width of the side wall that wherein said spacer material layer forms is 5-200nm.
10. the method for the electrode of making nano-size-spacing according to claim 1, the spacing width of the electrode of the nano-size-spacing that wherein said metal level forms is 5-200nm, length is 100nm-millimeter magnitude.
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| CN102180440A (en) * | 2011-04-06 | 2011-09-14 | 北京大学 | Preparation method of nano-gap electrode in micro-nano electromechanical device |
| CN102602880A (en) * | 2012-03-22 | 2012-07-25 | 中国科学院半导体研究所 | Universal self-aligned preparation method for fully limited nanowires among various materials |
| CN102768956A (en) * | 2012-07-02 | 2012-11-07 | 北京大学 | Method for manufacturing thin line with relatively small edge roughness |
| WO2015167019A1 (en) * | 2014-04-28 | 2015-11-05 | Quantum Biosystems Inc. | Nanogap electrode devices and systems and methods for forming the same |
| US9535033B2 (en) | 2012-08-17 | 2017-01-03 | Quantum Biosystems Inc. | Sample analysis method |
| US9644236B2 (en) | 2013-09-18 | 2017-05-09 | Quantum Biosystems Inc. | Biomolecule sequencing devices, systems and methods |
| US10202644B2 (en) | 2010-03-03 | 2019-02-12 | Quantum Biosystems Inc. | Method and device for identifying nucleotide, and method and device for determining nucleotide sequence of polynucleotide |
| US10261066B2 (en) | 2013-10-16 | 2019-04-16 | Quantum Biosystems Inc. | Nano-gap electrode pair and method of manufacturing same |
| US10438811B1 (en) | 2014-04-15 | 2019-10-08 | Quantum Biosystems Inc. | Methods for forming nano-gap electrodes for use in nanosensors |
| CN116169979A (en) * | 2023-03-08 | 2023-05-26 | 北京中科飞鸿科技股份有限公司 | Ultra-fine line width interdigital electrode, preparation method thereof and interdigital transducer |
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| US10202644B2 (en) | 2010-03-03 | 2019-02-12 | Quantum Biosystems Inc. | Method and device for identifying nucleotide, and method and device for determining nucleotide sequence of polynucleotide |
| US10876159B2 (en) | 2010-03-03 | 2020-12-29 | Quantum Biosystems Inc. | Method and device for identifying nucleotide, and method and device for determining nucleotide sequence of polynucleotide |
| CN102180440A (en) * | 2011-04-06 | 2011-09-14 | 北京大学 | Preparation method of nano-gap electrode in micro-nano electromechanical device |
| CN102602880A (en) * | 2012-03-22 | 2012-07-25 | 中国科学院半导体研究所 | Universal self-aligned preparation method for fully limited nanowires among various materials |
| CN102602880B (en) * | 2012-03-22 | 2014-12-17 | 中国科学院半导体研究所 | Universal self-aligned preparation method for fully limited nanowires among various materials |
| CN102768956A (en) * | 2012-07-02 | 2012-11-07 | 北京大学 | Method for manufacturing thin line with relatively small edge roughness |
| US9535033B2 (en) | 2012-08-17 | 2017-01-03 | Quantum Biosystems Inc. | Sample analysis method |
| US9644236B2 (en) | 2013-09-18 | 2017-05-09 | Quantum Biosystems Inc. | Biomolecule sequencing devices, systems and methods |
| US10557167B2 (en) | 2013-09-18 | 2020-02-11 | Quantum Biosystems Inc. | Biomolecule sequencing devices, systems and methods |
| US10261066B2 (en) | 2013-10-16 | 2019-04-16 | Quantum Biosystems Inc. | Nano-gap electrode pair and method of manufacturing same |
| US10466228B2 (en) | 2013-10-16 | 2019-11-05 | Quantum Biosystems Inc. | Nano-gap electrode pair and method of manufacturing same |
| US10438811B1 (en) | 2014-04-15 | 2019-10-08 | Quantum Biosystems Inc. | Methods for forming nano-gap electrodes for use in nanosensors |
| WO2015167019A1 (en) * | 2014-04-28 | 2015-11-05 | Quantum Biosystems Inc. | Nanogap electrode devices and systems and methods for forming the same |
| CN116169979A (en) * | 2023-03-08 | 2023-05-26 | 北京中科飞鸿科技股份有限公司 | Ultra-fine line width interdigital electrode, preparation method thereof and interdigital transducer |
| CN116169979B (en) * | 2023-03-08 | 2024-05-24 | 北京中科飞鸿科技股份有限公司 | Ultra-fine line width interdigital electrode, preparation method thereof and interdigital transducer |
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Application publication date: 20101222 |