CN102180440A - Preparation method of nano-gap electrode in micro-nano electromechanical device - Google Patents

Preparation method of nano-gap electrode in micro-nano electromechanical device Download PDF

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CN102180440A
CN102180440A CN2011100852402A CN201110085240A CN102180440A CN 102180440 A CN102180440 A CN 102180440A CN 2011100852402 A CN2011100852402 A CN 2011100852402A CN 201110085240 A CN201110085240 A CN 201110085240A CN 102180440 A CN102180440 A CN 102180440A
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layer
material
etching
structure
sacrificial
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CN2011100852402A
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于侃
于晓梅
王晓菲
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北京大学
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Abstract

The invention provides a preparation method of a nano-gap electrode in a micro-nano electromechanical device, which belongs to the field of micro-nano electromechanical systems. According to the preparation method, an appropriate material is selected to prepare a sacrificial layer, and the preparation method comprises the following steps of: firstly, preparing a nano-scale side wall structure of the sacrificial layer in a mode of back etching, wherein the side wall needs to have a certain height; secondly, depositing a layer of thin metal layer or other electrode materials; and thirdly, selectively corroding the side wall material of the sacrificial layer, wherein the metals or other electrode materials attached to the side wall are corroded together, and a gap is formed at the position of the side wall. The nano-gap electrode is prepared by keeping the thickness of the sacrificial layer side wall in a nano scale. The preparation method is compatible with the conventional semiconductor processing technique, is easy for large-scale production, and is low in cost.

Description

一种微纳机电器件中纳米间隙电极的制备方法 A micro-nano NEMS device electrode gap Preparation

技术领域 FIELD

[0001] 本发明涉及一种微纳机电器件中纳米间隙电极的制备方法,属于微纳机电系统领域。 [0001] The present invention relates to a method of micro and nano electromechanical devices nanogap electrodes belonging to the field of micro-nano electromechanical systems.

背景技术 Background technique

[0002] 随着硅器件特征尺寸的缩小,对于微纳结构的制作工艺的需求越来越大。 [0002] With the shrinking feature sizes of the silicon devices, micro and nano fabrication process for the structure of the growing demand. 纳米间隙电极是MEMS器件的基础部分。 Nanogap electrodes is a fundamental part of the MEMS device. 纳米间隙电极对于检测纳米尺度材料的性质,以及构造量子器件、生物传感器方面有重要的应用。 Nanogap electrodes for detecting properties of nanoscale materials, quantum devices and the configuration, biosensors have important applications.

[0003] 制造纳米间隙电极的工艺方式有电子束刻蚀法、原子力显微镜纳米刻蚀法、接点断裂法和电镀法等。 [0003] Process nanogap electrodes manufactured are electron beam lithography, atomic force microscopy nanolithography method, the contact breaking method and a plating method. 其中,(1)电子束具有比普通光更短的波长,由于采用电场精确地聚焦,因此可以获得更高的分辨率,而且可以在计算机控制下任意直写,但效率低,价格昂贵, 以及入射电子束产生的邻近效应问题使其很难大规模应用;(2)接点断裂法优势在于方法简单,可以制备间隙微小的电极,但不易于批量生产;(3)电镀法通过传统的光刻技术制备出间隙在微米量级的金属电极,然后将淀积置于电镀液中,电镀液中的金属还原沉积在电极表面,这种方法简便高效,但只能对具体的器件一个一个的操作;(4)电子迁移法成本低廉,但是所制备的电极外形不规则,制备过程不易控制,很难进行大规模制造。 Wherein, (1) an electron beam having a shorter wavelength than the normal light, the use of precisely focused electric field, higher resolution can be obtained, and may be arbitrarily write under computer control, but inefficient, expensive, and proximity effect problem generated by the incident electron beam so that large-scale application difficult; (2) cleavage method contacts the advantage that simple, small electrode gap can be prepared, but not easy for mass production; by conventional photolithography (3) plating techniques for preparing a gap in microns metal electrode, is deposited and then placed in the plating solution, the plating solution in the reduction of the metal deposited on the electrode, this method is simple and efficient, but only the operation of a specific device of a ; low (4) an electron transport cost method, but the prepared electrode irregular shape, the preparation process is difficult to control, it is difficult for large scale manufacturing.

发明内容 SUMMARY

[0004] 本发明提出一种基于微机械工艺的纳米间隙电极的制备方法。 [0004] The present invention provides a method for preparing a nanogap electrodes based on micro-mechanical process. 该方法采用牺牲层侧墙结构定义纳米间隙的宽度,可不受光刻精度的影响。 The method uses defined nanogap width of the sacrificial spacer layer structure, without being affected by the precision of photolithography.

[0005] 本发明提供的微纳机电器件中纳米间隙电极的制备方法,具体步骤包括: [0005] The production method of the nanogap electrodes, micro concrete step NEMS device of the present invention comprises:

[0006] 1)在基片上淀积一层介质材料作为绝缘层,再选择淀积一种厚度合适的材料作为侧墙的辅助结构层,辅助结构层材料应与绝缘层材料有较好的腐蚀选择比; [0006] 1) depositing on a substrate a layer of dielectric material as an insulating layer, and then selectively deposited material having a thickness suitable as an auxiliary spacer layer structure, the auxiliary structure layer material should have good etching the insulating layer material selectivity;

[0007] 2),光刻,定义辅助结构掩膜层图形后,干法刻蚀辅助结构层材料形成侧壁陡直的辅助结构图形,为后续的牺牲层淀积做准备; [0007] 2), lithography, the mask layer that define the secondary structure pattern, dry etching the auxiliary layer material forming a sidewall structure steep auxiliary structure pattern, in preparation for the subsequent deposition of the sacrificial layer;

[0008] 3)淀积一层牺牲层材料,牺牲层的厚度决定最后纳米间隙的宽度,牺牲层材料同时要与后续的纳米间隙电极材料有很好的腐蚀选择比; [0008] 3) depositing a sacrificial layer material, the thickness of the sacrificial layer determines the width of the last nanogap, while the sacrificial layer material and the subsequent nanogap electrode material has good etch selectivity ratio;

[0009] 4)回刻牺牲层,一般选择性过刻蚀3秒,直到辅助结构层上表面完全裸露,由于干法刻蚀的各向异性刻蚀性质,附着在辅助结构层侧壁的牺牲层会保留下来; [0009] 4) etching back the sacrificial layer, over-etching selectivity is generally 3 seconds until the upper surface of the auxiliary layer is completely bare structure, since the anisotropic etching dry etching properties, adhered to the sacrificial layer sidewall auxiliary structure layer will be retained;

[0010] 5)湿法腐蚀基片,选用腐蚀辅助结构层的腐蚀液,从而保护牺牲层侧墙结构不被腐蚀,辅助结构层腐蚀完成后只剩下纳米宽度的牺牲层侧墙。 [0010] 5) wet etching of the substrate, the choice of an etching solution etching the auxiliary layer structure, a sacrificial layer to protect against corrosion sidewall structure, the sacrificial layer leaving spacers nanometers width after etching the auxiliary layer structure is completed.

[0011] 6)淀积一层薄的电极材料,该材料为金属或其它导电性良好的材料,需与牺牲层侧墙材料有良好的腐蚀选择性; [0011] 6) depositing a thin layer of electrode material, the material is a metal or other conductive material having good, the sacrificial layer needs spacer material has good etch selectivity;

[0012] 7)湿法腐蚀牺牲层侧墙,由于电极材料不能完全覆盖侧墙结构,在腐蚀侧墙牺牲层时腐蚀液会横钻并腐蚀牺牲层结构,覆盖在侧墙上的电极材料会连同牺牲层侧墙一起被选择性腐蚀掉,形成最终的纳米间隙电极结构。 [0012] 7) wet etching the sacrificial spacer layer, since the electrode material can not completely cover the sidewall structure when etching the sacrificial layer sidewall etchant will etch the sacrificial layer and the cross-drilling structure, covering the electrode material on the sidewall will together with the sacrificial spacer layer is selectively etched together to form the final structure nanogap electrodes. [0013] 本发明提供的方法具有如下优点: [0013] The present invention provides a method has the following advantages:

[0014] 采用简单、可重复的工序,制作高集成度的纳米器件,并且不受光刻最小尺寸限制,不需要采用电子束光刻。 [0014] using a simple, reproducible process, the production of highly integrated nanodevice, the lithographic minimum dimension and is not limited, and does not require use of electron beam lithography.

[0015] 通过上述方法制作的硅纳米间隙电极结构,可应用于多种微纳机电传感器的制备,可以制作检测生物活性分子的Bio-MEMS传感器,可以制作研究纳米自旋电子学的量子器件等。 [0015] prepared by the above method for producing silicon nanogap electrode structure can be applied to the preparation of a variety of micro-nano electromechanical transducer can be produced Bio-MEMS sensor detecting biologically active molecule can be produced Nano spintronics devices such as quantum .

附图说明 BRIEF DESCRIPTION

[0016] 图l(a)_(d)为本发明实施例制作纳米间隙的工艺流程示意图,其中:(a)淀积绝缘介质层;(b)淀积辅助结构层;(c)光刻并刻蚀形成辅助结构层;(d)淀积牺牲层材料; (e)回刻牺牲层形成牺牲层侧墙;(f)选择性腐蚀辅助结构层材料形成侧墙牺牲层;(g)溅射薄金属层或主结构层材料;(h)腐蚀侧墙牺牲层形成纳米间隙结构; Depositing the auxiliary layer structure (B);; lithography (c) (a) depositing an insulating dielectric layer: [0016] FIG. L (a) _ (d) a schematic diagram of the production process of the present embodiment nanogap invention, wherein and etching to form the auxiliary layer structure; (d) depositing a sacrificial layer material; (e) etching back the sacrificial spacer layer is a sacrificial layer is formed; (f) selectively etching the spacer material layer auxiliary structure a sacrificial layer; (G) sputtering emitting layer or the primary layer of a thin metal material structure; (H) etching the sacrificial spacer layer is formed of nano-gap structure;

[0017] 图2是利用本发明制作的纳米间隙电极的扫描电镜照片。 [0017] FIG 2 is fabricated using the nanogap electrodes of the present invention is a scanning electron micrograph.

具体实施方式 Detailed ways

[0018] 下面结合通过实施例对本发明作进一步说明,但本发明并不限于以下实施例。 [0018] The following examples in conjunction with the present invention is further illustrated, but the present invention is not limited to the following embodiments.

[0019] 图1所示在硅衬底上制作纳米金属间隙的工艺流程图,具体步骤如下: [0019] Figure 1 shows the production of metal nano gap flow chart on a silicon substrate, the following steps:

[0020] 1)在硅衬底1上LPCVD厚度为IOOnm到120nm氮化硅层2,作为金属电极的绝缘层,见图1(a); [0020] 1) IOOnm to 120nm silicon nitride layer 2, an insulating layer as a metal electrode, shown in Figure 1 (a) in a silicon substrate of a thickness of the LPCVD;

[0021] 2)LPCVD淀积多晶硅层3,厚度800nm,作为后续氧化层淀积的辅助结构层3,见图1(b); [0021] 2) LPCVD deposition of polysilicon layer 3, a thickness of 800 nm, a subsequent auxiliary layer structure deposited oxide layer 3, shown in Figure 1 (b);

[0022] 3)光刻显影后用光刻胶做掩膜干法刻蚀多晶硅层,选用ASE,以形成侧壁陡直的辅助结构图形,便于后续的侧墙牺牲层4淀积,如图1(c); [0022] 3) photolithography using the photoresist mask after development do dry-etching the polysilicon layer, the choice of the ASE, an auxiliary structure to form a pattern of steep sidewall spacers to facilitate the subsequent deposition of the sacrificial layer 4, FIG. 1 (c);

[0023] 4) LPCVD淀积氧化硅层4,厚度lOOnm,其厚度决定侧墙牺牲层的宽度,由于LPCVD 良好的覆盖性,侧壁宽度比淀积厚度IOOnm稍大,如图1(d); [0023] 4) deposition of LPCVD silicon oxide layer 4, the thickness of lOOnm, which determines the width of the thickness of the sacrificial spacer layer, due to the good coverage LPCVD, the deposition thickness slightly larger than the width of the side walls IOOnm, FIG. 1 (d) ;

[0024] 5)回刻氧化层4,刻蚀厚度lOOnm,至多晶硅辅助结构层表面完全裸露,便于后续的TMAH腐蚀多晶硅辅助结构图形,如图1(e)。 [0024] 5) etch back oxide layer 4, a thickness of lOOnm etching, to the surface of the auxiliary structure of the polysilicon layer is completely exposed, to facilitate the subsequent secondary structures TMAH etching the polysilicon pattern, FIG. 1 (e).

[0025] 6)水浴80°C,TMAH湿法腐蚀多晶硅,由于多晶硅与氧化硅良好的腐蚀选择性,氧化硅侧墙牺牲层得以保留,如图1(f)。 [0025] 6) a water bath at 80 ° C, TMAH wet etching polysilicon, due to good etching selectivity of polysilicon and silicon oxide, the silicon oxide sacrificial spacer layer is retained, as shown in FIG 1 (f).

[0026] 7)溅射Cr/Au 100A/800A金属层5,作为电极材料,如图1 (g)。 [0026] 7) a sputtering Cr / Au 100A / 800A metal layer 5, as the electrode material, as shown in FIG 1 (g).

[0027] 8)BHF超声腐蚀氧化硅,腐蚀掉牺牲层侧墙,连带除掉附着在侧墙上的薄金属层, 最终形成纳米间隙电极结构,如图1(h)。 [0027] 8) BHF etching of the silicon oxide ultrasound, etching away the sacrificial spacer layer, the joint removal of a thin metal layer deposited on the spacers, forming nanogap electrode structure, as shown in FIG 1 (h).

[0028] 上述方法实现了本发明的实施方案_利用侧墙牺牲层工艺形成纳米间隙电极结构,并且可以通过牺牲层侧墙的宽度调整纳米间隙的线宽。 [0028] The method implements the embodiment of the present invention using a sacrificial layer process _ spacer formed nanogap electrode structure, and may adjust the line width by the width of the nanogap sacrificial layer sidewall spacers.

[0029] 图2是利用本发明制作的纳米间隙电极的扫描电镜照片,间隙宽度在IlOnm左右。 [0029] FIG. 2 is a scanning electron micrograph of the present invention produced using the nanogap electrodes, a gap width of about IlOnm.

[0030] 以上描述与附图的说明旨在说明本发明的实施方案,本发明的范围仅由所付的权利要求来限定。 [0030] The foregoing description and drawings are intended to illustrate embodiments of the invention, the scope of the present invention is limited only by the claims paid. 本领域的技术人员可以对本发明进行各种必要的改变或变更,但不应脱离本发明。 Those skilled in the art can make the necessary changes or variations of the present invention, but should not departing from the present invention.

Claims (4)

1. 一种纳米间隙电极的制备方法,其步骤包括:1)在基片上淀积一层绝缘材料作为绝缘层,再淀积一辅助结构层;该辅助结构层材料与绝缘层材料应有一定的腐蚀选择比;2)光刻、定义辅助结构掩膜层图形后,干法刻蚀辅助结构层材料形成侧壁陡直的辅助结构图形;3)淀积一层牺牲层材料,牺牲层的厚度为纳米间隙电极的宽度,同时该牺牲层材料与辅助结构层材料应有一定的腐蚀选择比;4)回刻牺牲层直到辅助结构层上表面完全裸露,由于干法刻蚀的各向异性刻蚀性质, 附着在辅助结构层侧壁的牺牲层被保留下来;5)选用腐蚀辅助结构层的腐蚀液腐蚀基片,由于牺牲层材料与辅助结构层材料有一定的腐蚀选择比,因此完成辅助结构层腐蚀后,牺牲层侧墙被保留下来;6)淀积一层电极材料,该电极材料与牺牲层侧墙材料有一定的腐蚀选择比;7)湿法腐蚀 1. A method for preparing a nanogap electrodes, comprising the steps of: a) depositing on a substrate a layer of insulating material as the insulating layer, then depositing an auxiliary layer structure; structure of the auxiliary layer and the insulating layer material should have a certain the etching selection ratio; 2) photolithography, the mask layer that define the secondary structure pattern, dry etching the auxiliary layer material forming a sidewall structure steep auxiliary structure pattern; 3) depositing a sacrificial layer material, the sacrificial layer, the thickness of the width of the nanogap electrodes while the sacrificial layer material and the auxiliary material should have some structural layer etching selectivity; 4) the sacrificial layer etch back until the upper surface of the auxiliary layer is completely bare structure, since the anisotropic dry etching etching properties, adhered auxiliary layer structure sidewall sacrificial layer is retained; 5) selection of etching the auxiliary layer structure etching solution etching the substrate, because the sacrificial layer material and the auxiliary structural layer material has a certain etching selection ratio, thus completing after etching the auxiliary layer structure, the sacrificial spacer layer is retained; 6) depositing a layer of electrode material, the electrode material layer of sacrificial spacer material has a certain etching selection ratio; 7) wet etching 牲层侧墙,在腐蚀牺牲层侧墙时,覆盖在侧墙上的电极材料会连同牺牲层侧墙一起被选择性腐蚀掉,最终在侧墙位置处形成纳米间隙电极。 Sacrifice material layer of an electrode spacer, when etching the sacrificial sidewall spacer layer overlying the spacers are selectively etched away along with the sacrificial spacer layer, forming spacers at the nanogap electrodes position.
2.如权利要求1所述的制备方法,其特征在于,步骤1)中,所述辅助结构层为多晶硅, 厚度为600nm-2 μ m。 2. The method as recited in claim 1, wherein in step 1), the auxiliary layer polysilicon structure, a thickness of 600nm-2 μ m.
3.如权利要求1所述的制备方法,其特征在于,步骤3)中,所述牺牲层为氧化硅,氧化硅厚度小于lOOnm。 The production method as claimed in claim 1, wherein in step 3), the sacrificial layer of silicon oxide, silicon oxide thickness of less than lOOnm.
4.如权利要求1所述的制备方法,其特征在于,步骤6)中,所述电极材料为金属或其它导电性良好的材料。 4. The method as recited in claim 1, wherein step 6), the electrode material is a metal or other conductive material having good.
CN2011100852402A 2011-04-06 2011-04-06 Preparation method of nano-gap electrode in micro-nano electromechanical device CN102180440A (en)

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