CN102768956A - Method for manufacturing thin line with relatively small edge roughness - Google Patents

Method for manufacturing thin line with relatively small edge roughness Download PDF

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Publication number
CN102768956A
CN102768956A CN2012102280421A CN201210228042A CN102768956A CN 102768956 A CN102768956 A CN 102768956A CN 2012102280421 A CN2012102280421 A CN 2012102280421A CN 201210228042 A CN201210228042 A CN 201210228042A CN 102768956 A CN102768956 A CN 102768956A
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method
layer
dry etching
sacrificial layer
substrate
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CN2012102280421A
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张耀凯
李佳
许晓燕
黄如
黎明
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北京大学
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Abstract

The invention provides a method for manufacturing a thin line with relatively small edge roughness, comprising the following steps of depositing a blocking layer and a sacrificial layer on a substrate; coating photoresist on the sacrificial layer, and defining a photoetching graph of the line; transferring the photoetching graph to the sacrificial layer by using a dry etching method; depositing a side wall material layer, and forming a side wall by using the dry etching method; carrying out wet etching on the sacrificial layer in the side wall to form a side wall mask layer; and transferring the line graph to the substrate by using the side wall mask layer and through the dry etching method, so as to obtain the thin line. The method disclosed by the invention is combined with the side wall technology and the wet etching technology; electron-beam lithography, high-temperature oxidation and the like are not used; and the thin line with small edge roughness can be obtained.

Description

一种制备边缘粗糙度较小的细线条的方法 A method for preparing a smaller fine line edge roughness of

技术领域 FIELD

[0001] 本发明属于超大规模集成电路制造技术领域,涉及一种制备集成电路中超细线条的方法,尤其涉及一种结合侧墙技术及湿法腐蚀来制备边缘粗糙度较小的超细线条的方法。 [0001] The present invention belongs to the field of ultra large scale integrated circuit manufacturing technology, relates to a method of preparing an integrated circuit superfine lines, particularly to ultra-fine line edge roughness smaller one kind is prepared and wet etching techniques in conjunction with spacer Methods.

背景技术 Background technique

[0002] 随着集成电路的发展,器件的集成度不断提高,要求器件的尺寸不断减小,制备小尺寸细线条越来越关键。 [0002] With the development of integrated circuits, integrated devices continues to increase, decreasing the size of the device required, preparing a small sized thin lines increasingly critical.

[0003] 采用电子束光刻虽然可以制备细线条,但是由于耗时长,成本高,在工业生产中不具备优势,并且电子束光刻工程中存在电子散射,制备30nm以下细线条遇到很大挑战。 [0003] However, since the electron beam is time-consuming, expensive, in the industrial production does not have the advantage, and the presence of electron scattering in an electron beam lithography Engineering, 30 nm or less prepared fine lines can be prepared while experiencing fine line lithography, large challenge. 其它制备方法,如普通光刻和氧化工艺,虽然能制备细线条,但是细线条有较大的LER(边缘粗糙度),再加上氧化要进行高温加工,时间较长,成本较高,限制了其在工业生产中的发展。 Other production methods, such as photolithography and ordinary oxidation process, although fine lines can be prepared, but the fine lines of LER greater (edge ​​roughness), coupled to a high temperature oxidation process, a longer time, higher cost, limit its development in industrial production.

[0004] 侧墙技术是利用已形成的侧墙作为硬掩模,并向下刻蚀硅形成细线条。 [0004] technique is to use sidewall spacers formed as a hard mask, and etching the silicon formed fine lines. 侧墙技术工艺步骤简单,制作工时短,对设备要求不高,实施性强。 Spacer technology process steps is simple, short manufacturing steps, facility request, and strong embodiment. 通过合理设计,可以利用侧墙技术制备出20nm以下细线条。 By rational design, 20nm or less can be prepared by using spacer technology fine lines.

发明内容 SUMMARY

[0005] 本发明提出一种结合侧墙技术及湿法腐蚀来制备边缘粗糙度(LER)较小的超细纳米线条的方法,避免使用电子束光刻、高温氧化等工艺,可获得尺寸在20nm以下的细线条,同时,线条的LER可以得到改善。 [0005] The present invention proposes a edge roughness (LER) Method smaller ultrafine nano-binding spacer lines prepared and wet etching techniques, avoiding the use of electron beam lithography, high temperature oxidation process, in the obtained size 20nm or less fine lines, while lines LER can be improved.

[0006] 为达到上述目的,本发明采用如下技术方案: [0006] To achieve the above object, the present invention adopts the following technical solution:

[0007] 一种制备边缘粗糙度较小的细线条的方法,包括以下步骤: [0007] A method of edge roughness smaller preparing fine lines, comprising the steps of:

[0008] I)在衬底上淀积阻挡层和牺牲层; [0008] I) deposition of a barrier layer and a sacrificial layer on a substrate;

[0009] 2)在所述牺牲层上涂光刻胶,并定义线条的光刻图形; [0009] 2) coating a photoresist on the sacrificial layer, and photolithographic definition of the graphic lines;

[0010] 3)采用干法刻蚀方法将所述光刻图形转移至所述牺牲层; [0010] 3) a dry etching method of a lithographic pattern is transferred to the sacrificial layer;

[0011] 4)淀积侧墙材料层,并采用干法刻蚀方法形成侧墙; [0011] 4) depositing a spacer material layer, and forming spacers using a dry etching method;

[0012] 5)湿法腐蚀侧墙内的牺牲层,形成侧墙掩膜层; [0012] 5) wet etching of the sacrificial layer within the spacer, spacer mask layer is formed;

[0013] 6)利用所述侧墙掩膜层,通过干法刻蚀将线条图形转移至衬底上,得到细线条。 [0013] 6) using the sidewall spacer mask layer by dry etching the line pattern is transferred onto the substrate, to give a fine line.

[0014] 进一步地,所述衬底为硅衬底。 [0014] Further, the substrate is a silicon substrate.

[0015] 进一步地,所述阻挡层为氧化硅,所述牺牲层为多晶硅。 [0015] Further, the barrier layer is a silicon oxide, the sacrificial layer is polysilicon.

[0016] 进一步地,采用普通光学光刻方法定义线条图形。 [0016] Further, the ordinary optical lithography method defined line pattern.

[0017] 进一步地,所述侧墙材料层为氮化硅。 [0017] Further, the spacer layer is a silicon nitride material.

[0018] 进一步地,采用低压化学气相沉积方法或等离子体增强化学气相沉积方法进行所述淀积。 [0018] Further, using a low pressure chemical vapor deposition method or a plasma enhanced chemical vapor deposition method for the deposition.

[0019] 进一步地,所述干法刻蚀为各向异性干法刻蚀。 [0019] Further, the dry etching is anisotropic dry etching.

[0020]进一步地,米用 TMAH (Tetramethyl Ammonium Hydroxide,四甲基氢氧化铵)溶液进行所述湿法腐蚀;TMAH溶液浓度优选为25wt%,腐蚀温度优选为60°C。 [0020] Further, the wet etching performed with rice TMAH (Tetramethyl Ammonium Hydroxide, tetramethylammonium hydroxide) solution; solution of TMAH concentration is preferably 25wt%, the corrosion temperature is preferably 60 ° C.

[0021] 本发明的优点和积极效果如下: [0021] The advantages and positive effects of the present invention are as follows:

[0022] I)由氮化硅侧墙作掩膜刻蚀出的硅细线条粗糙度小,形貌好。 [0022] I) a silicon nitride spacers as a mask to etch silicon fine line roughness, good morphology. 多晶硅的干法刻蚀侧面较氧化硅、氮化硅陡直,由它形成的侧墙光滑度得到提高,再加上湿法腐蚀多晶硅较干法刻蚀更能彻底去除多晶硅,不会在侧墙残留造成线条粗糙。 Dry etching the polysilicon side than silicon oxide, silicon nitride steep, spacers formed by its smoothness is improved, together with the wet etching is dry etching the polysilicon is more completely removing the polysilicon, not the side wall residue caused by rough lines.

[0023] 2)利用侧墙技术可以制备尺寸小于20nm的线条,满足小尺寸器件关键工艺的要求。 [0023] 2) the line size of less than 20nm may be prepared using spacer technology to meet the requirements of the small size of critical process components.

[0024] 3)采用TMAH溶液湿法腐蚀多晶硅,操作简便,安全;并且不会引入金属离子,适用于集成电路制造工艺中。 [0024] 3) the wet etching using TMAH solution polysilicon, simple and safe operation; and do not introduce metal ions, suitable for integrated circuit fabrication process.

[0025] 4)工艺流程耗时短,可操作性强,适于工业生产。 [0025] 4) short time-consuming process, easy to operate, suitable for industrial production.

附图说明 BRIEF DESCRIPTION

[0026] 图I是本发明实施例的制备边缘粗糙度较小的细线条的方法的工艺流程图。 [0026] FIG. I is prepared embodiment of the present invention the edge roughness of the process flow diagram of a method of smaller fine line.

[0027] 图2是本发明实施例的制备细线条过程中各材料层结构示意图。 [0027] FIG. 2 is a schematic view of the structure of each layer of material during the preparation of thin lines of the embodiment of the present invention. 其中:1衬底材料;2—氧化娃;3一多晶娃;4一光刻I父;5一氮化娃;6一衬底材料系线条。 Wherein: a substrate material; 2- baby oxide; polymorph 3 a baby; I 4 a photolithography parent; 5 baby nitride; 6 a line-based material substrate.

具体实施方式 Detailed ways

[0028] 下面通过具体实施例,并配合附图,对本发明做详细的说明。 [0028] The following specific embodiments and the accompanying drawings, a detailed description of the invention.

[0029] 图I是本实施例的制备边缘粗糙度较小的细线条的方法的步骤流程图。 The steps of a method [0029] FIG. I is prepared according to the present embodiment of the edge roughness smaller fine line embodiment of a flowchart. 该流程可进一步概括为下面三个大步骤: The process may further be summarized into the following three major steps:

[0030] I)在衬底上淀积阻挡层和牺牲层,并定义线条的光刻图形。 [0030] I) deposition of a barrier layer and a sacrificial layer on the substrate, and defines the line lithography patterning.

[0031] 阻挡层材料为氧化硅,作用是在后续刻蚀牺牲层和腐蚀牺牲层时作衬底的阻挡层。 [0031] The barrier layer material is silicon oxide, is acting as a barrier layer during subsequent etching of the substrate and etching the sacrificial layer a sacrificial layer. 牺牲层材料为多晶硅,作为后续淀积侧墙的支撑层。 Sacrificial material is polysilicon, the sidewall spacer as a follow-deposited support layer. 具体工艺步骤包括: Specific process steps comprising:

[0032] a)淀积一层氧化硅阻挡层,阻挡后续刻蚀以及腐蚀; [0032] a) depositing a silicon oxide barrier layer, the barrier and subsequent etching etching;

[0033] b)淀积一层多晶硅薄膜; [0033] b) depositing a layer of polysilicon film;

[0034] c)在多晶硅上涂上一层光刻胶,光刻定义出细线条; [0034] c) coated on the polysilicon layer of photoresist, defining a fine line lithography;

[0035] d)干法刻蚀将图形转移到多晶硅薄膜上. [0035] d) dry etching to transfer the pattern on the polysilicon film.

[0036] 2)湿法腐蚀形成侧墙 [0036] 2) wet etching to form first spacers

[0037]目的是制备出后续刻蚀衬底硅所用侧墙。 [0037] The object is to prepare a silicon substrate is used in subsequent etching spacers. 侧墙作为刻蚀硅衬底的掩膜层,它的宽度直接决定了刻蚀出来的硅线条的尺寸。 Sidewall spacer as a mask, etch the silicon substrate, which directly determines the size of the width of the etched silicon out of the line. 具体工艺步骤如下: The specific process steps are as follows:

[0038] e)淀积一层一定厚度的氮化硅; [0038] e) depositing a layer of a certain thickness of the silicon nitride;

[0039] f)干法刻蚀氮化硅,形成侧墙; [0039] f) dry etching the silicon nitride, forming spacers;

[0040] g)湿法腐蚀多晶硅牺牲层,形成氮化硅侧墙掩膜层。 [0040] g) wet etching the sacrificial polysilicon layer, a silicon nitride spacer mask layer.

[0041] 3)干法刻蚀衬底材料,形成细线条 [0041] 3) dry-etching the substrate material, forming fine lines

[0042] 主要通过干法刻蚀,利用氮化硅侧墙作掩膜层,将线条转移到硅衬底材料,最终制备LER较小的细线条。 [0042] mainly by dry etching, using the silicon nitride layer spacer as a mask, the silicon substrate material is transferred to the line, the smaller fine line LER final preparation. 具体工艺步骤如下: The specific process steps are as follows:

[0043] h)干法刻蚀氧化硅阻挡层; [0043] h) dry-etching the silicon oxide barrier layer;

[0044] i)干法刻蚀硅衬底。 [0044] i) dry etching the silicon substrate.

[0045] 上述方法中,淀积氧化硅、多晶硅、氮化硅采用低压化学气相沉积方法,还可以采用等离子体增强化学气相沉积(PECVD),但沉积膜的质量不如低压化学气相沉积好。 [0045] The above process, the deposition of silicon oxide, polysilicon, silicon nitride using low pressure chemical vapor deposition method, may also be plasma enhanced chemical vapor deposition (PECVD), but not as good as the quality of the deposited film is good low pressure chemical vapor deposition. 定义光刻胶采用的是普通光学光刻即可,也可以采用更先进的光学光刻技术。 Definition of the photoresist used in ordinary photolithography can, it can be more advanced optical lithography. 刻蚀氧化硅、多晶硅、氮化硅和衬底材料采用的是各向异性干法刻蚀技术。 Etching the silicon oxide, polysilicon, silicon nitride and the substrate material used is an anisotropic dry etching. 湿法腐蚀多晶硅采用TMAH溶液,TMAH溶液浓度优选为25wt%,腐蚀温度优选为60°C ;此外还可以采用氢氧化钾(KOH)溶液等,但KOH有毒性,所以在工业生产中使用不多。 Wet etching polysilicon using a TMAH solution, a TMAH solution concentration is preferably 25wt%, the corrosion temperature is preferably 60 ° C; in addition can also be employed potassium hydroxide (KOH) solution or the like, but toxic KOH, used in industrial production so much .

[0046] 本实施例制备的细线条,小的边缘粗糙度是通过采用多晶硅牺牲层和湿法腐蚀多晶硅实现的。 [0046] This Example was prepared fine line, a small edge roughness by using a polysilicon layer and wet etching the sacrificial polysilicon achieved. 多晶硅的干法刻蚀侧面较氧化硅、氮化硅陡直,侧面形貌较好,后续经过淀积刻蚀形成的氮化硅侧墙也比较陡直。 Dry etching the side surface of the polysilicon than silicon oxide, silicon nitride steep side surface morphology preferably, after the subsequent deposition of the silicon nitride spacers formed by etching is relatively steep. 多晶硅牺牲层的去除采用TMAH溶液湿法腐蚀,TMAH对硅材料的腐蚀速率较高,且速率可通过调节腐蚀溶液的浓度和温度调节,并且它对氧化硅和氮化硅都有较高的选择比。 Removing the polysilicon sacrificial layer using a wet etching solution of TMAH, the higher the rate of TMAH etching the silicon material, and the rate may be adjusted by adjusting the concentration and temperature of the etching solution, silicon oxide and silicon nitride, and it has a high selectivity ratio. 较之干法刻蚀,湿法腐蚀多晶硅牺牲层反应更彻底,去除更干净。 Compared with dry etching, wet etching the polysilicon sacrificial layer react more thoroughly removed cleaner. 这样,侧墙的LER较小,刻蚀后的硅线条LER也较小。 Thus, the spacer is small LER, LER silicon lines after etching is small. 线条尺寸的控制则是通过形成尺寸较小的侧墙尺寸来实现。 The stripe size control is achieved by forming a sidewall spacer dimensions smaller size. 较高的牺牲层厚度和较薄的氮化硅厚度可以形成尺寸较小的侧墙尺寸,经过干法刻蚀,能将侧墙掩模图形转移到衬底硅材料,最终制备出20nm以下超细线条。 The higher the sacrificial layer thickness and the thickness of the thin silicon nitride sidewall spacers can be formed smaller size dimensions, subjected to dry etching, the mask pattern can be transferred to the sidewall silicon substrate, 20nm or less over the final preparation fine line.

[0047] 下面提供应用上述方法制备细线条的具体实例,但本发明不限于其中所提及的工艺参数。 [0047] The following examples provide specific application of the above method for producing fine line, but the present invention is not limited to the process parameters mentioned therein. 图2为制备过程中各材料层的示意图,结合该图具体说明如下: Figure 2 is a schematic view of layers of material preparation process, the following detailed description in conjunction with the drawing:

[0048] 实施例I : [0048] Example I:

[0049] I、在(100) /<110>体硅衬底上化学气相淀积一层氧化硅薄膜,厚度为200 A,如图2(a)所示。 [0049] I, the (100) / <110> silicon substrate body by chemical vapor deposition layer of silicon oxide film with a thickness of 200 A, FIG. 2 (a) shown in FIG.

[0050] 2、在氧化硅薄膜上化学气相淀积一层多晶硅薄膜,厚度为1500 A,如图2(b)所示; [0050] 2, a silicon oxide film on the chemical vapor deposition layer of polysilicon film with a thickness of 1500 A, shown in FIG. 2 (B);

[0051] 3、在多晶硅薄膜上涂光刻胶,如图2(c)所示; [0051] 3, photoresist is coated on the polycrystalline silicon thin film, FIG. 2 (c) below;

[0052] 4、光刻定义出将要作为牺牲层的区域,如图2(d)所示; [0052] 4, to be used as a lithographically-defined regions of the sacrificial layer, as shown in Figure 2 (d);

[0053] 5、各向异性干法刻蚀多晶硅薄膜,最终将光刻胶上的图形转移到多晶硅薄膜材料上,如图2(e)所示; [0053] 5, anisotropic dry etching polycrystalline silicon thin film on the photoresist pattern eventually transferred to the polycrystalline silicon thin film materials, as shown in FIG 2 (e) below;

[0054] 6、去掉光刻胶,如图2 (f)所示; [0054] 6, the photoresist is removed, FIG. 2 (f) below;

[0055] 7、在氧化硅薄膜和多晶硅薄膜的表面上化学气相淀积氮化硅,厚度为200A,如图2 (g)所示; [0055] 7, on the surface of the silicon oxide film and a polysilicon thin film chemical vapor deposition of silicon nitride, having a thickness of 200A, as shown in Figure 2 (g);

[0056] 8、各向异性干法刻蚀氮化硅,形成氮化硅侧墙,如图2 (h)所示; [0056] 8, anisotropic dry etching of silicon nitride, a silicon nitride spacers, as shown in FIG 2 (h) below;

[0057] 9、在25wt%,60°C的TMAH溶液中湿法腐蚀多晶硅,牺牲层被腐蚀掉,形成氮化硅硬掩膜,如图2 (i)所示; [0057] 9, the wet etching in the polysilicon TMAH solution 25wt%, 60 ° C, the sacrificial layer is etched, a silicon nitride hard mask, FIG. 2 (i) below;

[0058] 10、各向异性干法刻蚀氧化硅,如图2 (j)所示; [0058] 10, anisotropic dry etching of the silicon oxide, 2 (J);

[0059] 11、各向异性干法刻蚀硅衬底800A,形成硅细线条,如图2(k)所示; [0059] 11, anisotropic dry etching of the silicon substrate 800A, forming a silicon thin lines in FIG. 2 (k) as shown;

[0060] 12、热(170°C )的浓磷酸腐蚀氮化硅,如图2(1)所示; [0060] 12, the heat (170 ° C) concentrated phosphoric acid etching of silicon nitride, as shown in FIG. 2 (1);

[0061] 13、氢氟酸:水(体积比1:10)湿法腐蚀氧化硅至全片脱水,如图2(m)所示。 [0061] 13, hydrofluoric acid: water (volume ratio 1:10) wet etching the silicon oxide to the whole sheet dewatering, FIG. 2 (m) shown in FIG.

[0062] 实施例2 : [0062] Example 2:

[0063] 此例提供制备尺寸更小的细线条的工艺参数。 [0063] This example provides the preparation of smaller fine-line process parameters. 要制备出尺寸更小的细线条,可以将多晶硅牺牲层厚度增加。 To prepare smaller fine line, may increase the thickness of the polysilicon sacrificial layer. 这样在刻蚀氮化硅形成侧墙时,由于横向钻蚀更严重使得氮化硅硬掩模尺寸更小,最后制备的细线条尺寸也更小,能达IOnm以下。 Thus when etching the silicon nitride spacers, due to the lateral undercutting silicon nitride hard mask such that more serious smaller, the size of the last fine line also produced a smaller, less capable of IOnm. 具体步骤如下:[0064] I、在(100)/〈110〉体硅衬底上化学气相淀积一层氧化硅薄膜,厚度为200 A,如图2(a)所示。 Specific steps are as follows: [0064] I, the (100) / <110> silicon substrate body by chemical vapor deposition layer of silicon oxide film with a thickness of 200 A, FIG. 2 (a) shown in FIG.

[0065] 2、在氧化硅薄膜上化学气相淀积一层多晶硅薄膜,厚度为2000A,如图2 (b)所示; [0065] 2, a silicon oxide film on the chemical vapor deposition layer of polysilicon film, a thickness of 2000A, as shown in Figure 2 (B);

[0066] 3、在多晶硅薄膜上涂光刻胶,如图2 (C)所示; [0066] 3, photoresist is coated on the polycrystalline silicon thin film, FIG. 2 (C) below;

[0067] 4、光刻定义出将要作为牺牲层的区域,如图2(d)所示; [0067] 4, to be used as a lithographically-defined regions of the sacrificial layer, as shown in Figure 2 (d);

[0068] 5、各向异性干法刻蚀多晶硅薄膜,最终将光刻胶上的图形转移到多晶硅薄膜材料上,如图2(e)所示; [0068] 5, anisotropic dry etching polycrystalline silicon thin film on the photoresist pattern eventually transferred to the polycrystalline silicon thin film materials, as shown in FIG 2 (e) below;

[0069] 6、去掉光刻胶,如图2(f)所示; [0069] 6, the photoresist is removed, FIG. 2 (f) below;

[0070] 7、在氧化硅薄膜和多晶硅薄膜的表面上化学气相淀积氮化硅,厚度为200A,如图2 (g)所示; [0070] 7, on the surface of the silicon oxide film and a polysilicon thin film chemical vapor deposition of silicon nitride, having a thickness of 200A, as shown in Figure 2 (g);

[0071] 8、各向异性干法刻蚀氮化硅,形成氮化硅侧墙,如图2(h)所示; [0071] 8, anisotropic dry etching of silicon nitride, a silicon nitride spacers, as shown in FIG 2 (h) below;

[0072] 9、在25wt%,60°C的TMAH溶液中湿法腐蚀多晶硅,牺牲层被腐蚀掉,形成氮化硅硬掩膜,如图2 (i)所示; [0072] 9, the wet etching in the polysilicon TMAH solution 25wt%, 60 ° C, the sacrificial layer is etched, a silicon nitride hard mask, FIG. 2 (i) below;

[0073] 10、各向异性干法刻蚀氧化硅,如图2 (j)所示; [0073] 10, anisotropic dry etching of the silicon oxide, 2 (J);

[0074] 11、各向异性干法刻蚀硅衬底800A,形成硅细线条,如图2(k)所示; [0074] 11, anisotropic dry etching of the silicon substrate 800A, forming a silicon thin lines in FIG. 2 (k) as shown;

[0075] 12、热(170°C )的浓磷酸腐蚀氮化硅,如图2(1)所示; [0075] 12, the heat (170 ° C) concentrated phosphoric acid etching of silicon nitride, as shown in FIG. 2 (1);

[0076] 13、氢氟酸:水(I: 10)湿法腐蚀氧化硅至全片脱水,如图2 (m)所示。 [0076] 13, hydrofluoric acid: water (I: 10) wet etching the silicon oxide to the whole sheet dewatering, FIG. 2 (m) shown in FIG. 至此,可以得到LER较小的细线条。 At this point, you can get a smaller LER fine line.

[0077] 以上实施例仅用以说明本发明的技术方案而非对其进行限制,本领域的普通技术人员可以对本发明的技术方案进行修改或者等同替换,而不脱离本发明的精神和范围,本发明的保护范围应以权利要求所述为准。 [0077] The above embodiments are intended to illustrate the present invention and not to limit it, those of ordinary skill in the art may make modifications to the technical solutions of the present invention, or equivalent replacements without departing from the spirit and scope of the present invention, the scope of the invention should be the subject of the claims.

Claims (10)

1. 一种制备边缘粗糙度较小的细线条的方法,其步骤包括: 1)在衬底上淀积阻挡层和牺牲层; 2)在所述牺牲层上涂光刻胶,并定义线条的光刻图形; 3)采用干法刻蚀方法将所述光刻图形转移至所述牺牲层; 4)淀积侧墙材料层,并采用干法刻蚀方法形成侧墙; 5)湿法腐蚀侧墙内的牺牲层,形成侧墙掩膜层; 6)利用所述侧墙掩膜层,通过干法刻蚀将线条图形转移至衬底上,得到细线条。 A method of preparing edge roughness smaller fine line, comprising the steps of: 1) a barrier layer deposited on a substrate and the sacrificial layer; 2) coating a photoresist on the sacrificial layer, and define a line lithographic pattern; 3) a dry etching method using photolithography the pattern is transferred to the sacrificial layer; 4) depositing a spacer material layer, and forming spacers using a dry etching method; 5) wet etching the sacrificial layer in the sidewall, formed spacer mask layer; 6) using the sidewall spacer mask layer by dry etching the line pattern is transferred onto the substrate, to give a fine line.
2.如权利要求I所述的方法,其特征在于,所述衬底为硅衬底。 The method of claim I as claimed in claim 2, wherein said substrate is a silicon substrate.
3.如权利要求I所述的方法,其特征在于,所述阻挡层为氧化硅,所述牺牲层为多晶硅。 The method of claim I as claimed in claim 3, wherein said barrier layer is silicon oxide, the sacrificial layer is polysilicon.
4.如权利要求I所述的方法,其特征在于,采用普通光学光刻方法定义线条图形。 The method of claim I as claimed in claim 4, wherein the ordinary photolithography method defined line pattern.
5.如权利要求I所述的方法,其特征在于,所述侧墙材料层为氮化硅。 5. The method of claim I, wherein said spacer layer is a silicon nitride material.
6.如权利要求I所述的方法,其特征在于,采用低压化学气相沉积方法进行所述淀积。 The method of claim I as claimed in claim 6, characterized in that, using a low pressure chemical vapor deposition method for the deposition.
7.如权利要求I所述的方法,其特征在于,采用等离子体增强化学气相沉积方法进行所述淀积。 7. The method of claim I, wherein the plasma enhanced chemical vapor deposition method for the deposition.
8.如权利要求I所述的方法,其特征在于,所述干法刻蚀为各向异性干法刻蚀。 8. The method of claim I, wherein said dry etching is anisotropic dry etching.
9.如权利要求I所述的方法,其特征在于,采用TMAH溶液进行所述湿法腐蚀。 9. The method of claim I, wherein the use of the TMAH solution for wet etching.
10.如权利要求9所述的方法,其特征在于,所述TMAH溶液的浓度为25wt%,腐蚀温度为60。 10. The method according to claim 9, wherein the concentration of the TMAH solution is 25wt%, the corrosion temperature of 60. . .
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