JP6753526B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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Description
本願の発明に係る半導体装置の製造方法では、導波路の半導体レーザー側の端部で、基板と導波路層との間に設けられる第1導電性層が導波方向に分断される。このため、第1導電性層を通って半導体レーザーから導波路側に電流が漏れることを抑制できる。従って、消費電力を低減できる。
図1は、実施の形態1に係る半導体装置100の平面図である。半導体装置100は基板20を備える。基板20は、絶縁性基板である。基板20は、i−InPから形成される。半導体装置100は、基板20の上面に設けられ、レーザー光を発する半導体レーザー12を備える。また、半導体装置100は、半導体レーザー12が発するレーザー光を導波させる導波路16を備える。半導体装置100は光半導体素子である。
図9は、実施の形態2の半導体装置200の製造方法を説明する断面図である。実施の形態では、基板220の構造が実施の形態1と異なる。基板220の上面側には、エッチングストップ層238が設けられる。第1導電性層24は、エッチングストップ層238の上に設けられる。エッチングストップ層238は絶縁性のエピタキシャル成長層である。エッチングストップ層238は、i−InGaAsPから形成される。また、露出部218ではエッチングストップ層238が埋め込み層14から露出している。
図11は、実施の形態3の半導体装置300の断面図である。半導体装置300の分断領域23では、導波路16は断面視において保護絶縁膜340に取り囲まれる。本実施の形態に係る半導体装置300の製造方法では、分断領域23を形成した後に、CVD(Chemical Vapor Deposition)成膜法で導波路16の端部17に保護絶縁膜340を形成する。本実施の形態では、被覆性の良いCVD成膜法を用いることで、分断領域23で導波路16が保護絶縁膜340で取り囲まれる。このとき、導波路16の側面および裏面も保護絶縁膜340で覆われた構造が得られる。導波路16の裏面は導波路16の基板20と対向する面である。
図12は、実施の形態4の半導体装置400の断面図である。半導体装置400は、分断領域23で導波路層32と基板20との間を埋めるポリイミド442を備える。ポリイミド442は、半導体レーザー12、導波路16、埋め込み層14および露出部18を覆うように設けられる。本実施の形態に係る半導体装置400の製造方法は、半導体レーザー12、導波路16、埋め込み層14および露出部18にポリイミド442を塗布する工程を備える。ポリイミド442は塗布膜であるため、分断領域23において導波路層32と基板20との間はポリイミド442で埋められる。
Claims (10)
- 基板と、
前記基板の上面に設けられ、レーザー光を発する半導体レーザーと、
前記基板の上面に設けられた第1導電性層と、前記第1導電性層の上に設けられ前記レーザー光を導波させる導波路層と、を有する導波路と、
前記基板の上面に設けられ、前記半導体レーザーと前記導波路とを取り囲む埋め込み層と、
を備え、
前記導波路の前記半導体レーザーと接続される端部の両側には、前記埋め込み層が前記導波路の導波方向に分断されることで、前記基板が前記埋め込み層から露出した露出部が設けられ、
前記端部には、前記第1導電性層が前記導波方向に分断されている分断領域が設けられることを特徴とする半導体装置。 - 前記基板には、前記導波方向と垂直な方向の幅が前記導波路の幅よりも広い溝が、前記分断領域の直下に設けられることを特徴とする請求項1に記載の半導体装置。
- 前記基板の上面側には、エッチングストップ層が設けられ、
前記露出部では、前記エッチングストップ層が前記埋め込み層から露出していることを特徴とする請求項1に記載の半導体装置。 - 前記分断領域で、前記導波路は断面視において保護絶縁膜に取り囲まれることを特徴とする請求項1〜3の何れか1項に記載の半導体装置。
- 前記分断領域で、前記導波路層と前記基板との間を埋めるポリイミドを備えることを特徴とする請求項1〜3の何れか1項に記載の半導体装置。
- 基板の上面に、レーザー光を発する半導体レーザーを形成する工程と、
前記基板の上面に設けられた第1導電性層と、前記第1導電性層の上に設けられ前記レーザー光を導波させる導波路層と、を有する導波路を形成する工程と、
前記基板の上面に、前記半導体レーザーと前記導波路とを取り囲む埋め込み層を形成する工程と、
前記埋め込み層が前記導波路の導波方向に分断されるように、前記導波路の前記半導体レーザーと接続される端部の両側で前記埋め込み層の一部を除去し、前記基板が前記埋め込み層から露出した露出部を形成する工程と、
前記半導体レーザーと、前記導波路と、前記埋め込み層と、前記露出部と、を絶縁膜で覆う工程と、
前記絶縁膜に複数の開口を前記導波路の両側にそれぞれ設け、前記露出部を露出させる開口形成工程と、
前記絶縁膜をマスクとして、前記導波路層よりも前記第1導電性層に対してエッチングレートが大きいエッチング液を用いてウェットエッチングを行い、前記端部で前記第1導電性層の一部を除去し、前記第1導電性層が前記導波方向に分断された分断領域を前記端部に設けるエッチング工程と、
を備えることを特徴とする半導体装置の製造方法。 - 前記エッチング液は、前記導波路層よりも前記基板に対してエッチングレートが大きく、
前記エッチング工程では、前記導波方向と垂直な方向の幅が前記導波路の幅よりも広い溝が、前記基板の前記分断領域の直下に設けられることを特徴とする請求項6に記載の半導体装置の製造方法。 - 前記基板の上面側には、エッチングストップ層が設けられ、
前記開口形成工程では、前記エッチングストップ層と、前記第1導電性層と、を露出させるように前記複数の開口が設けられ、
前記エッチング液は、前記エッチングストップ層よりも前記第1導電性層に対してエッチングレートが大きいことを特徴とする請求項6に記載の半導体装置の製造方法。 - 前記分断領域で、前記導波路が断面視において保護絶縁膜で取り囲まれるように、CVD成膜法で前記保護絶縁膜を形成する工程を備えることを特徴とする請求項6〜8の何れか1項に記載の半導体装置の製造方法。
- 前記分断領域で、前記導波路層と前記基板との間をポリイミドで埋める工程を備えることを特徴とする請求項6〜8の何れか1項に記載の半導体装置の製造方法。
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