JP6701641B2 - 半導体モジュール - Google Patents
半導体モジュール Download PDFInfo
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- JP6701641B2 JP6701641B2 JP2015159813A JP2015159813A JP6701641B2 JP 6701641 B2 JP6701641 B2 JP 6701641B2 JP 2015159813 A JP2015159813 A JP 2015159813A JP 2015159813 A JP2015159813 A JP 2015159813A JP 6701641 B2 JP6701641 B2 JP 6701641B2
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- 239000004065 semiconductor Substances 0.000 title claims description 185
- 239000000758 substrate Substances 0.000 claims description 24
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 238000001816 cooling Methods 0.000 description 19
- 238000010586 diagram Methods 0.000 description 6
- 239000004020 conductor Substances 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000020169 heat generation Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000498 cooling water Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
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Description
また、本発明の一観点によれば、外部からの電流を裏面から入力するドレイン板と、絶縁板と、前記絶縁板のおもて面の中央部に設けられたゲート回路板と前記絶縁板のおもて面に前記ゲート回路板を取り囲んで設けられた回路板とを備え、前記ドレイン板のおもて面上に配置され、前記絶縁板の裏面側と前記ドレイン板が接合された積層基板と、ワイドバンドギャップ半導体により構成されたスイッチング素子を含み、おもて面にゲート電極とソース電極とを備え、裏面にドレイン電極を備え、前記ドレイン板のおもて面に配置され、前記ドレイン板と前記ドレイン電極が電気的に接続された第1半導体チップと、ダイオード素子を含み、おもて面にアノード電極を備え、裏面にカソード電極を備え、前記ドレイン板のおもて面のうち、前記第1半導体チップと前記積層基板との間に配置され、前記ドレイン板と前記カソード電極が電気的に接続された第2半導体チップと、ゲート配線層をおもて面に設け、ソース配線層を裏面に設け、前記ゲート配線層は、一端が前記第1半導体チップの前記ゲート電極に電気的に接続され、他端が前記ゲート回路板に電気的に接続されて、前記ソース配線層は、一端が前記第1半導体チップの前記ソース電極及び前記第2半導体チップの前記アノード電極にそれぞれ接続され、他端が前記回路板に電気的に接続されているプリント基板と、前記回路板上に配置され、前記第1半導体チップにより制御された前記電流を外部に出力するソース端子と、を有する半導体モジュールが提供される。
実施の形態の半導体モジュールについて、図1〜図3を用いて説明する。
図1は、実施の形態の半導体モジュールの上面図であり、図2は、実施の形態の半導体モジュールの断面図である。但し、図2(A)は、図1の一点鎖線Y1−Y1による断面図であり、図2(B)は、図1の一点鎖線X−Xによる断面図をそれぞれ示している。
また、半導体モジュール100は、第1半導体チップ410及び第2半導体チップ420と、積層基板310とを電気的に接続する接続部材であるプリント基板500及び導電ポスト511〜515を有する。さらに、ゲート回路板313aにはゲート端子330が、回路板313bには一対のソース端子320がそれぞれ配置されている。なお、ゲート端子330には、ゲート支柱部620を介してゲート接触子610が接続されている。また、ゲート接触子610は、導電性を備える弾性部材により構成されている。
以下、このような半導体モジュール100の各構成について図4〜図9を用いて詳細に説明する。
但し、図4(B)は、図4(A)における一点鎖線Y3−Y3における断面図である。図6(A)は、図5の矢視Aから見た図であり、図6(B)は、図5の矢視Bから見た図である。
次いで、図7〜図9に示されるように、第1半導体チップ410及び第2半導体チップ420と、積層基板310(ゲート回路板313a及び回路板313b)との間が接続部材(プリント基板500及び導電ポスト511〜515)で電気的に接続される。
図10は、実施の形態の半導体モジュールで構成される回路構成を示す図である。
図11は、実施の形態の半導体モジュールにおける電流の流れを示す図である。
なお、図11では、ケース700及び蓋600等の記載を省略し、電流の流れに関わる構成を記載している。また、図11は、図1の一点鎖線Y2−Y2における断面図をそれぞれ表している。さらに、図11(A)は、第1半導体チップ410(MOSFET)に対するゲートがオン時の、図11(B)は、第1半導体チップ410(MOSFET)に対するゲートをオフした直後の電流の流れをそれぞれ破線で示している。
なお、図13でも、図11(B)と同様に、図1の一点鎖線Y2−Y2における断面図をそれぞれ表している。また、ケース700及び蓋600等の記載を省略し、電流の流れに必要な構成を記載している。さらに、図13は、第1半導体チップ410に対するゲートをオフした直後の電流の流れをそれぞれ破線で示している。
参考例の半導体モジュールにおいて、第1半導体チップ410(MOSFET)のゲート電極への制御信号をオフにする。すると、ドレイン板200からソース端子320に印加されていた電圧が逆方向に印加されるようになるために、図13に示されるように、逆に印加された電圧の印加方向に沿って電流が流れ出す。ソース端子320からの電流は、回路板313bと、導電ポスト515と、プリント基板500のソース配線層530とを経由して、すべての電流が第1半導体チップ410(MOSFET)のボディダイオード412に入力される。第1半導体チップ410(MOSFET)に入力されたすべての電流は、ボディダイオード412を通電するため、第1半導体チップ410が発熱して、半導体モジュールの特性が低下してしまう。
200 ドレイン板
201,202 溝部
310 積層基板
311 金属板
312 絶縁板
313a ゲート回路板
313b 回路板
320 ソース端子
330 ゲート端子
410 第1半導体チップ
411 MOSFET
412 ボディダイオード
420 第2半導体チップ
421 ダイオード
500 プリント基板
511,512,513,514,515 導電ポスト
520 ゲート配線層
530 ソース配線層
600 蓋
610 ゲート接触子
700 ケース
800 冷却装置
Claims (8)
- 外部からの電流を裏面の中央部から入力するドレイン板と、
絶縁板と、前記絶縁板のおもて面に設けられた回路板とを備え、前記ドレイン板のおもて面上の中央部に配置され、前記絶縁板の裏面側と前記ドレイン板が接合された積層基板と、
ワイドバンドギャップ半導体により構成されたスイッチング素子を含み、おもて面にゲート電極とソース電極とを備え、裏面にドレイン電極を備え、前記ドレイン板のおもて面の周縁部に前記積層基板の1組の対向する一対の辺に沿って1列ずつ配置され、前記ドレイン板と前記ドレイン電極が電気的に接続された第1半導体チップと、
ダイオード素子を含み、おもて面にアノード電極を備え、裏面にカソード電極を備え、前記ドレイン板のおもて面のうち前記積層基板の前記一対の辺に沿って、前記第1半導体チップと前記積層基板との間に1列ずつ配置され、前記ドレイン板と前記カソード電極が電気的に接続された第2半導体チップと、
前記第1半導体チップの前記ソース電極と前記回路板とを電気的に接続し、前記第2半導体チップの前記アノード電極と前記回路板とを電気的に接続する接続部材と、
前記回路板上に配置され、前記第1半導体チップにより制御された前記電流を外部に出力するソース端子と、
を有する半導体モジュール。 - 前記第1半導体チップは、前記スイッチング素子に逆並列で接続されたボディダイオードを含む、
請求項1記載の半導体モジュール。 - 前記第2半導体チップの前記アノード電極から前記カソード電極への抵抗は、前記第1半導体チップの前記ボディダイオードの抵抗よりも小さい、
請求項2記載の半導体モジュール。 - 前記第1半導体チップの前記ゲート電極に入力される制御信号がオンからオフになると、
前記ソース端子から前記ドレイン板に電圧が印加される、
請求項1記載の半導体モジュール。 - 前記ソース端子からの電流が前記回路板と前記接続部材とを経由して、前記第2半導体チップの前記アノード電極に導通する、
請求項4記載の半導体モジュール。 - 前記接続部材は、プリント基板と、前記プリント基板に固定された導電ポストで構成される、
請求項1記載の半導体モジュール。 - 前記スイッチング素子は、炭化シリコンにより構成されている、
請求項1記載の半導体モジュール。 - 外部からの電流を裏面から入力するドレイン板と、
絶縁板と、前記絶縁板のおもて面の中央部に設けられたゲート回路板と前記絶縁板のおもて面に前記ゲート回路板を取り囲んで設けられた回路板とを備え、前記ドレイン板のおもて面上に配置され、前記絶縁板の裏面側と前記ドレイン板が接合された積層基板と、
ワイドバンドギャップ半導体により構成されたスイッチング素子を含み、おもて面にゲート電極とソース電極とを備え、裏面にドレイン電極を備え、前記ドレイン板のおもて面に配置され、前記ドレイン板と前記ドレイン電極が電気的に接続された第1半導体チップと、
ダイオード素子を含み、おもて面にアノード電極を備え、裏面にカソード電極を備え、前記ドレイン板のおもて面のうち、前記第1半導体チップと前記積層基板との間に配置され、前記ドレイン板と前記カソード電極が電気的に接続された第2半導体チップと、
ゲート配線層をおもて面に設け、ソース配線層を裏面に設け、前記ゲート配線層は、一端が前記第1半導体チップの前記ゲート電極に電気的に接続され、他端が前記ゲート回路板に電気的に接続されて、前記ソース配線層は、一端が前記第1半導体チップの前記ソース電極及び前記第2半導体チップの前記アノード電極にそれぞれ接続され、他端が前記回路板に電気的に接続されているプリント基板と、
前記回路板上に配置され、前記第1半導体チップにより制御された前記電流を外部に出力するソース端子と、
を有する半導体モジュール。
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