CN115039222A - 可自由配置的功率半导体模块 - Google Patents
可自由配置的功率半导体模块 Download PDFInfo
- Publication number
- CN115039222A CN115039222A CN202180011873.0A CN202180011873A CN115039222A CN 115039222 A CN115039222 A CN 115039222A CN 202180011873 A CN202180011873 A CN 202180011873A CN 115039222 A CN115039222 A CN 115039222A
- Authority
- CN
- China
- Prior art keywords
- semiconductor
- board
- power
- terminal
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 196
- 239000000758 substrate Substances 0.000 claims description 27
- 238000001465 metallisation Methods 0.000 claims description 15
- 239000002184 metal Substances 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000005245 sintering Methods 0.000 description 4
- 239000010949 copper Substances 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 230000003044 adaptive effect Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5381—Crossover interconnections, e.g. bridge stepovers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
- H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/32238—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8384—Sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/71—Means for bonding not being attached to, or not being formed on, the surface to be connected
- H01L24/72—Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1027—IV
- H01L2924/10272—Silicon Carbide [SiC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0254—High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
- H05K1/0262—Arrangements for regulating voltages or for using plural voltages
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/04—Assemblies of printed circuits
- H05K2201/042—Stacked spaced PCBs; Planar parts of folded flexible circuits having mounted components in between or spaced from each other
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10151—Sensor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10166—Transistor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10196—Variable component, e.g. variable resistor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/222—Completing of printed circuits by adding non-printed jumper connections
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Geometry (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Materials Engineering (AREA)
- Power Conversion In General (AREA)
- Combinations Of Printed Boards (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
一种功率半导体模块(10)包括:至少一个半导体板(16),包括至少两个半导体芯片(24),每个半导体芯片(24)具有两个功率电极(26,28);适配器板(14),在至少两个半导体芯片(24)上方附接至半导体板(16),适配器板(14)在背离半导体板(16)的一侧上针对每个半导体芯片(24)包括端子区域(46);其中,适配器板(14)在每个端子区域(46)中为与端子区域(46)相关的半导体芯片(24)的每个功率电极(26,28)提供功率端子(42);其中,每个功率端子(42)通过端子区域(46)下方的导电垂直柱(34,36)与半导体芯片(24)电连接。
Description
技术领域
本发明涉及电力电子领域。特别地,本发明涉及一种功率半导体模块。
背景技术
多芯片功率半导体模块通常针对确定的拓扑(诸如半桥配置)而设计,并且可能无法提取芯片个体信息,因为功率半导体芯片被并联连接和控制。复杂的拓扑需要通过使用各种单独的模块来实现。功率模块端子通常限于基本连接,可能无法提取芯片个体诊断信号(诸如板上温度和芯片电流)。
US2017077068A1示出了一种具有衬底和印刷电路板的半导体模块,芯片被结合至衬底上,印刷电路板通过导电柱与衬底连接。
US2019/150268A1示出了一种半导体模块。该半导体模块具有其上设置有开关元件的两个衬底,其通过垂直柱与上方电路板连接,电路板将两个衬底彼此连接。电路板包括连接至垂直柱的多个导电区域。
US2017/047923A1示出了一种具有衬底上半导体开关的功率半导体模块。半导体开关的一个电极通过柱与衬底上方的电路板连接。
US2017/112005A1涉及一种功率半导体模块,其包括通过可拆卸跳线连接的若干子模块。可拆卸跳线允许重新配置子模块中一个或多个功率半导体开关之间的连接。
发明内容
本发明的目的在于提供一种具有小占位面积和低杂散电感的可配置功率半导体模块。
该目的通过独立权利要求的主题来实现。另外的示例性实施例通过从属权利要求和以下描述变得显而易见。
本发明涉及一种功率半导体模块。半导体模块可以是将两个或更多半导体芯片彼此机械和电性互连,并且具有可以通过模块的壳体暴露的端子的器件。在这里和下文中,术语“功率”可以涉及半导体模块和/或半导体模块的组件处理大于10A的电流和/或大于100V的电压的能力。
根据本发明的实施例,功率半导体模块包括具有至少两个半导体芯片的至少一个半导体板,每个半导体芯片具有两个功率电极。半导体板可以是具有半导体芯片的衬底,半导体芯片结合至该衬底的金属化层。半导体板可以是印制电路板,半导体芯片附接至印制电路板。
半导体芯片可以是可控器件,诸如晶体管和/或晶闸管。半导体芯片中的一些也可以是二极管。半导体芯片可以基于Si或SiC或其它宽带隙材料。半导体芯片可以彼此并排地布置在半导体板中和/或可以基本上布置在一层中。
功率电极可以是发射极和集电极、或者源极和漏极。可控半导体芯片还可以包括控制电极,诸如栅电极。
根据本发明的实施例,功率半导体模块包括在至少两个半导体芯片上方连接到半导体板的适配器板,该适配器板在背离半导体板的一侧上针对每个半导体芯片包括端子区域。适配器板可以通过壳体附接到半导体板,和/或可以电连接至下方的半导体板。适配器板可以是印刷电路板,在一侧(外侧)包括端子,在相对侧(内侧)包括与半导体板的电气连接。
对于每个半导体芯片,端子区域可以布置在半导体区域上方。不同半导体芯片的端子区域可以相同地设计。端子区域可以提供用于单独连接到半导体芯片的每个电极或至少连接到功率电极的端子。半导体芯片可以在半导体板和适配器板中彼此电和/或电流隔离。仅端子的连接可以产生半导体芯片之间的电连接。
根据本发明的实施例,适配器板在每个端子区域提供针对与端子区域相关的半导体芯片的每个功率电极的功率端子。可选地,用于电连接至控制电极、功率电极和/或与半导体芯片相关的传感器的一个或多个辅助端子还可以设置在端子区域中。
通常,端子可以是导电元件,另外的导体可以附接到该导电元件。
适配器板可以布置在半导体芯片的顶部上和/或可以结合至半导体芯片的所有控制和传感器信号。适配器板可以实现灵活的拓扑配置和/或诊断信号提取。
根据本发明的实施例,与端子区域相关的半导体芯片的每个功率端子通过端子区域下方(和/或功率端子下方)的导电垂直柱与半导体芯片电连接。导电柱可以是细长的直金属体。垂直方向可以正交于由半导体板和/或适配器板的延伸限定的平面。垂直方向也可以正交于其中布置有半导体芯片的平面。垂直柱可以直接端接在芯片的功率电极上或由半导体板提供的导体区域上并电连接至功率电极。
通过端子区域,模块中的半导体芯片可以互连成所有需要的拓扑,诸如并联、串联、半桥等。互连可以用跳线和/或桥来实现。由于端子区域下方的垂直柱,模块可以设计得很紧凑,可以具有高功率密度,并且可以具有低杂散电感。
本文中,术语“下方”可以指端子区域沿垂直方向朝向半导体板的投影。当组件在投影区域中时,该组件可以被视作为在端子区域下方。
多芯片功率半导体模块可以提供每个半导体芯片的所有功率和可选控制电极的单独的连接,其中所有半导体芯片可以被布置成彼此电绝缘。这可以允许配置各种拓扑和/或转换器封装。在这种情况下,当还提供辅助端子时,这可以附加地允许先进的单芯片感测和控制。
不同拓扑的示例为其中几个半桥的中点为星形连接的交错拓扑、多相拓扑、半桥拓扑、全桥拓扑和/或诸如NPC桥的多级拓扑。自适应拓扑也是可能的,例如在操作期间具有受控并联,这可以用来优化与负载分布相关的效率。
根据本发明的实施例,适配器板在与端子区域相关的半导体芯片的端子区域中提供至少一个辅助端子,辅助端子连接至端子区域下方和/或辅助端子下方的导电垂直柱。辅助端子可以较功率端子具有更低的额定电流和/或可以更小。
根据本发明的实施例,与端子区域相关的半导体芯片包括控制电极,并且辅助端子中的一个通过其导电垂直柱与半导体芯片的控制电极电连接。垂直柱可以直接连接至半导体芯片的栅电极。
根据本发明的实施例,半导体板包括用于与端子区域相关的半导体芯片的传感器。传感器可以是温度传感器和电流传感器中的一种。温度传感器可以感测半导体芯片的温度。电流传感器(诸如片上电流镜)可以感测通过半导体芯片的负载电流。传感器可以布置在端子区域下方。辅助端子可以通过其导电垂直柱电连接至传感器。
根据本发明的实施例,辅助端子通过其导电垂直柱与和端子区域相关的半导体芯片的功率电极电连接。该辅助端子也可以通过适配器板与导电垂直柱连接,其也连接相应的功率端子和相应的功率电极。
根据本发明的实施例,功率端子中的每个具有至少两个插塞式连接器。插塞式连接器可以是公连接器或母连接器,其被设计成可以与另一插塞式连接器可逆地机械和电气连接。
适配器板可以包括用于将两个插塞式连接器互连的跳线连接器,插塞式连接器用于电连接不同半导体芯片的功率电极。跳线连接器可以被视作为跳线。
然而,不同芯片的功率端子也可以以结合互连的方式连接,诸如金属条、线和/或电缆,其可以被视作为桥和/或桥接互连。
根据本发明的实施例,功率端子、部分功率端子或全部功率端子布置在相应端子区域的外部区域中,其中,外部区域布置在适配器板的边缘处。可以包括一个或多个插塞式连接器的这部分功率端子,可用于连接功率半导体模块的端子。
根据本发明的实施例,至少一个辅助端子布置在端子区域的内部区域中,其中,外部区域布置在适配器板的边缘与内部区域之间。可以有第二外部区域或中间区域,其中也布置有部分功率端子。第二外部区域或中间区域可以布置在第一外部区域和内部区域之间。
内部区域和可选的第二外部区域可以被栅极驱动器板覆盖。栅极驱动器板则可以通过垂直互连与辅助端子连接。
栅极驱动器板可以覆盖第二外部区域,其中功率端子通过跳线和/或桥互连。通过栅极驱动器板,可以执行单芯片控制和/或诊断。控制信号可以施加到与控制电极互连的辅助端子。测量信号可以从与功率电极和/或传感器互连的辅助端子接收。
根据本发明的实施例,端子区域在适配器板上被布置成至少一行。此外,半导体芯片可以在端子区域下方布置成一行或多行。例如,两个行可以相对于功率半导体模块的中心垂直平面镜像对称地布置。
如何设计半导体板有若干可能的情况。例如,半导体板可以基于具有金属化层的衬底、基于印刷电路板和/或附接至基板的芯片封装来设计。
根据本发明的实施例,半导体板包括具有结构化的金属化层的衬底,至少两个半导体芯片结合至金属化层。衬底可以由聚合物和/或陶瓷制成,并且可以在一侧或两侧上覆盖金属化层。一个或多个单独的引线框也可以作为衬底。金属化层可以被结构化,即被划分成若干区域,其可用于连接和/或结合一个或多个半导体芯片和/或垂直柱。
根据本发明的实施例,垂直柱是引脚,其连接至适配器板,并按压在由半导体板提供的接触区域上。每个垂直柱的顶部也可以结合至半导体板的相应接触区域。接触区域可以是半导体芯片的电极本身,或者可以由金属化层的一部分提供。
适配器板可以是印刷电路板,具有结合至其衬底的引脚网格。引脚和/或垂直柱可以由引脚网格提供。引脚网格可以结合到半导体板。结合可以例如通过烧结、焊接或导电粘合剂结合来实现,例如通过引脚上粘合剂帽。
根据本发明的实施例,半导体板针对每个半导体芯片包括芯片级封装。每个芯片级封装可以包括至少一个半导体芯片、连接至半导体芯片的垂直柱(例如电镀通孔和再分布层)、以及其中嵌入有半导体芯片和垂直柱的模具或PCB封装。每个芯片级封装还可以提供结合区,垂直柱电连接至结合区,其中适配器板结合至芯片级封装的结合区。芯片级封装可以附接至模块的共同基板。结合区可以设置在芯片级封装的上表面上,其全部可以布置在相同平面上。
半导体芯片可以预装在顶侧上具有结合区的芯片级芯片封装中,适配器板可以例如通过焊接、烧结或导电粘合剂结合来结合至结合区。
根据本发明的实施例,适配器板和半导体板由多层电路板提供,其中嵌入有至少两个半导体芯片。多层电路板也可以单独提供半导体板。在这两种情况下,垂直柱可以被设置为多层电路板的通孔,该通孔可以穿过多层电路板的多个层。
多层电路板可以由多个聚合物层制成,在一侧或两侧之间和/或在一侧或两侧上具有导电层,其被层压在一起。在层压过程期间,半导体芯片可以被嵌入多层电路板中。
根据本发明的实施例,功率半导体模块包括附接至适配器板的栅极驱动器板,其中垂直引脚将栅极驱动器板与适配器板上的辅助端子互连。可以是印刷电路板的栅极驱动器板可以处理来自半导体芯片的测量信号和/或可以生成施加到半导体芯片的控制信号。栅极驱动器板可以附接至适配器板上/适配器板中。
根据本发明的实施例,栅极驱动器板仅覆盖端子区域的一部分功率端子,例如仅覆盖内部区域中的功率端子。例如,栅极驱动器板可以覆盖其中不同半导体芯片的功率端子被互连和/或布置有辅助端子的区域。
综上所述,功率半导体模块向模块的所有半导体芯片分别提供功率端子和可选的辅助端子。通过暴露的端子,在工厂和/或服务中每个半导体芯片可以被单独测试。
由于垂直柱,用最小的衬底面积可以达到最大的功率密度,可以不需要用于引线键合的空间,可以实现对称的热扩散和更好的可靠性。此外,垂直柱可以产生低电感和对称电磁设计。
本发明的这些和其它方面将从下文描述的实施例中变得显而易见,并且参考下文描述的实施例进行阐明。
附图说明
本发明的主题将在下文中参照附图中示出的示例性实施例进行更详细的说明。
图1示意性地示出了根据本发明的实施例的功率半导体模块的俯视图。
图2示意性地示出了根据本发明的另外的实施例的穿过功率半导体模块的截面图。
图3示意性地示出了根据本发明的实施例的功率半导体模块的一部分的俯视图。
图4示意性地示出了根据本发明的实施例的功率半导体模块的一部分的俯视图。
图5示意性地示出了根据本发明的另外的实施例的穿过功率半导体模块的截面图。
图6示意性地示出了根据本发明的另外的实施例的穿过功率半导体模块的截面图。
图7示意性地示出了根据本发明的另外的实施例的穿过功率半导体模块的截面图。
附图中使用的参考标记及其含义在参考标记列表中以摘要形式列出。原则上,相同的部件在图中具有相同的参考标记。
具体实施方式
图1示出了功率半导体模块10的俯视图,而图2示出了功率半导体模块10的截面图,其上附接有栅极驱动器板12。
如图2所示,模块10由栅极驱动器板12组成,栅极驱动器板12附接到适配器板14,适配器板14附接到半导体板16。
半导体板16可以包括具有一个或多个金属化层20、22的衬底18,诸如DBC(直接键合铜)衬底或IMS(绝缘金属衬底)。金属化层20可以被结构化成区域20a、20b、20c,这些区域相对于半导体板16彼此电隔离。在区域20a、20b、20c上,半导体芯片24与第一功率电极26结合。半导体芯片24中的每个的相对侧设置有第二功率电极28和控制电极30。例如,半导体芯片24可以是Si和/或SiC器件,诸如晶体管和/或晶闸管。
一个或多个传感器32可以并入和/或附接至半导体芯片24,例如,传感器32可以感测芯片24的温度和/或通过半导体芯片24的电流。该传感器32可以提供面对适配器板14的接触区域33。此外,电极28、30和区域20a、20b、20c的未被芯片24覆盖的部分可以被视作为面对适配器板14的接触区域。一个或多个传感器32可以是相应半导体芯片24的板载传感器,即可以集成到相应半导体芯片24中。
可以是印刷电路板(诸如金属芯PCB和/或柔性PCB)的适配器板14在面对半导体板16的一侧上包括导电垂直柱34、36、38、40。柱34、36、38、40可以将适配器板14和半导体板14的接触区域28、30、33电互连。
在相对侧(图1中所示),适配器板14包括功率端子42和辅助端子44。端子42、44被布置在端子区域46中,端子区域46被布置在相应半导体芯片24上方。在图1中,仅描绘了一个端子区域46和其中的端子。然而,如图所示,模块10具有端子区域46的两行48。
在每个端子区域46中,一个功率端子42可以通过一个或多个柱34与相应区域20a、20b、20c以及相应的功率电极26电连接。一个功率端子42可以通过一个或多个柱36与其它功率电极28直接电连接。辅助端子44可以通过柱38与控制电极30直接电连接。辅助端子44可以通过柱40与传感器32直接电连接。辅助端子44也可以通过适配器板14与功率电极28、30中的一个连接。
半导体芯片24可以通过将不同半导体芯片24的功率端子44互连的连接器50互连成不同拓扑。功率端子44可以包括插塞式连接器52,连接器50可以是可以插入这些插塞式连接器52中的跳线连接器。连接器50也可以是桥接器,其两端结合到功率端子42。通过连接器50,模块10内的半导体芯片可以被互连成不同的拓扑,诸如串联、并联、半桥等。
每个端子区域46可以划分为内部区域46a(其中布置有辅助端子44)、中间区域46b(其中布置有功率端子42的内部部分)和外部区域46c(其中布置有功率端子42的外部部分)。
外部区域46c可以设置在适配器板14的边缘处,并且端子42的外部部分(以及可选地,该外部部分中的插塞式连接器52)可以用于连接模块端子54与功率端子42(参见图2)。
外部区域46c和内部区域46a之间的中间区域46b中的端子42的内部部分(以及可选地,该部分中的插塞式连接器52)可以用于将半导体芯片24彼此互连。
在内部区域46a中,栅极驱动器板12可以与辅助端子44连接。
返回到图2,辅助端子可以包括压入式插座,从栅极驱动器板12伸出的引脚56可以插置其中。与垂直柱34、36、38、40类似,引脚56可以相对于板12、14、16垂直地对准,和/或可以从栅极驱动器板12的面对适配器板14的一侧伸出。在相对侧上,栅极驱动器板12可以包括诸如控制组件的栅极驱动器组件58、用于评估传感器信号的组件和/或诸如电容器和电阻器的无源元件。
栅极驱动器板12可以与适配器板14同样小,和/或可以仅在端子区域46的内部区域46a和中间区域46b中覆盖适配器板14。
图2还示出,适配器板14和半导体板16可以通过壳体60机械互连,壳体60可以粘接到适配器板14和半导体板16。
图3和图4示出了不同端子区域46的可能性。通常,功率端子42的插塞式连接器52可以布置成两个平行的行。此外,辅助端子44可以布置成平行于功率端子42的一行。如图1和图4所示,辅助端子44可以布置在两个功率端子44之外。然而,如图3所示,辅助端子44也可以布置在功率端子之间。
图5示出了栅极驱动器板12可以具有带引脚56的压入式引脚阵列,其可以压入到设计为压入式插座的辅助端子44中。此外,垂直柱34、36、38、40可以是引脚,它们被压靠在接触区域28、30、33上。该引脚34、36、38、40可以具有适于烧结到相应接触区域28、30、33的顶部和/或帽62。例如,引脚34、36、38、40可以由Cu制成,其烧结帽由Ag制成。
模块10的适配器板14、半导体板16和壳体60之间的内部可以用凝胶填充和/或用树脂灌封。
图5的模块可以通过首先拾取芯片24并将芯片24放置在衬底18上,然后将它们烧结到金属化层20来制造。之后,可以对准适配器板14,并且可以烧结引脚34、36、38、40。之后,可以封装模块。最后,例如,模块10的用户可以压入跳线连接器50和栅极驱动器板12。这种制造方式可以具备的优点是可以不需要嵌入和/或晶圆级处理。
图6示出了其中半导体板16包括针对每个半导体芯片24的芯片级封装64的功率半导体模块10。为了形成半导体板16,芯片级封装64可以结合到具有结构化的金属化层20的衬底18。
每个芯片级封装64可以包括一个或多个半导体芯片24、连接至半导体芯片24的垂直柱34、36、38、40(诸如电镀铜通孔和/或再分布层)以及其中嵌入有半导体芯片24和垂直柱34、36、38、40的模具和/或PCB封装66。每个芯片级封装还可以包括引线框和/或基板65,用于将芯片封装结合到模块10的衬底18。
在另一侧,每个芯片级封装64可以提供结合区68,垂直柱34、36、38、40电连接至结合区68。适配器板14则可以结合到芯片封装64的结合区68。
例如,在每个芯片级封装64中,可以容纳具有板载温度和电流传感器的反向导通IGBT、具有续流二极管的IGBT或者两个并联的SiC MOSFET。
图5的模块可以通过首先拾取芯片级封装64并将芯片级封装64放置在衬底18上,然后将它们结合到金属化层20来制造。之后,可以对准适配器板14并结合到结合区。最后,例如模块10的用户可以压入跳线连接器50和栅极驱动器板12。这种制造方式可以具备的优点是不存在与对准板有关的精确问题,而且可以不需要进一步封装。
图6示出了其中通过多层电路板70提供适配器板14和半导体板16的功率半导体模块10,在多层电路板70中嵌入有至少两个半导体芯片24。多层电路板70可以由金属基板22和引线框72制成,半导体芯片24被结合在引线框72上。聚合物绝缘层可以布置在金属层22、72之间。垂直柱34、36、38、40可以由多层电路板70的通孔和金属化轨道提供。
图6的模块可以通过拾取半导体芯片24并将半导体芯片24放置在引线框72中,并且将它们烧结到引线框72来制造。之后,可以在金属层22、72之间布置PCB层,并且可以包括适配器板14的金属层以及其它组件,诸如通孔34、36、38、40、端子42、44等,并且可以将全部组件层压在一起。最后,例如模块10的用户可以压入跳线连接器50和栅极驱动器板12。这种制造方式可以具备的优点是模块可以具有相当小的高度,而且可以只需要少数的结合步骤和制造步骤。此外,可以不需要额外的衬底18。
尽管已在附图和前述描述中详细示出和描述了本发明,但是这些图示和描述应被视作为说明性或示例性的,而非限制性的;本发明不限于公开的实施例。通过对附图、公开内容和所附权利要求的研究,本领域技术人员可以理解并实现公开的实施例的其它变体,并且实践所要求保护的发明。在权利要求中,词语“包括”不排除其它元件或步骤,并且不定冠词“一”或“一个”不排除多个。单个处理器或控制器或其它单元可以实现权利要求中所述的多个项目的功能。仅在相互不同的从属权利要求中列举特定措施的事实并不表明这些措施的组合不能发挥优势。权利要求中的任何参考标记都不应被解释为限制范围。
参考标记列表
10 功率半导体模块
12 栅极驱动器板
14 适配器板
16 半导体板
18 衬底
20 金属化层
20a,20b,20c 区域
22 金属化层
24 半导体芯片
26 第一功率电极
28 第二功率电极
30 控制电极
32 传感器
33 接触区域
34 垂直柱
36 垂直柱
38 垂直柱
40 垂直柱
42 功率端子
44 辅助端子
46 端子区域
46a,46b,46c 区域
48 行
50 连接器
52 插塞式连接器
54 模块端子
56 引脚
58 栅极驱动器组件
60 壳体
62 顶部、帽
64 芯片级封装
65 引线框和/或基板
66 模具和/或PCB封装
68 结合区
70 多层电路板
72 引线框。
Claims (14)
1.一种功率半导体模块(10),包括:
至少一个半导体板(16),所述至少一个半导体板包括至少两个半导体芯片(24),每个所述半导体芯片(24)具有两个功率电极(26,28);
适配器板(14),在所述至少两个半导体芯片(24)上方附接至所述半导体板(16),所述适配器板(14)在背离所述半导体板(16)的一侧上针对每个所述半导体芯片(24)包括端子区域(46);
其中,所述适配器板(14)在每个所述端子区域(46)中为与所述端子区域(46)相关的所述半导体芯片(24)的每个所述功率电极(26,28)提供功率端子(42);
其中,每个所述功率端子(42)通过所述端子区域(46)下方的导电垂直柱(34,36)与所述半导体芯片(24)电连接;
其中,所述功率端子(42)中的每个具有至少两个插塞式连接器(52);
其中,所述适配器板(14)包括用于将两个所述插塞式连接器(52)互连的跳线连接器(50),所述插塞式连接器用于电连接不同半导体芯片(24)的功率电极(26,28)。
2.根据权利要求1所述的功率半导体模块(10),
其中,所述适配器板(14)在与所述端子区域(46)相关的所述半导体芯片(24)中的至少一个半导体芯片的所述端子区域(46)中,提供至少一个辅助端子(44),所述辅助端子(44)连接至所述端子区域(46)下方的导电垂直柱(38,40)。
3.根据权利要求2所述的功率半导体模块(10),
其中,与所述端子区域(46)相关的所述半导体芯片(24)中的至少一个半导体芯片包括控制电极(30),并且所述辅助端子(44)中的一个通过其导电垂直柱(38)与所述半导体芯片(24)的所述控制电极(30)电连接。
4.根据权利要求2或3所述的功率半导体模块(10),
其中,所述半导体板(16)包括针对与所述端子区域(46)相关的所述半导体芯片(24)中的至少一个半导体芯片的传感器(32);
其中,辅助端子(44)通过其导电垂直柱(40)电连接至所述传感器(32)。
5.根据权利要求4所述的功率半导体模块(10),
其中,所述传感器(32)是温度传感器和电流传感器中的一种。
6.根据权利要求2至5中任一项所述的功率半导体模块(10),
其中,辅助端子(44)通过导电垂直柱(34,36)与和所述端子区域(46)相关的所述半导体芯片(24)中的至少一个半导体芯片的功率电极(26,28)电连接。
7.根据前述权利要求中任一项所述的功率半导体模块(10),
其中,功率端子(42)被布置在相应的端子区域(46)的外部区域(46c)中,其中,所述外部区域(46c)被布置在所述适配器板(14)的边缘处。
8.根据权利要求7所述的功率半导体模块(10),
其中,至少一个辅助端子(44)被布置在所述端子区域(46)的内部区域(46a)中,其中,所述外部区域(46c)被布置在所述适配器板(14)的边缘与所述内部区域(46a)之间。
9.根据前述权利要求中任一项所述的功率半导体模块(10),
其中,所述端子区域(46)在所述适配器板(14)上布置成至少一行(48)。
10.根据前述权利要求中任一项所述的功率半导体模块(10),
其中,所述半导体板(16)包括具有结构化的金属化层(20)的衬底(18),所述至少两个半导体芯片(24)被结合至所述金属化层。
11.根据权利要求10所述的功率半导体模块(10),
其中,所述垂直柱(34,36)是连接至所述适配器板(14)的引脚,使得所述引脚按压在由所述半导体板(16)提供的接触区域(28,30,33)上;
其中,每个所述垂直柱(34,36)的顶部结合至所述半导体板(16)的相应的接触区域(28,30,33)。
12.根据权利要求1至9中任一项所述的功率半导体模块(10),
其中,所述半导体板(16)针对每个半导体芯片(24)包括芯片级封装(64);
其中,每个芯片级封装(64)包括至少一个半导体芯片(24)、连接至所述半导体芯片(24)的所述垂直柱(34,36)以及其中嵌入有所述半导体芯片(24)和所述垂直柱(34,36)的模具封装(66);
其中,每个芯片级封装(64)提供结合区(68),所述垂直柱(34,36)电连接至所述结合区;
其中,所述适配器板(14)结合至所述芯片级封装(64)的所述结合区(68)。
13.根据权利要求1至9中任一项所述的功率半导体模块(10),
其中,所述适配器板(14)和所述半导体板(16)由多层电路板(70)提供,所述多层电路板中嵌入有至少两个所述半导体芯片(24);
其中,所述垂直柱(34,36)是所述多层电路板(70)的通孔。
14.根据前述权利要求中任一项所述的功率半导体模块(10),还包括:
附接至所述适配器板(14)的栅极驱动器板(12),其中,垂直引脚将所述栅极驱动器板(12)与所述适配器板(14)上的辅助端子(44)互连;
其中,所述栅极驱动器板(12)仅覆盖所述端子区域(46)的所述功率端子(42)的部分。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP20154510.0 | 2020-01-30 | ||
EP20154510 | 2020-01-30 | ||
PCT/EP2021/052004 WO2021152021A1 (en) | 2020-01-30 | 2021-01-28 | Free configurable power semiconductor module |
Publications (1)
Publication Number | Publication Date |
---|---|
CN115039222A true CN115039222A (zh) | 2022-09-09 |
Family
ID=69423064
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202180011873.0A Pending CN115039222A (zh) | 2020-01-30 | 2021-01-28 | 可自由配置的功率半导体模块 |
Country Status (5)
Country | Link |
---|---|
US (1) | US20230116118A1 (zh) |
EP (1) | EP4097761B1 (zh) |
JP (1) | JP2023512274A (zh) |
CN (1) | CN115039222A (zh) |
WO (1) | WO2021152021A1 (zh) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102021208770A1 (de) | 2021-08-11 | 2023-02-16 | Zf Friedrichshafen Ag | Halbbrücke für einen Inverter zum Betreiben eines Elektrofahrzeugantriebs, Leistungsmodul umfassend mehrere Halbbrücken, Inverter, Verfahren zum Herstellen eines Inverters |
DE102021208767A1 (de) | 2021-08-11 | 2023-02-16 | Zf Friedrichshafen Ag | Halbbrücke für einen Inverter zum Betreiben eines Elektrofahrzeugantriebs, Leistungsmodul umfassend mehrere Halbbrücken, Inverter, Verfahren zum Herstellen eines Inverters |
DE102021208772B4 (de) | 2021-08-11 | 2024-05-16 | Zf Friedrichshafen Ag | Halbbrücke für einen Inverter zum Betreiben eines Elektrofahrzeugantriebs, Leistungsmodul umfassend mehrere Halbbrücken, Inverter, Verfahren zum Herstellen eines Inverters |
DE102022209564A1 (de) | 2022-09-13 | 2023-07-06 | Zf Friedrichshafen Ag | Leistungsmodul und verfahren zum montieren eines leistungsmoduls |
DE102022211926A1 (de) | 2022-11-10 | 2024-05-16 | D + L Dubois + Linke Gesellschaft mit beschränkter Haftung | Schweißgerät |
DE102022213006A1 (de) | 2022-12-02 | 2024-06-13 | Zf Friedrichshafen Ag | Leistungsmodul für einen Wandler mit separater Leiterplatte zur Steuersignalführung |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE112014002405T5 (de) | 2013-05-16 | 2016-05-19 | Fuji Electric Co., Ltd | Halbleitervorrichtung |
DE112015000156T5 (de) | 2014-04-14 | 2016-06-16 | Fuji Electric Co., Ltd. | Halbleitervorrichtung |
JP6701641B2 (ja) | 2015-08-13 | 2020-05-27 | 富士電機株式会社 | 半導体モジュール |
US9839146B2 (en) | 2015-10-20 | 2017-12-05 | Cree, Inc. | High voltage power module |
EP3555914B1 (en) * | 2016-12-16 | 2021-02-03 | ABB Schweiz AG | Power semiconductor module with low gate path inductance |
-
2021
- 2021-01-28 JP JP2022546497A patent/JP2023512274A/ja active Pending
- 2021-01-28 CN CN202180011873.0A patent/CN115039222A/zh active Pending
- 2021-01-28 EP EP21701349.9A patent/EP4097761B1/en active Active
- 2021-01-28 US US17/795,970 patent/US20230116118A1/en active Pending
- 2021-01-28 WO PCT/EP2021/052004 patent/WO2021152021A1/en unknown
Also Published As
Publication number | Publication date |
---|---|
US20230116118A1 (en) | 2023-04-13 |
JP2023512274A (ja) | 2023-03-24 |
EP4097761B1 (en) | 2024-06-26 |
WO2021152021A1 (en) | 2021-08-05 |
EP4097761A1 (en) | 2022-12-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP4097761B1 (en) | Freely configurable power semiconductor module | |
JP7162013B2 (ja) | Dc端子の同軸配列を有するハーフブリッジモジュール | |
US9147649B2 (en) | Multi-chip module | |
US9275930B2 (en) | Circuit device and method of manufacturing the same | |
US10636732B2 (en) | Power module based on multi-layer circuit board | |
US10950516B2 (en) | Resin encapsulated power semiconductor module with exposed terminal areas | |
US7466020B2 (en) | Power module | |
US20130140684A1 (en) | Semiconductor Device Assembly Utilizing a DBC Substrate | |
US9468087B1 (en) | Power module with improved cooling and method for making | |
US8450837B2 (en) | Circuit device having an improved heat dissipitation, and the method of manufacturing the same | |
KR20140032923A (ko) | 와이어리스 모듈 | |
CN110190034B (zh) | 包括具有经由开口安装的芯片和部件的载体的封装 | |
CN110753996B (zh) | 功率电子设备模块 | |
US9129960B2 (en) | Semiconductor device and manufacturing method thereof | |
US10170401B2 (en) | Integrated power module | |
CN113140530A (zh) | 包括连接到流体热沉的半导体封装的电子模块 | |
WO2018007062A1 (en) | Low-inductance power module design | |
CN112582386B (zh) | 功率模块及其制备方法、电器设备 | |
CN115443531A (zh) | 功率模组及其制造方法、转换器和电子设备 | |
CN110148566B (zh) | 一种堆叠结构的智能功率模块及其制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20240112 Address after: Zurich, SUI Applicant after: Hitachi Energy Co.,Ltd. Address before: Swiss Baden Applicant before: Hitachi energy Switzerland AG |
|
TA01 | Transfer of patent application right |