JP6690252B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP6690252B2
JP6690252B2 JP2016010826A JP2016010826A JP6690252B2 JP 6690252 B2 JP6690252 B2 JP 6690252B2 JP 2016010826 A JP2016010826 A JP 2016010826A JP 2016010826 A JP2016010826 A JP 2016010826A JP 6690252 B2 JP6690252 B2 JP 6690252B2
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Prior art keywords
wiring member
diode
conductive member
semiconductor device
semiconductor chip
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JP2016010826A
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JP2017130621A (ja
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知紘 西村
知紘 西村
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Priority to JP2016010826A priority Critical patent/JP6690252B2/ja
Priority to US15/376,543 priority patent/US10199347B2/en
Publication of JP2017130621A publication Critical patent/JP2017130621A/ja
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Description

本発明は、半導体装置に関する。
半導体装置は、複数のパワー半導体素子を含み、電力変換装置、または、スイッチング装置として利用されている。半導体装置は、例えば、ＩＧＢＴ（Insulated Gate Bipolar Transistor）、ＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）等を含む半導体チップが接続されて、スイッチング装置として機能することができる。
特に、近年になって炭化シリコン（ＳｉＣ）がＭＯＳＦＥＴの構成材料として良く利用されている。炭化シリコンから構成されるＭＯＳＦＥＴでは、その素子構造上、内部に寄生ダイオードが作り込まれてしまう。このようなＭＯＳＦＥＴを動作させて、寄生ダイオードに電流が流れ続けると、ＳｉＣウェハあるいはＳｉＣエピタキシャル層、またはその両方に基底面転位（Basal Plane Dislocation : BPD）を起点として積層欠陥（Stacking Fault : SF）が成長してしまう。これにより、ＭＯＳＦＥＴのオン抵抗が上昇してしまい、ＭＯＳＦＥＴの信頼性が低下してしまうことが知られている（例えば、非特許文献１参照）。
そこで、一般的には、炭化シリコンのＭＯＳＦＥＴに対して、炭化シリコンからなるショットキーバリアダイオード（Schottky Barrier Diode : SBD）のような還流ダイオードを並列接続することで、ＭＯＳＦＥＴの寄生ダイオードに対する電流の流入を減少させることが可能となる。これにより、ＭＯＳＦＥＴ内の積層欠陥の成長が抑制されるようになる。
なお、上記の積層欠陥の成長はＩＧＢＴの素子構造においても生じる。
M.Skowronski and S.Ha、"Degradation of hexagonal silicon-carbide-based bipolar devices"、Journal of Applied Physics、2006、Vol.99、011101
しかしながら、炭化シリコンから構成されるＭＯＳＦＥＴと還流ダイオードとを並列接続したとしても、ＭＯＳＦＥＴへの逆導通電流はＭＯＳＦＥＴの寄生ダイオードと還流ダイオードとに分流されてしまう。すなわち、依然として、寄生ダイオードへの電流の流入が生じてしまい、ＭＯＳＦＥＴのオン抵抗が上昇してしまい、ＭＯＳＦＥＴの信頼性が低下してしまうおそれがある。なお、逆導通電流とはソース電極からドレイン電極方向へ流入する電流である。
本発明は、このような点を鑑みてなされたものであり、寄生ダイオードへの電流の流入が低減された半導体装置を提供することを目的とする。
本発明の一観点によれば、ソース電極をおもて面に備える半導体チップと、アノード電極をおもて面に備えるダイオードと、絶縁板と、前記絶縁板のおもて面に形成され、前記半導体チップ及び前記ダイオードが配置される第１導電部材と、前記絶縁板のおもて面に形成され、前記ソース電極からの出力信号が導通する第２導電部材と、を備える積層基板と、前記ソース電極と前記第２導電部材とを電気的に接続する第１配線部材と、前記アノード電極と前記第２導電部材とを電気的に接続し、前記第１配線部材よりも表面積が広い第２配線部材と、を有する半導体装置が提供される。
また、本発明の一観点によれば、おもて面にソース電極を備える半導体チップと、おもて面にアノード電極を備えるダイオードと、絶縁板と、前記絶縁板のおもて面に形成され、前記半導体チップ及び前記ダイオードが配置される第１導電部材と、前記絶縁板のおもて面に形成され、前記ソース電極からの出力信号が導通する第２導電部材と、を備える積層基板と、前記ソース電極と前記第２導電部材とを電気的に接続する第１配線部材と、前記アノード電極と前記第２導電部材とを電気的に接続し、前記第１配線部材よりも電気抵抗が小さい第２配線部材と、を有する半導体装置が提供される。
開示の技術によれば、半導体チップのオン抵抗の上昇を抑制して、信頼性の低下を抑えることができる。
第１の実施の形態の半導体装置を示す上面図である。 第１の実施の形態の半導体装置を示す側面図である。 第１の実施の形態の半導体装置で構成される回路構成を示す図である。 第２の実施の形態の半導体装置を示す上面図である。
以下、実施の形態について図面を用いて説明するが、以下の実施形態は特許請求の範囲にかかる発明を限定するものではない。また、実施形態の中で説明されている特徴の組み合わせのすべてが発明の解決手段に必須であるとは限らない。
［第１の実施の形態］
第１の実施の形態の半導体装置について、図１及び図２を用いて説明する。
図１は、第１の実施の形態の半導体装置を示す上面図である。
図２は、第１の実施の形態の半導体装置を示す側面図である。
但し、図２（Ａ）は、図１の矢視Ｙから見た場合の側面図であり、図２（Ｂ）は、図１の矢視Ｘから見た場合の側面図である。
半導体装置１００は、放熱ベース１１０と、放熱ベース１１０上に配置された積層基板１２０と、積層基板１２０上に配置された半導体チップ１３０及びダイオード１４０とを有する。さらに、半導体装置１００は、積層基板１２０と半導体チップ１３０並びにダイオード１４０とを電気的に接続する第１配線部材１５０、第２配線部材１６０及び第３配線部材１７０と、積層基板１２０に電気的に接続されている第１，第２，第３外部端子１８１，１８２，１８３とを有する。
放熱ベース１１０は、熱伝導率が高い、例えば、銅（Ｃｕ）、アルミニウム（Ａｌ）、アルミ炭化ケイ素（Ａｌ−ＳｉＣ）等により構成されている。
積層基板１２０は、例えば、セラミックス等の絶縁板１２１と、絶縁板１２１のおもて面に形成された、パターン化された第１，第２，第３導電部材１２２ａ，１２２ｂ，１２２ｃと、絶縁板１２１の裏面に形成された第４導電部材１２３とを備える。
半導体チップ１３０は、ＭＯＳＦＥＴの素子構造を含み、ソース電極１３１と、ゲート電極１３２とをおもて面に備え、ドレイン電極を裏面に備えている。また、ＭＯＳＦＥＴは、例えば、炭化シリコン、窒化ガリウム等のワイドバンドギャップ半導体により構成されている。このような半導体チップ１３０は、絶縁耐量が高く、高周波かつ高温で動作可能である。また、半導体チップ１３０は、積層基板１２０の第２導電部材１２２ｂ上にドレイン電極がはんだ等の接合材料を介して電気的に接続されて配置されている。また、半導体チップ１３０は、ＭＯＳＦＥＴに対して、その内部構造内に、寄生ダイオードが並列接続されるように形成されている。
ダイオード１４０は、例えば、ショットキーバリアダイオードであって、アノード電極１４１をおもて面に、カソード電極を裏面にそれぞれ備えている。また、ダイオード１４０もまた、炭化シリコン、窒化ガリウム等のワイドバンドギャップ半導体により構成されている。このようなダイオード１４０も同様に、絶縁耐量が高く、高周波かつ高温で動作可能である。また、ダイオード１４０は、積層基板１２０の第２導電部材１２２ｂ上にカソード電極がはんだ等の接合材料を介して電気的に接続されて配置されている。
第１配線部材１５０は、半導体チップ１３０のソース電極１３１と、積層基板１２０の第１導電部材１２２ａとを電気的に接続する。第１配線部材１５０は、金（Ａｕ）、銀（Ａｇ）、銅、アルミニウム、鉄（Ｆｅ）のうち少なくとも一種により構成されている。また、第１配線部材１５０は、ソース電極１３１と第１導電部材１２２ａとに対して、はんだ、金属粒子含有ペースト等を用いて接合され、または、超音波接合により接合されている。第１配線部材１５０は、図１及び図２に図示するように、板状の部材により逆Ｕ字状に構成されているが、これに限らず、ワイヤのような柱状の部材で構成しても構わない。
第２配線部材１６０は、ダイオード１４０のアノード電極１４１と、積層基板１２０の第１導電部材１２２ａとを電気的に接続する。第２配線部材１６０は、金、銀、銅、アルミニウム、鉄のうち少なくとも一種により構成されている。また、第２配線部材１６０は、アノード電極１４１と第１導電部材１２２ａとに対して、はんだ、金属粒子含有ペースト等を用いて接合され、または、超音波接合により接合されている。第２配線部材１６０は、図１及び図２に図示するように、板状の部材により逆Ｕ字状に構成されているが、これに限らず、ワイヤのような柱状の部材で構成しても構わない。また、第２配線部材１６０は、第１配線部材１５０よりもその表面積が広くなっている。つまり、表皮効果を考慮した場合、第２配線部材１６０の電流が導通する表面積は、第１配線部材１５０のその表面積よりも広くなっている。第１の実施の形態では、第２配線部材１６０は、第１配線部材１５０と同じ厚さであるために、第１配線部材１５０よりも幅が広くなっている。
第３配線部材１７０は、半導体チップ１３０のゲート電極１３２と、積層基板１２０の第３導電部材１２２ｃとを電気的に接続する。第３配線部材１７０は、金、銀、銅、アルミニウム、鉄のうち少なくとも一種により構成されている。また、第３配線部材１７０は、ゲート電極１３２と第３導電部材１２２ｃとに対して、はんだ、金属粒子含有ペースト等を用いて接合され、または、超音波接合により接合されている。第３配線部材１７０は、図１及び図２に図示するように、板状の部材により逆Ｕ字状に構成されているが、これに限らず、ワイヤのような柱状の部材で構成しても構わない。
第１外部端子１８１は、一端が外部負荷の負極に電気的に接続されて、他端が積層基板１２０の第１導電部材１２２ａの端部に電気的に接続されている。第１外部端子１８１は、第１配線部材１５０と第１導電部材１２２ａとを導通した、半導体チップ１３０のソース電極１３１から出力された出力信号を出力する。
第２外部端子１８２は、一端が外部負荷の正極に電極に電気的に接続されて、他端が積層基板１２０の第２導電部材１２２ｂの端部に電気的に接続されている。第２外部端子１８２は、外部から入力された入力信号が第２導電部材１２２ｂを導通して半導体チップ１３０のドレイン電極とダイオード１４０のカソード電極とにそれぞれ入力する。
第３外部端子１８３は、一端が制御信号を入力する電極に電気的に接続されて、他端が積層基板１２０の第３導電部材１２２ｃの端部に電気的に接続されている。第３外部端子１８３は、外部から入力された制御信号が、第３導電部材１２２ｃと第３配線部材１７０とを経由して、半導体チップ１３０のゲート電極１３２に入力する。
このような構成を有する半導体装置１００は、第１，第２，第３外部端子１８１，１８２，１８３の一端が突出するように各構成が樹脂（図示を省略）等の絶縁性の材料で封止されて構成される。
次に、このような半導体装置１００で構成される回路構成と信号の流れについて図３（並びに図１）を用いて説明する。
図３は、第１の実施の形態の半導体装置で構成される回路構成を示す図である。
半導体装置１００では、半導体チップ１３０のＭＯＳＦＥＴ（Ｑ）と、ダイオード１４０（Ｄ１）とが並列に接続されている。また、半導体チップ１３０のＭＯＳＦＥＴ（Ｑ）には、寄生ダイオードとして、ダイオードＤ２が形成されている。ダイオードＤ２は、半導体チップ１３０のＭＯＳＦＥＴ（Ｑ）に対して並列に接続されている。
そして、半導体装置１００では、第１外部端子１８１に外部負荷の負極が、第２外部端子１８２に外部負荷の正極がそれぞれ接続され、第３外部端子１８３には外部から制御信号が入力される。
したがって、第２外部端子１８２から入力された入力信号は、第２導電部材１２２ｂを経由して、半導体チップ１３０のＭＯＳＦＥＴ（Ｑ）のドレイン電極に入力される。半導体チップ１３０のＭＯＳＦＥＴ（Ｑ）は、第３外部端子１８３から第３導電部材１２２ｃと第３配線部材１７０とを経由してゲート電極１３２に制御信号が入力される。半導体チップ１３０（Ｑ）は、当該制御信号に応じて、ソース電極１３１から出力信号を出力する。出力信号は、第１配線部材１５０と第１導電部材１２２ａとを経由して、第１外部端子１８１から出力される。すなわち、信号は第２外部端子１８２側から入り、第１外部端子１８１側へ流れる。
このような半導体装置１００において、第１外部端子１８１側から第２外部端子１８２側へ流れる逆導通電流が生じると、当該逆導通電流は、第１導電部材１２２ａを導通して、第１配線部材１５０と第２配線部材１６０とに分岐する。
ここで、表皮効果を考慮した場合、第２配線部材１６０では電流が導通する表面積は、第１配線部材１５０の表面積よりも広くなっており、第２配線部材１６０は第１配線部材よりも表面積が広くなっている。また、半導体装置１００では、ワイドバンドギャップ半導体からなる半導体チップ１３０のＭＯＳＦＥＴ（Ｑ）とダイオード１４０（Ｄ１）により構成されていることから高周波による動作が実現可能である。このように、第２配線部材１６０では、表面積が大きく、高周波による信号が導通することにより表皮効果が生じるため、第２配線部材１６０の電気抵抗は、第１配線部材１５０の電気抵抗よりも見かけ上低くなる。そして、第１外部端子１８１側からの逆導通電流は、第１配線部材１５０よりも第２配線部材１６０に多く流れるようになる。したがって、第１配線部材１５０に流れる逆導通電流が減少するため、半導体チップ１３０のダイオードＤ２に流れる逆導通電流も減少し、ＳｉＣウェハあるいはＳｉＣエピタキシャル層、またはその両方に基底面転位を起点とした積層欠陥の成長が抑制される。その結果、ＭＯＳＦＥＴ（Ｑ）のオン抵抗の上昇も抑制されて、半導体チップ１３０の信頼性の低下も抑えられる。
なお、第２配線部材１６０では、既述の通り、金、銀、銅、アルミニウム、鉄のうち少なくとも一種により構成されている。これらの材質を用いることにより、第２配線部材１６０は表皮効果がより生じやすくなる。
上記半導体装置１００では、ソース電極１３１をおもて面に備える半導体チップ１３０と、アノード電極１４１をおもて面に備えるダイオード１４０と、ソース電極１３１からの出力信号が導通する第１導電部材１２２ａとを有する。半導体装置１００は、さらに、ソース電極１３１と第１導電部材１２２ａとを電気的に接続する第１配線部材１５０と、アノード電極１４１と第１導電部材１２２ａとを電気的に接続し、表面積が、第１配線部材１５０よりも広い第２配線部材１６０と、を有する。これにより、逆導通電流が第１配線部材１５０よりも第２配線部材１６０に多く流れるようになる。したがって、第１配線部材１５０に流れる逆導通電流が減少するため、半導体チップ１３０の寄生ダイオードに流れる逆導通電流も減少し、半導体チップ１３０内部の積層欠陥の成長が抑制される。その結果、半導体チップ１３０のオン抵抗の上昇も抑制されて、半導体チップ１３０並びに半導体装置１００の信頼性の低下も抑えられる。
［第２の実施の形態］
第２の実施の形態では、半導体装置に生じた逆導通電流を半導体チップ側ではなくダイオード側に多く流入させるために、第１の実施の形態とは異なる方法について、図４（並びに図３）を用いて説明する。
図４は、第２の実施の形態の半導体装置を示す上面図である。
なお、第２の実施の形態の半導体装置２００は、第４配線部材２６０以外は、第１の実施の形態の半導体装置１００と同じ構成であって、同じ符号を付している。また、半導体装置２００の回路構成も、図３と同様である。
第４配線部材２６０は、その電気抵抗率が第１配線部材１５０の電気抵抗率よりも小さい材質が適用されている。例えば、第１配線部材１５０がアルミニウムで構成される場合には、第４配線部材２６０は、アルミニウムよりも電気抵抗率が小さい銅により構成される。
すなわち、第４配線部材２６０では、その抵抗が第１配線部材１５０の抵抗よりも小さいために、第１外部端子１８１側から第２外部端子１８２側へ流れる逆導通電流は、第１配線部材１５０よりも第４配線部材２６０に多く流れるようになる。したがって、第１配線部材１５０に流れる逆導通電流が減少するため、半導体チップ１３０のダイオードＤ２に流れる逆導通電流も減少し、半導体チップ１３０内の積層欠陥の成長が抑制される。その結果、ＭＯＳＦＥＴ（Ｑ）のオン抵抗の上昇も抑制されて、半導体チップ１３０並びに半導体装置２００の信頼性の低下も抑えられる。
なお、上述の第１および第２の実施形態の説明において、ＭＯＳＦＥＴを用いて実施した場合について説明したが、ＭＯＳＦＥＴの代わりにＩＧＢＴを用いて実施してもよい。その場合、上記説明中の、「ソース電極」が「エミッタ電極」に対応し、「ドレイン電極」が「コレクタ電極」に対応する。
１００ 半導体装置
１１０ 放熱ベース
１２０ 積層基板
１２１ 絶縁板
１２２ａ 第１導電部材
１２２ｂ 第２導電部材
１２２ｃ 第３導電部材
１２３ 第４導電部材
１３０ 半導体チップ
１３１ ソース電極
１３２ ゲート電極
１４０ ダイオード
１４１ アノード電極
１５０ 第１配線部材
１６０ 第２配線部材
１７０ 第３配線部材
１８１ 第１外部端子
１８２ 第２外部端子
１８３ 第３外部端子
２６０ 第４配線部材

Claims (5)

  1. ソース電極をおもて面に備える半導体チップと、
    アノード電極をおもて面に備えるダイオードと、
    絶縁板と、前記絶縁板のおもて面に形成され、前記半導体チップ及び前記ダイオードが配置される第１導電部材と、前記絶縁板のおもて面に形成され、前記ソース電極からの出力信号が導通する第２導電部材と、を備える積層基板と、
    前記ソース電極と前記第２導電部材とを電気的に接続する第１配線部材と、
    前記アノード電極と前記第２導電部材とを電気的に接続し、前記第１配線部材よりも表面積が広い第２配線部材と、
    を有する半導体装置。
  2. 前記半導体チップ及び前記ダイオードは、ワイドバンドギャップ半導体により構成されている、
    請求項１に記載の半導体装置。
  3. 前記ワイドバンドギャップ半導体は、炭化シリコン、窒化ガリウムである、
    請求項２に記載の半導体装置。
  4. 前記第２配線部材とは、金、銀、銅、アルミニウム、鉄のうち少なくとも一種により構成されている、
    請求項１乃至３のいずれかに記載の半導体装置。
  5. おもて面にソース電極を備える半導体チップと、
    おもて面にアノード電極を備えるダイオードと、
    絶縁板と、前記絶縁板のおもて面に形成され、前記半導体チップ及び前記ダイオードが配置される第１導電部材と、前記絶縁板のおもて面に形成され、前記ソース電極からの出力信号が導通する第２導電部材と、を備える積層基板と、
    前記ソース電極と前記第２導電部材とを電気的に接続する第１配線部材と、
    前記アノード電極と前記第２導電部材とを電気的に接続し、前記第１配線部材よりも電気抵抗が小さい第２配線部材と、
    を有する半導体装置。
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