JP6622343B2 - 炭化ケイ素半導体デバイス及びその製造方法 - Google Patents
炭化ケイ素半導体デバイス及びその製造方法 Download PDFInfo
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- JP6622343B2 JP6622343B2 JP2018053913A JP2018053913A JP6622343B2 JP 6622343 B2 JP6622343 B2 JP 6622343B2 JP 2018053913 A JP2018053913 A JP 2018053913A JP 2018053913 A JP2018053913 A JP 2018053913A JP 6622343 B2 JP6622343 B2 JP 6622343B2
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
101 第1の面
110 ソースゾーン
120 本体領域
128 接触部分
130 ドリフト構造
131 低濃度にドープされたドリフトゾーン
132 電流拡散ゾーン
140 シールド領域
150 トレンチ構造
151 第1のセグメント
152 第2のセグメント
155 ゲート電極
156 分離誘電体
157 補助電極
158 ゲート導体構造
159 フィールド誘電体
161、162 ストライプ部分
190 メサ部分
310 第1の負荷電極
500 半導体デバイス
700 炭化ケイ素基板
701 処理面
720 本体層
730 ドリフト層構造
750 トレンチ
759 誘電体スペーサ
792 補助材料
1501 第1のトレンチ構造
1502 第2のトレンチ構造
1571 埋込部分
1572 接続部分
1575 インタフェース層
1581 第1の接続部分
1582 第2の接続部分
1583 第3の接続部分
Claims (23)
- 第1の面から炭化ケイ素半導体本体内に延在するトレンチ構造であって、前記トレンチ構造の下部の補助電極と、前記補助電極と前記第1の面との間に配置されたゲート電極とを含むトレンチ構造と、
前記トレンチ構造の前記下部の前記補助電極に隣接し、ドリフト構造と第1のpn接合を形成するシールド領域と、
を含み、前記補助電極が、前記シールド領域と低オーミック接触する、半導体デバイス。 - 前記補助電極が、前記第1の面から前記トレンチ構造の前記下部まで延在する接続部分を含む、請求項1に記載の半導体デバイス。
- 前記ゲート電極を含む前記トレンチ構造の第1のセグメントが、前記トレンチ構造の水平長手方向に沿って前記接続部分を含む第2のセグメントと交互に存在し、前記水平長手方向が、前記第1の面と平行である、請求項2に記載の半導体デバイス。
- 第1の負荷電極と前記第1の面との間にゲート導体構造をさらに含み、前記ゲート導体構造が、前記トレンチ構造内の前記ゲート電極の分離した部分を接続する、請求項1〜3の何れか一項に記載の半導体デバイス。
- 前記ゲート導体構造が、前記ゲート電極に直接隣接する第1の接続部分と、前記トレンチ構造の隣り合うトレンチ構造間の前記炭化ケイ素半導体本体のメサ部分の上の第2の接続部分と、前記第1及び第2の接続部分の隣り合う接続部分を横方向に接続する第3の接続部分とを含む、請求項4に記載の半導体デバイス。
- 前記トレンチ構造がグリッドを形成する、請求項1〜3の何れか一項に記載の半導体デバイス。
- 前記トレンチ構造のストライプ部分間に形成されたメサ部分の水平断面が、矩形、ひし形、及び六角形の内の1つである、請求項6に記載の半導体デバイス。
- 前記シールド領域が、前記トレンチ構造の前記下部の前記補助電極の下に配置される、請求項1〜7の何れか一項に記載の半導体デバイス。
- 前記トレンチ構造が、前記ゲート電極及び前記補助電極を分離する分離誘電体を含む、請求項1〜8の何れか一項に記載の半導体デバイス。
- 前記ドリフト構造と第2のpn接合を形成し、及び前記第1の面と本体領域との間に形成されたソースゾーンと第3のpn接合を形成する本体領域をさらに含む、請求項1〜9の何れか一項に記載の半導体デバイス。
- 前記ソースゾーン及び前記本体領域が、前記第1の面に直接隣接する、請求項10に記載の半導体デバイス。
- 前記第1の面に沿って、前記ソースゾーンが、前記本体領域の接触部分を水平に取り囲む、請求項10又は11に記載の半導体デバイス。
- 前記ドリフト構造が、低濃度にドープされたドリフトゾーン、及び前記本体領域と前記ドリフトゾーンとの間の電流拡散ゾーンを含み、前記電流拡散ゾーンが、横方向に前記シールド領域と隣接し、及び前記シールド領域が、前記ドリフトゾーンに隣接する、請求項10〜12の何れか一項に記載の半導体デバイス。
- 前記補助電極が、前記シールド領域に隣接する金属インタフェース層を含む、請求項1〜13の何れか一項に記載の半導体デバイス。
- 第1の面から炭化ケイ素半導体本体内に延在し、並びに、それぞれトレンチ構造の第1の側壁から反対側の第2の側壁へと延在する第1及び第2のセグメントを含む、前記トレンチ構造と、
前記第1のセグメント内に形成され、及び前記トレンチ構造の下部において前記炭化ケイ素半導体本体から誘電的に絶縁されたゲート電極と、
前記第2のセグメントに形成された補助電極と、
前記トレンチ構造の前記下部の前記補助電極と隣接し、及び前記炭化ケイ素半導体本体のドリフト構造と第1のpn接合を形成するシールド領域と、
前記補助電極及び前記ドリフト構造を分離するフィールド誘電体と、
を含み、前記補助電極が、前記シールド領域と低オーミック接触する、半導体デバイス。 - 前記第1のセグメントが、第1のトレンチ構造に形成され、及び前記第2のセグメントが、第2のトレンチ構造に形成される、請求項15に記載の半導体デバイス。
- 前記第1のセグメント及び前記第2のセグメントが、前記トレンチ構造の水平長手方向に沿って交互に存在し、前記水平長手方向が、前記第1の面と平行である、請求項16に記載の半導体デバイス。
- 前記ドリフト構造と第2のpn接合を形成し、及びソースゾーンと第3のpn接合を形成する本体領域をさらに含み、前記ソースゾーンが、前記第1の面と前記本体領域との間に形成される、請求項15〜17の何れか一項に記載の半導体デバイス。
- 前記ドリフト構造が、低濃度にドープされたドリフトゾーン、及び前記本体領域と前記ドリフトゾーンとの間の電流拡散ゾーンを含み、前記電流拡散ゾーンが、横方向に前記シールド領域に隣接し、及び前記シールド領域が、前記ドープされたドリフトゾーンに直接隣接する、請求項18に記載の半導体デバイス。
- 炭化ケイ素デバイスの製造方法であって、
ドリフト層構造と第2のpn接合を形成する本体層を含む炭化ケイ素基板の処理面にトレンチを形成するステップであって、前記本体層は、前記処理面と前記ドリフト層構造との間に存在し、及び前記トレンチが、前記ドリフト層構造を露出させることと、
前記トレンチの下部を通してドーパントを注入することによって、前記ドリフト層構造と第1のpn接合を形成するシールド領域を形成することと、
前記トレンチの側壁上に誘電体スペーサを形成することと、
前記トレンチの下部セクションに補助電極の埋込部分を形成することであって、前記埋込部分が、前記シールド領域と低オーミック接触する、埋込部分を形成することと、
を含む方法。 - 前記埋込部分を形成することが、高濃度にドープされた多結晶シリコンを堆積することを含む、請求項20に記載の方法。
- 選択的な酸化物成長によって、前記埋込部分の露出面上に分離誘電体を形成することをさらに含む、請求項21に記載の方法。
- 前記トレンチを補助材料で充填し、及び/又は覆い、並びに、前記トレンチの前記下部を通して注入された前記ドーパントを活性化するため、及び/又は注入損傷をアニールするために前記炭化ケイ素基板を加熱することをさらに含む、請求項20〜22の何れか一項に記載の方法。
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