JP6621708B2 - 半導体装置、半導体装置の製造方法 - Google Patents

半導体装置、半導体装置の製造方法 Download PDF

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JP6621708B2
JP6621708B2 JP2016105603A JP2016105603A JP6621708B2 JP 6621708 B2 JP6621708 B2 JP 6621708B2 JP 2016105603 A JP2016105603 A JP 2016105603A JP 2016105603 A JP2016105603 A JP 2016105603A JP 6621708 B2 JP6621708 B2 JP 6621708B2
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wiring
shield
layer
shield body
sealing resin
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JP2017212377A (ja
JP2017212377A5 (https=
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健 宮入
健 宮入
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to US15/587,834 priority patent/US9991228B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/423—Shielding layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
    • H10W42/261—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons characterised by their shapes or dispositions
    • H10W42/273—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons characterised by their shapes or dispositions the arrangements being between laterally adjacent chips, e.g. walls between chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
    • H10W42/261—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons characterised by their shapes or dispositions
    • H10W42/276—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons characterised by their shapes or dispositions the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
    • H10W42/281—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons characterised by their materials
    • H10W42/287—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons characterised by their materials materials for magnetic shielding, e.g. ferromagnetic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/652—Cross-sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/014—Manufacture or treatment using batch processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/10—Configurations of laterally-adjacent chips

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP2016105603A 2016-05-26 2016-05-26 半導体装置、半導体装置の製造方法 Active JP6621708B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2016105603A JP6621708B2 (ja) 2016-05-26 2016-05-26 半導体装置、半導体装置の製造方法
US15/587,834 US9991228B2 (en) 2016-05-26 2017-05-05 Semiconductor device with electromagnetic shield

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2016105603A JP6621708B2 (ja) 2016-05-26 2016-05-26 半導体装置、半導体装置の製造方法

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JP2017212377A JP2017212377A (ja) 2017-11-30
JP2017212377A5 JP2017212377A5 (https=) 2019-03-07
JP6621708B2 true JP6621708B2 (ja) 2019-12-18

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Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI566339B (zh) * 2014-11-11 2017-01-11 矽品精密工業股份有限公司 電子封裝件及其製法
CN107424974A (zh) * 2016-05-24 2017-12-01 胡迪群 具有埋入式噪声屏蔽墙的封装基板
US10804119B2 (en) * 2017-03-15 2020-10-13 STATS ChipPAC Pte. Ltd. Method of forming SIP module over film layer
US10629542B2 (en) 2018-04-05 2020-04-21 Samsung Electro-Mechanics Co., Ltd. Electronic device module
US10790238B2 (en) 2018-05-10 2020-09-29 Samsung Electro-Mechanics Co., Ltd. Electronic device module and method of manufacturing the same
KR20190129650A (ko) 2018-05-10 2019-11-20 삼성전기주식회사 전자 소자 모듈 및 그 제조 방법
KR102592329B1 (ko) 2018-06-26 2023-10-20 삼성전자주식회사 반도체 패키지 제조 방법
US10629518B2 (en) * 2018-08-29 2020-04-21 Nxp Usa, Inc. Internally-shielded microelectronic packages and methods for the fabrication thereof
US10755979B2 (en) * 2018-10-31 2020-08-25 Ningbo Semiconductor International Corporation Wafer-level packaging methods using a photolithographic bonding material
US11071196B2 (en) * 2019-04-05 2021-07-20 Samsung Electro-Mechanics Co., Ltd. Electronic device module and method of manufacturing electronic device module
WO2020250425A1 (ja) * 2019-06-14 2020-12-17 株式会社 東芝 半導体装置
US11362041B2 (en) * 2019-12-19 2022-06-14 Amkor Technology Japan, Inc. Semiconductor devices including shielding layer and methods of manufacturing semiconductor devices
CN114868245A (zh) * 2019-12-27 2022-08-05 株式会社村田制作所 模块
JP2021125525A (ja) * 2020-02-04 2021-08-30 キオクシア株式会社 半導体パッケージおよびその製造方法
US11626337B2 (en) * 2020-05-19 2023-04-11 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and methods of manufacturing semiconductor devices
CN112701089A (zh) * 2020-09-10 2021-04-23 成都芯源系统有限公司 集成电路封装结构、集成电路封装单元及相关制造方法
CN112908984A (zh) * 2021-01-18 2021-06-04 上海先方半导体有限公司 一种带有散热片的ssd堆叠封装结构及其制作方法
EP4040483A3 (en) 2021-02-04 2022-10-26 Murata Manufacturing Co., Ltd. Electronic component with internal shielding
US11869848B2 (en) * 2021-08-11 2024-01-09 STATS ChipPAC Pte. Ltd. Semiconductor device and method of stacking devices using support frame
CN114206090B (zh) * 2021-11-30 2024-04-16 四川天邑康和通信股份有限公司 一种能够有效解决pon/全光网关发热和屏蔽信号互绕的方法
TWI840976B (zh) * 2022-09-29 2024-05-01 海華科技股份有限公司 電磁屏蔽封裝結構與其製造方法、及電子組件

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006100302A (ja) * 2004-09-28 2006-04-13 Sharp Corp 高周波モジュールおよびその製造方法
JP4489575B2 (ja) 2004-12-17 2010-06-23 新光電気工業株式会社 半導体装置及びその製造方法
JP2006294701A (ja) * 2005-04-06 2006-10-26 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
DE602006012571D1 (de) * 2005-04-21 2010-04-15 St Microelectronics Sa Vorrichtung zum Schutz einer elektronischen Schaltung
CN101300911B (zh) * 2005-11-28 2010-10-27 株式会社村田制作所 电路模块以及制造电路模块的方法
JP4650244B2 (ja) * 2005-12-02 2011-03-16 株式会社村田製作所 回路モジュールおよびその製造方法
US7626247B2 (en) * 2005-12-22 2009-12-01 Atmel Corporation Electronic package with integral electromagnetic radiation shield and methods related thereto
JP4424449B2 (ja) * 2007-05-02 2010-03-03 株式会社村田製作所 部品内蔵モジュール及びその製造方法
JP2009218484A (ja) * 2008-03-12 2009-09-24 Tdk Corp 電子モジュール、および電子モジュールの製造方法
KR101711045B1 (ko) * 2010-12-02 2017-03-02 삼성전자 주식회사 적층 패키지 구조물
US8835226B2 (en) * 2011-02-25 2014-09-16 Rf Micro Devices, Inc. Connection using conductive vias
JP5861260B2 (ja) * 2011-03-10 2016-02-16 日本電気株式会社 半導体装置の製造方法及び半導体装置
KR20120131530A (ko) * 2011-05-25 2012-12-05 삼성전자주식회사 반도체 장치 및 그 제조 방법
KR20140023112A (ko) * 2012-08-17 2014-02-26 삼성전자주식회사 반도체 패키지를 포함하는 전자 장치 및 그 제조 방법
JP5767268B2 (ja) * 2013-04-02 2015-08-19 太陽誘電株式会社 回路モジュール及びその製造方法
WO2015194435A1 (ja) * 2014-06-20 2015-12-23 株式会社村田製作所 回路モジュール及びその製造方法
US9570406B2 (en) * 2015-06-01 2017-02-14 Qorvo Us, Inc. Wafer level fan-out with electromagnetic shielding
US10043761B2 (en) * 2015-10-19 2018-08-07 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof

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