JP6557701B2 - 半導体装置パッケージ及びその製造方法 - Google Patents

半導体装置パッケージ及びその製造方法 Download PDF

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JP6557701B2
JP6557701B2 JP2017091536A JP2017091536A JP6557701B2 JP 6557701 B2 JP6557701 B2 JP 6557701B2 JP 2017091536 A JP2017091536 A JP 2017091536A JP 2017091536 A JP2017091536 A JP 2017091536A JP 6557701 B2 JP6557701 B2 JP 6557701B2
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semiconductor device
isolation layer
device package
interconnect layer
layer
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JP2017204635A5 (enExample
JP2017204635A (ja
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天賜 陳
天賜 陳
光雄 陳
光雄 陳
聖民 王
聖民 王
育穎 李
育穎 李
▲ゆ▼慈 彭
▲ゆ▼慈 彭
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日月光半導体製造股▲ふん▼有限公司
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
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  • Manufacturing & Machinery (AREA)
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Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109075151B (zh) 2016-04-26 2023-06-27 亚德诺半导体国际无限责任公司 用于组件封装电路的机械配合、和电及热传导的引线框架
US10049893B2 (en) * 2016-05-11 2018-08-14 Advanced Semiconductor Engineering, Inc. Semiconductor device with a conductive post
JP2019040924A (ja) * 2017-08-22 2019-03-14 新光電気工業株式会社 配線基板及びその製造方法と電子装置
US10741482B2 (en) * 2017-12-29 2020-08-11 Advanced Semiconductor Engineering, Inc. Semiconductor device package
US10497635B2 (en) 2018-03-27 2019-12-03 Linear Technology Holding Llc Stacked circuit package with molded base having laser drilled openings for upper package
US11735570B2 (en) * 2018-04-04 2023-08-22 Intel Corporation Fan out packaging pop mechanical attach method
TWI672791B (zh) * 2018-05-07 2019-09-21 財團法人工業技術研究院 晶片封裝結構及其製造方法
US11410977B2 (en) 2018-11-13 2022-08-09 Analog Devices International Unlimited Company Electronic module for high power applications
US11477559B2 (en) * 2019-07-31 2022-10-18 Advanced Semiconductor Engineering, Inc. Semiconductor device package and acoustic device having the same
US11235404B2 (en) * 2020-03-21 2022-02-01 International Business Machines Corporation Personalized copper block for selective solder removal
EP4161222A4 (en) 2020-05-26 2024-07-10 LG Innotek Co., Ltd. PACKAGING SUBSTRATE
US11844178B2 (en) 2020-06-02 2023-12-12 Analog Devices International Unlimited Company Electronic component
US11476128B2 (en) 2020-08-25 2022-10-18 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
CN117199053A (zh) * 2022-06-01 2023-12-08 长鑫存储技术有限公司 封装结构及其制作方法、半导体器件
WO2025121102A1 (ja) * 2023-12-04 2025-06-12 株式会社村田製作所 回路モジュール

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3361881B2 (ja) * 1994-04-28 2003-01-07 株式会社東芝 半導体装置とその製造方法
US5912510A (en) * 1996-05-29 1999-06-15 Motorola, Inc. Bonding structure for an electronic device
JP4564113B2 (ja) * 1998-11-30 2010-10-20 株式会社東芝 微粒子膜形成方法
TW464927B (en) * 2000-08-29 2001-11-21 Unipac Optoelectronics Corp Metal bump with an insulating sidewall and method of fabricating thereof
US6683375B2 (en) * 2001-06-15 2004-01-27 Fairchild Semiconductor Corporation Semiconductor die including conductive columns
US20030006062A1 (en) * 2001-07-06 2003-01-09 Stone William M. Interconnect system and method of fabrication
JP2003069181A (ja) * 2001-08-28 2003-03-07 Mitsubishi Electric Corp 電子機器装置及びその製造方法
TWI245402B (en) * 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
US7749886B2 (en) * 2006-12-20 2010-07-06 Tessera, Inc. Microelectronic assemblies having compliancy and methods therefor
DE102009010885B4 (de) * 2009-02-27 2014-12-31 Advanced Micro Devices, Inc. Metallisierungssystem eines Halbleiterbauelements mit Metallsäulen mit einem kleineren Durchmesser an der Unterseite und Herstellungsverfahren dafür
US8383457B2 (en) * 2010-09-03 2013-02-26 Stats Chippac, Ltd. Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect
US8982107B2 (en) * 2010-05-24 2015-03-17 Sharp Kabushiki Kaisha Scanning signal line drive circuit and display device provided with same
US8580607B2 (en) * 2010-07-27 2013-11-12 Tessera, Inc. Microelectronic packages with nanoparticle joining
US9202715B2 (en) * 2010-11-16 2015-12-01 Stats Chippac Ltd. Integrated circuit packaging system with connection structure and method of manufacture thereof
US8610285B2 (en) * 2011-05-30 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. 3D IC packaging structures and methods with a metal pillar
US8535983B2 (en) * 2011-06-02 2013-09-17 Infineon Technologies Ag Method of manufacturing a semiconductor device
US20130099371A1 (en) 2011-10-21 2013-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package having solder jointed region with controlled ag content
TW201401456A (zh) * 2012-06-19 2014-01-01 矽品精密工業股份有限公司 基板結構與封裝結構
CN105230135B (zh) 2013-05-21 2018-04-20 株式会社村田制作所 模块
TWI517318B (zh) 2013-06-14 2016-01-11 日月光半導體製造股份有限公司 具金屬柱組之基板及具金屬柱組之封裝結構
TWI567902B (zh) 2013-06-14 2017-01-21 日月光半導體製造股份有限公司 具定位組之基板組
US9478485B2 (en) * 2013-06-28 2016-10-25 STATS ChipPAC Pte. Ltd. Semiconductor device and method of stacking semiconductor die on a fan-out WLCSP
US9653442B2 (en) * 2014-01-17 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and methods of forming same
CN106463472B (zh) * 2014-06-27 2019-10-11 索尼公司 半导体器件及制造其的方法
US10049893B2 (en) * 2016-05-11 2018-08-14 Advanced Semiconductor Engineering, Inc. Semiconductor device with a conductive post

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US10446411B2 (en) 2019-10-15
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CN107424970A (zh) 2017-12-01
US20170330870A1 (en) 2017-11-16
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