JP6416822B2 - 薄膜トランジスタ及びそれを含む表示装置のバックプレーン基板 - Google Patents
薄膜トランジスタ及びそれを含む表示装置のバックプレーン基板 Download PDFInfo
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- 239000010409 thin film Substances 0.000 title claims description 62
- 239000000758 substrate Substances 0.000 title claims description 60
- 239000010410 layer Substances 0.000 claims description 106
- 239000010408 film Substances 0.000 claims description 64
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 36
- 239000004973 liquid crystal related substance Substances 0.000 claims description 6
- 239000002356 single layer Substances 0.000 claims description 6
- 239000011159 matrix material Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 claims 2
- 238000000034 method Methods 0.000 description 47
- 238000005530 etching Methods 0.000 description 26
- 239000002184 metal Substances 0.000 description 21
- 238000002425 crystallisation Methods 0.000 description 14
- 230000008025 crystallization Effects 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- 229910021417 amorphous silicon Inorganic materials 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 10
- 238000001878 scanning electron micrograph Methods 0.000 description 10
- 238000001816 cooling Methods 0.000 description 8
- 238000001312 dry etching Methods 0.000 description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 238000005499 laser crystallization Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 5
- 238000005054 agglomeration Methods 0.000 description 4
- 230000002776 aggregation Effects 0.000 description 4
- 238000004380 ashing Methods 0.000 description 4
- 239000012467 final product Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 235000010599 Verbascum thapsus Nutrition 0.000 description 2
- 244000178289 Verbascum thapsus Species 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229910001092 metal group alloy Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
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- 238000009413 insulation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
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- 238000009751 slip forming Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
- H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
Description
図5Aは、本発明の第1実施例に係る薄膜トランジスタのシリコン層を形成した直後の状態を示す平面図である。図5Bは、図5Aの平面図のI−I’線に沿った断面図である。図6は、本発明の第1実施例に係る薄膜トランジスタのシリコン層のレーザー結晶化後の状態を示す断面図(図5AのI−I’線に沿った断面図)である。図7は、本発明の第1実施例に係る薄膜トランジスタを示す断面図(図5AのI−I’線に沿った断面図)である。
図10Aは、本発明の第2実施例に係る薄膜トランジスタのシリコン層を形成した直後の状態を示す平面図である。図10Bは、図10Aの平面図のII−II’線に沿った断面図である。図11は、本発明の第2実施例に係る薄膜トランジスタのシリコン層のレーザー結晶化後の状態を示す断面図(II−II’線に沿った断面図)である。図12は、本発明の第2実施例に係る薄膜トランジスタを示す断面図(II−II’線に沿った断面図)である。
210,310 ゲート電極
210a,310a 平坦部
210b,310b 傾斜部
220,320 ゲート絶縁膜
2300,3300 非晶質シリコン
230,330 アクティブ層
240,340 層間絶縁膜
250,350 ソース電極
260,360 ドレイン電極
Claims (17)
- 基板と、
前記基板上に設けられ、平坦部及び前記平坦部の側部に傾斜部を有し、前記傾斜部の横幅(a)と高さ(h)との比(h/a)が1.192以下である、単層且つ単一の材料で形成されたゲート電極と、
前記基板上に配置され、前記ゲート電極を覆い、該ゲート電極の平坦部よりも薄く形成されたゲート絶縁膜と、
前記ゲート絶縁膜上に設けられ、前記ゲート電極の上方に位置する多結晶シリコンのアクティブ層と、
前記アクティブ層の両端に接続されたソース電極及びドレイン電極と、
を含み、
前記傾斜部は、
前記基板に隣接して設けられ、前記基板の面に対して第1角度をなす傾斜面及び第1の高さ(h1)を有する第1傾斜部と、
前記第1傾斜部の上に設けられ、前記基板の面に対して第2角度をなす傾斜面及び前記第1の高さよりも大きい第2の高さ(h2)を有する第2傾斜部と、
を含む、
薄膜トランジスタ。 - 前記傾斜部の傾斜面の前記基板の面に対する角度は2°〜50°の範囲である、請求項1に記載の薄膜トランジスタ。
- 前記ゲート電極の前記平坦部の厚さは、前記傾斜部の高さ(h)と実質的に等しく、少なくとも1000Åである、請求項1又は2に記載の薄膜トランジスタ。
- 前記ゲート絶縁膜及び前記アクティブ層は、前記ゲート電極の前記平坦部及び前記傾斜部を覆うように形成されている、請求項1乃至3のいずれか1項に記載の薄膜トランジスタ。
- 前記第1角度は前記第2角度よりも大きい、請求項1に記載の薄膜トランジスタ。
- 前記第1傾斜部は、前記ゲート電極の前記平坦部の厚さの1/2以下である、請求項5に記載の薄膜トランジスタ。
- 前記第2角度は2°〜50°の範囲である、請求項6に記載の薄膜トランジスタ。
- マトリクス状に区分された複数の画素を有する基板を有し、
前記複数の画素のうちの少なくとも一つは、
前記基板上に設けられ、平坦部及び前記平坦部の側部に傾斜部を有し、前記傾斜部の横幅(a)と高さ(h)との比(h/a)が1.192以下である、単層且つ単一の材料で形成されたゲート電極と、
前記基板上に配置され、前記ゲート電極を覆い、該ゲート電極の平坦部よりも薄く形成されたゲート絶縁膜と、
前記ゲート絶縁膜上に設けられ、前記ゲート電極の上方に位置する多結晶シリコンのアクティブ層と、
前記アクティブ層の両端に接続されたソース電極及びドレイン電極と、
を含み、
前記傾斜部は、
前記基板に隣接して設けられ、前記基板の面に対して第1角度をなす傾斜面及び第1の高さ(h1)を有する第1傾斜部と、
前記第1傾斜部の上に設けられ、前記基板の面に対して第2角度をなす傾斜面及び前記第1の高さよりも大きい第2の高さ(h2)を有する第2傾斜部と、
を含む、
表示装置のバックプレーン基板。 - 前記傾斜部の傾斜面の前記基板の面に対する角度は2°〜50°の範囲である、請求項8に記載のバックプレーン基板。
- 前記ゲート電極の前記平坦部の厚さは、前記傾斜部の高さ(h)と実質的に等しく、少なくとも1000Åである、請求項8又は9に記載のバックプレーン基板。
- 前記ゲート絶縁膜及び前記アクティブ層は、前記ゲート電極の前記平坦部及び前記傾斜部を覆うように形成されている、請求項8乃至10のいずれか1項に記載のバックプレーン基板。
- 前記第1角度は前記第2角度よりも大きい、請求項8に記載のバックプレーン基板。
- 前記第1傾斜部は、前記ゲート電極の前記平坦部の厚さの1/2以下である、請求項12に記載のバックプレーン基板。
- 前記第2角度は2°〜50°の範囲である、請求項13に記載のバックプレーン基板。
- 請求項8乃至14のいずれか1項に記載のバックプレーン基板を備え、液晶表示装置又は有機発光表示装置である、表示装置。
- 前記表示装置は、液晶表示装置であり、前記画素は、前記ドレイン電極に接続された画素電極を更に有する、請求項15に記載の表示装置。
- 前記表示装置は、有機発光表示装置であり、前記画素は、有機発光ダイオードを有し、前記ドレイン電極は、前記有機発光ダイオードの第1の電極を構成する、請求項15に記載の表示装置。
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KR1020150067321A KR102430573B1 (ko) | 2015-05-14 | 2015-05-14 | 박막 트랜지스터 및 이를 포함한 백플레인 기판 |
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CN109244081B (zh) * | 2018-08-30 | 2021-06-22 | 武汉华星光电半导体显示技术有限公司 | 阵列基板及显示面板 |
KR102598061B1 (ko) * | 2018-09-03 | 2023-11-03 | 삼성디스플레이 주식회사 | 유기 발광 표시 장치 및 그 제조 방법 |
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JPH10229197A (ja) * | 1997-02-17 | 1998-08-25 | Sanyo Electric Co Ltd | 薄膜トランジスタ、薄膜トランジスタの製造方法 |
TW400556B (en) | 1997-02-26 | 2000-08-01 | Samsung Electronics Co Ltd | Composition for a wiring, a wiring using the composition, a manufacturing method thereof, a display using the wiring and a manufacturing method thereof |
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JPH11111997A (ja) | 1997-10-06 | 1999-04-23 | Sanyo Electric Co Ltd | 薄膜トランジスタ |
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US6365917B1 (en) | 1998-11-25 | 2002-04-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
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JP2001035808A (ja) * | 1999-07-22 | 2001-02-09 | Semiconductor Energy Lab Co Ltd | 配線およびその作製方法、この配線を備えた半導体装置、ドライエッチング方法 |
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TWI306311B (en) | 2002-06-21 | 2009-02-11 | Sanyo Electric Co | Thin film transistor and method for producing thin film transistor |
JP2004031409A (ja) | 2002-06-21 | 2004-01-29 | Sanyo Electric Co Ltd | 薄膜トランジスタの製造方法 |
KR100543001B1 (ko) | 2003-09-03 | 2006-01-20 | 삼성에스디아이 주식회사 | 박막 트랜지스터 및 액티브 매트릭스 평판 표시 장치 |
KR101087398B1 (ko) * | 2004-06-30 | 2011-11-25 | 엘지디스플레이 주식회사 | 액정표시장치의 패드 구조 및 그 제조방법 |
JP2007294672A (ja) | 2006-04-25 | 2007-11-08 | Mitsubishi Electric Corp | 配線基板、表示装置及びそれらの製造方法 |
TWI574423B (zh) | 2008-11-07 | 2017-03-11 | 半導體能源研究所股份有限公司 | 半導體裝置和其製造方法 |
KR101570347B1 (ko) * | 2008-11-25 | 2015-11-20 | 삼성디스플레이 주식회사 | 박막 트랜지스터 표시판 및 그 제조 방법 |
IN2012DN05057A (ja) | 2009-12-28 | 2015-10-09 | Semiconductor Energy Lab | |
WO2012102314A1 (en) * | 2011-01-28 | 2012-08-02 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device and semiconductor device |
KR20130017034A (ko) * | 2011-08-09 | 2013-02-19 | 엘지디스플레이 주식회사 | 박막트랜지스터 어레이 기판 및 그 제조방법 |
TWI605590B (zh) * | 2011-09-29 | 2017-11-11 | 半導體能源研究所股份有限公司 | 半導體裝置及其製造方法 |
JP6021586B2 (ja) * | 2012-10-17 | 2016-11-09 | 株式会社半導体エネルギー研究所 | 半導体装置 |
CN104157699B (zh) | 2014-08-06 | 2019-02-01 | 北京大学深圳研究生院 | 一种背沟道刻蚀型薄膜晶体管及其制备方法 |
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US20160336419A1 (en) | 2016-11-17 |
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