JP6184352B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6184352B2 JP6184352B2 JP2014052704A JP2014052704A JP6184352B2 JP 6184352 B2 JP6184352 B2 JP 6184352B2 JP 2014052704 A JP2014052704 A JP 2014052704A JP 2014052704 A JP2014052704 A JP 2014052704A JP 6184352 B2 JP6184352 B2 JP 6184352B2
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Description
図1は、第1実施形態に係る半導体装置の模式的立体図である。
図3(a)および図3(b)は、第1実施形態に係る半導体装置のオン状態の動作を表す模式的断面図である。
例えば、接続領域11aおよび絶縁層12の組をトレンチ領域と呼称した場合、半導体装置1Aは、このトレンチ領域の下端において、トレンチ領域と半導体層21との接合部が急峻に曲がる角部13を有している。この角部13にはリカバリー時に電界が集中し易くなる。これにより、角部13の付近でアバランシェが起き易くなる。アバランシェによって発生した正孔(h)の流れをアバランシェ電流17とする。
図5(a)および図5(b)は、第1実施形態の第1変形例に係る半導体装置の模式的断面図であり、図5(c)は、その半導体装置の模式的平面図であり、図5(d)は、第1変形例のさらに別の半導体装置の模式的平面図である。
図6(a)および図6(b)は、第1実施形態の第2変形例に係る半導体装置の模式的断面図である。
半導体領域31が接続領域11aの両側の一方の側に設けられ、他方の側に設けられていない構造は、上記の構造に限られない。
図8は、第2実施形態に係る半導体装置の模式的立体図である。
図9(a)は、第2実施形態に係る半導体装置の模式的断面図であり、図9(b)は、第2実施形態に係る半導体装置の模式的平面図である。
図10(a)および図10(b)は、第2実施形態に係る半導体装置のオン状態の動作を表す模式的断面図である。
図12は、参考例に係る半導体装置のリカバリー状態の動作を表す模式的断面図である。
以下に説明する半導体装置は、カソード電極10と、アノード電極11と、半導体層20と、半導体層21と、半導体領域30と、半導体領域31と、接続領域11aと、絶縁層12と、を備えている。それぞれの変形した箇所について説明する。
図13(a)および図13(b)は、第2実施形態の第1変形例に係る半導体装置の模式的断面図であり、図13(c)は、その半導体装置の模式的平面図である。
図14(a)および図14(b)は、第2実施形態の第2変形例に係る半導体装置の模式的断面図である。
半導体領域31が接続領域11aの両側の一方の側に設けられ、他方の側に設けられていない構造は、上記の構造に限られない。
図16(a)は、第3実施形態に係る半導体装置の模式的断面図であり、図16(b)は、第3実施形態に係る半導体装置の模式的平面図である。
図17(a)は、第3実施形態の変形例に係る半導体装置の模式的断面図であり、図17(b)は、第3実施形態の変形例に係る半導体装置の模式的平面図である。
図18は、第4実施形態に係る半導体装置の模式的平面図である。
図18には、チップ状になった半導体装置1A〜3Bの模式的平面が表されている。半導体装置1A〜3Bのそれぞれは、活性領域95と、活性領域95を取り囲む周辺領域96と、を備える。ここで、活性領域95とは、半導体装置が素子(ダイオード)として機能することが可能な領域である。
上述した半導体装置1A〜3Bは、IGBTと複合させることができる。
一例として、半導体装置1Aと半導体装置2AとIGBTと複合させた形態を、図19、20に示す。
半導体装置4Bにおいては、半導体領域30の第2領域部は、半導体層21の第2領域部とアノード電極11との間に設けられ、アノード電極11にショットキー接触している。複数の接続領域11aは、アノード電極11に接し、アノード電極11から半導体層21にまで達している。Y方向において、複数の接続領域11aの配列ピッチは、複数のゲート電極40の配列ピッチよりも広くなっている。
Claims (12)
- 第1電極と、
第2電極と、
前記第1電極と前記第2電極との間に設けられ、前記第1電極に接する第1導電形の第1半導体層と、
前記第1半導体層と前記第2電極との間に設けられ、一部が前記第2電極に接する第2導電形の第1半導体領域と、
前記第1半導体領域と前記第2電極との間に設けられ、前記第2電極に接し、前記第1半導体領域の不純物濃度よりも不純物濃度が高い第2導電形の第2半導体領域と、
一端が前記第2電極に接し、他端が前記第1半導体層に位置し、前記第2電極に沿って前記第1電極から前記第2電極に向かう第1方向に延在する絶縁層と、
前記第2電極に接し、前記第2電極から前記第1半導体層にまで達し、前記第1方向に交差する第2方向に延在する領域と、
を備え、
前記第1半導体領域は、前記第2電極に接しない部分において、前記第1半導体層と前記第2半導体領域との間に設けられ、
前記第1半導体領域及び前記第2半導体領域は、前記第2電極に接する部分において、前記第2方向に沿って交互に配置され、
前記第1方向および前記第2方向に交差する第3方向において、前記絶縁層は、前記第2半導体領域と前記領域の間に設けられ、
前記第2半導体領域の少なくとも一部は、前記絶縁層に接している半導体装置。 - 前記第2半導体領域は、前記第2方向において複数の領域に分割されている請求項1記載の半導体装置。
- 前記延在する領域と前記第1半導体層との間および前記延在する領域と前記第1半導体領域との間に前記絶縁層が設けられている請求項1または2に記載の半導体装置。
- 前記延在する領域は、前記絶縁層に接している請求項1〜3のいずれか1つに記載の半導体装置。
- 前記第2半導体領域の不純物濃度の最大値は、3×1017cm−3以上である請求項1〜4のいずれか1つに記載の半導体装置。
- 前記第1半導体領域の不純物濃度の最大値は、3×1017cm−3未満である請求項1〜5のいずれか1つに記載の半導体装置。
- 第1電極と、
第2電極と、
前記第1電極と前記第2電極との間に設けられ、前記第1電極に接する第1導電形の第1半導体層と、
前記第1半導体層と前記第2電極との間に設けられ、不純物濃度の最大値が3×1017cm−3未満である第2導電形の第1半導体領域と、
一端が前記第2電極に接し、他端が前記第1半導体層に位置し、前記第2電極に沿って前記第1電極から前記第2電極に向かう第1方向に延在する絶縁層と、
前記第1半導体領域と前記第2電極との間に設けられ、前記絶縁層に接し、前記第1半導体領域の不純物濃度よりも不純物濃度が高く、不純物濃度の最大値が3×1017cm−3以上である第2導電形の第2半導体領域と、
前記第2電極に接し、前記第2電極から前記第1半導体層にまで達し、前記第1方向に交差する第2方向に延在する領域と、
を備え、
前記第2半導体領域は、前記第2電極に沿って、前記第2方向に延在し、
前記第1方向および前記第2方向に交差する第3方向において、前記絶縁層は、前記第2半導体領域と前記領域の間に設けられ、
前記第2半導体領域の少なくとも一部は、前記絶縁層に接している半導体装置。 - 前記領域と前記第1半導体層との間および前記領域と前記第1半導体領域との間に前記絶縁層が設けられている請求項7記載の半導体装置。
- 前記絶縁層は、前記第2方向に延在している請求項7または8に記載の半導体装置。
- 前記絶縁層は、前記第2方向に延在し、
前記第2半導体領域は、前記第2方向に延在する第1領域と、前記第3方向に延在する第2領域と、を有している請求項7または8に記載の半導体装置。 - 前記第1方向における前記第1半導体領域の不純物濃度プロファイルのピークは、前記第2電極と前記第1半導体層との間に位置している請求項7〜10のいずれか1つに記載の半導体装置。
- 前記第2半導体領域は、前記領域の前記第3方向両側の一方の側に設けられ、他方の側に設けられていない請求項7〜11のいずれか1つに記載の半導体装置。
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